JPH02260059A - Bus control system for computer - Google Patents

Abstract

PURPOSE:To carry out the input/output of data without latching the data on a system bus by securing a constitution where a local bus controller supplies a bus cycle and signal to a CPU in response to a system bus end signal. CONSTITUTION:A system bus controller 7 supplies the data read signal 12 to the circuits 14 and 15 set on a system bus 11 respectively in response to a system bus cycle request signal 5 which is received from a local bus controller 4 in response to a bus cycle request signal 2 received from a CPU 1. Then the data are outputted to the bus 11. At the same time, the controller 7 outputs a system bus cycle end signal 6 to the controller 4 after a prescribed access time while keeping the signal 12 active. The controller 4 supplies a bus cycle end signal 3 to the CPU 1 in response to the signal 6 and reads the data on the circuits 14 and 15 via the buses 11 and 8 respectively. As a result, the CPU 1 can perform the input/output of data without latching the data on the bus 11.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a computer bus control system, and particularly relates to a local bus that connects a main memory to a central processing unit (CPU) and a local bus that connects each peripheral circuit to the local bus. In a small computer bus consisting of two system buses, if both buses are controlled by asynchronous clocks, the CPU cannot input or output data without latching the data on the system bus when the CPU finishes accessing the system bus. Concerning improvements to make it more effective.

[Summary of the Invention] In a computer system that inputs and outputs data between a main memory, each peripheral circuit, and a CPU using a local bus and a system bus, the local bus controller and the system bus controller control both buses using asynchronous clocks. This bus control system allows the CPU to read data from each peripheral circuit without latching it at the end of the CPU's access to the system bus.

[Prior Art] Conventionally, in order for a CPU to access a local bus and a system bus, a bus controller synchronized with the CPU clock is configured to read/write data. In addition, if the resources on the system bus (memory, I10 controller, etc.) are slower than the access speed of the CPU, this is handled by applying a wait circuit that extends one CPU bus cycle by a clock unit or by a certain period of time. In particular, in order to ensure compatibility between controllers and bus masters on the system bus, the system bus controller operates using a clock that is asynchronous to the CPU clock. In this case, when accessing the system bus, read/write control signals to the system bus are generated in synchronization with the asynchronous clock.

For this reason, it is necessary to secure the data until the CPU reads the data in the CPU read cycle, so the data is latched using a transparent latch or flip-flop, and the system bus read/write control signal is output. After finishing.

A method is used in which the wait state of the CPU is released and the data latched externally is made to be read by the CPU.

[Problems to be Solved by the Invention] However, according to such a conventional system, the CPU clock is generated by a read signal generated by a clock asynchronous to the CPU clock.
An external latch must be used to secure the data until the U data read timing. It is impossible to construct the circuit with a buffer with a register, and an increase in the number of parts will inevitably lead to an increase in cost and an increase in board space.

[Object of the Invention] Accordingly, an object of the present invention is to provide a bus control method that allows a CPU to input and output data without latching data on a system bus.

[Means for Solving Problem 11] In order to achieve the above object, the present invention provides a computer equipped with a CPU, a local bus, a system bus, a local bus controller, and a system bus controller.
In response to a system bus cycle request signal output by the local bus controller in response to a bus cycle request signal from the CPU, the system bus controller provides a data read signal to each circuit on the system bus and outputs data to the system bus. At the same time, after a specified access time, the system bus controller outputs a system bus cycle end signal to the local bus controller while keeping the data read signal active, and the local bus controller responds to this system bus end signal to
The gist is that a bus cycle end signal is given to U to read data from each of the circuits via the system bus and the local bus.

[Operation] The local bus and the system bus are controlled by asynchronous clocks, and when the CPU finishes accessing the system bus, the data on the system bus is read by the CPU without being latched.

[Examples] The present invention will be described below with reference to examples shown in the drawings. FIG. 1 shows an embodiment of a computer bus control system according to the present invention.

In the figure, 1 is a central processing unit (CPU); 2 is a central processing unit (CPU);
is the bus cycle request signal (STATUS), 3 is the bus cycle end signal, 4 is the local bus controller, 5
is the system bus cycle request signal (ATBUS), 6 is the system bus cycle end signal (ATBRDY), 7 is the system bus controller, 8 is the local bus, 9 is the main memory, 10 is the system bus bidirectional buffer, 11 is the system bus , 12 is a data read signal (RE A D
), 13 is a timing extension request signal (WAIT), 14
is the I10 controller, and 15 is the expansion memory.

I10 controller, 16 is clock generator, 17 is C
PU clock (PCLK), 18 is a system bus clock (REFCK).

When the CPUI reads data from each circuit 14, 15, etc. on the system bus 11.

A bus cycle request signal (usually a CPU I status output) 2 is output to a local bus controller 4 operating in synchronization with a CPU clock 17 output from a clock generator 16. Local bus controller 4 outputs system bus cycle request signal 5 to system bus controller 7 in response to bus cycle request signal 2 .

The system bus controller 7 operates in synchronization with a system bus clock 18 which is asynchronous with the CPU clock 17 output from the clock generator 16, and responds to the system cycle request signal 5 by clocking the I10 on the system bus 11.
A data read signal 12 is output to the controller 14, expansion memory/extension I10 controller 15, and the like. I
10 controller 14 and the like output the data currently addressed to the system bus 11 by the data read signal 12. Furthermore, if the access time of the I10 controller 14 or the like is slow, each peripheral circuit can output a timing extension request signal 13 to the system bus controller 7 to extend the time of the data read signal 12.

In this way, after a specified access time, data is loaded onto the system bus 11, and the data is delivered from each peripheral circuit to the CPU on the local bus 8 via the bidirectional buffer 10. Since the timing of reading data on the bus 8 is controlled by the CPU clock 17, the system bus controller 7, which operates with a clock asynchronous to the CPU clock 17, keeps the data read signal 12 active even after the specified access time. local bus controller 4 while holding
The system bus cycle end signal 6 is outputted to.

When the local bus controller 4 confirms the system bus cycle end signal 6, it activates the bus cycle end signal 3 to the CPUI. During this bus cycle,
The CPUI, which has been waiting in a wait state, reads the data. At this time, the system bus controller 7 also monitors the bus cycle end signal 3 and turns off the data read signal 12, which has been kept active.

This completes the bus cycle in which the CPU reads read data on the system bus 11 requested by the CPU.

FIG. 2 shows a timing chart of the cycle of the bus control method described above.

[Effects of the Invention] As explained above, according to the present invention, since the above-described bus control method is adopted, there is no need to latch data on the system bus, and the system bus buffer circuit can be simplified.

Additionally, the number of signals used for system bus buffer control can be reduced. Therefore, for example, when implementing a system bus controller and a local bus controller into LSI, the number of external signal bins for controlling buffers is reduced, and valuable LSI pins can be used for other signals.

Furthermore, since the CPU clock and the system bus clock are asynchronous, the operating speed of the CPU can be increased due to advances in devices while maintaining compatibility with the operating speed of the system bus that has existed in the past.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a timing chart for explaining the operation. 1......CPU, 4...Local bus controller, 7...System bus controller, 8...... Local bus, 9...Old...Main memory, 10...Bidirectional buffer, 11...Old...System bus.

Claims (1)

[Claims] A central processing unit; a local bus connected between the central processing unit and main memory; a system bus connected to the local bus via a bidirectional buffer; and a system bus controller that operates asynchronously with the local bus controller to control the system bus, and the local bus controller operates in response to a bus cycle request signal from a central processing unit. In response to the system bus cycle request signal to be output, the system bus controller gives a data read signal to each circuit on the system bus to output data to the system bus, and after a specified access time, the system bus controller A system bus cycle end signal is output to the local bus controller while the data read signal is kept active, and the local bus controller responds to the system bus end signal to give a bus cycle end signal to the central processing unit. A bus control system for a computer, characterized in that data of each of the circuits is read via a system bus and a local bus.