JPH0225538B2 - - Google Patents
Info
- Publication number
- JPH0225538B2 JPH0225538B2 JP56151706A JP15170681A JPH0225538B2 JP H0225538 B2 JPH0225538 B2 JP H0225538B2 JP 56151706 A JP56151706 A JP 56151706A JP 15170681 A JP15170681 A JP 15170681A JP H0225538 B2 JPH0225538 B2 JP H0225538B2
- Authority
- JP
- Japan
- Prior art keywords
- register
- sign
- absolute value
- augend
- addition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15170681A JPS5852747A (ja) | 1981-09-25 | 1981-09-25 | 加減算回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15170681A JPS5852747A (ja) | 1981-09-25 | 1981-09-25 | 加減算回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5852747A JPS5852747A (ja) | 1983-03-29 |
| JPH0225538B2 true JPH0225538B2 (enrdf_load_stackoverflow) | 1990-06-04 |
Family
ID=15524482
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15170681A Granted JPS5852747A (ja) | 1981-09-25 | 1981-09-25 | 加減算回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5852747A (enrdf_load_stackoverflow) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5930143A (ja) * | 1982-08-11 | 1984-02-17 | Hitachi Ltd | 演算処理方式 |
| JPS62212080A (ja) * | 1986-03-12 | 1987-09-18 | Kawasaki Steel Corp | フラツシユバツト溶接機の制御装置 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5647841A (en) * | 1979-09-22 | 1981-04-30 | Kokusai Denshin Denwa Co Ltd <Kdd> | Pcm signal operation system |
-
1981
- 1981-09-25 JP JP15170681A patent/JPS5852747A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5852747A (ja) | 1983-03-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4953115A (en) | Absolute value calculating circuit having a single adder | |
| US4992969A (en) | Integer division circuit provided with a overflow detector circuit | |
| US4503511A (en) | Computing system with multifunctional arithmetic logic unit in single integrated circuit | |
| US4677582A (en) | Operation processing apparatus | |
| JPH0225538B2 (enrdf_load_stackoverflow) | ||
| JPH03135627A (ja) | ファジイ演算装置 | |
| JPH0380324A (ja) | 中央演算処理装置 | |
| JP2520484B2 (ja) | 除算回路 | |
| JP2575856B2 (ja) | 演算回路 | |
| JPS61138334A (ja) | 10進演算処理装置 | |
| JPH0619700B2 (ja) | 演算装置 | |
| JPH0330170B2 (enrdf_load_stackoverflow) | ||
| JPS6188334A (ja) | 除算回路 | |
| JP3110072B2 (ja) | 事前正規化回路 | |
| JP3139011B2 (ja) | 固定小数点プロセッサ | |
| GB857511A (en) | Improvements in or relating to dividing multiplying arrangements for electronic digital computing machines | |
| JP2604667B2 (ja) | 予測機能付き演算装置 | |
| JP2542120B2 (ja) | 情報処理装置 | |
| JPH02178833A (ja) | 異なるビット長のデータを加算する加算器 | |
| JPH0316650B2 (enrdf_load_stackoverflow) | ||
| JPS6118219B2 (enrdf_load_stackoverflow) | ||
| JPS6129020B2 (enrdf_load_stackoverflow) | ||
| JPH01258129A (ja) | 算術論理演算回路 | |
| JPS60140427A (ja) | 10進加減算方式 | |
| JPH03150631A (ja) | 10進除算回路 |