JPH02253714A - Receiver - Google Patents

Receiver

Info

Publication number
JPH02253714A
JPH02253714A JP7379189A JP7379189A JPH02253714A JP H02253714 A JPH02253714 A JP H02253714A JP 7379189 A JP7379189 A JP 7379189A JP 7379189 A JP7379189 A JP 7379189A JP H02253714 A JPH02253714 A JP H02253714A
Authority
JP
Japan
Prior art keywords
voltage
circuit
signal
intermediate frequency
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7379189A
Other languages
Japanese (ja)
Inventor
Akira Isomine
五十嶺 朗
Hiroyuki Nagao
裕之 長尾
Toru Ito
徹 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu General Ltd
Original Assignee
Fujitsu General Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu General Ltd filed Critical Fujitsu General Ltd
Priority to JP7379189A priority Critical patent/JPH02253714A/en
Publication of JPH02253714A publication Critical patent/JPH02253714A/en
Pending legal-status Critical Current

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  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Abstract

PURPOSE:To exactly execute a search stop by providing a first logic circuit to AND between the zero point detection signal of a signoidal characteristic voltage, which is obtained from an FM frequency detection signal, and the level detection signal of an intermediate frequency circuit and executing the search stop according to a signal from this first logic circuit. CONSTITUTION:Since a signoidal characteristic voltage Vs is outputted from an FM frequency detection circuit 5 and inputted to comparators 7 and 8, an output voltage Va is made 'L' in the non-inversion comparator 7 when the voltage Vs lower than a reference voltage V1 is inputted. Then, in the inversion comparator 8, when the voltage Vs higher than a reference voltage V2 in inputted, an output voltage Vb is made 'L'. In an intermediate frequency circuit 4, when an intermediate frequency signal effectively exists, the level of a voltage Vc in a terminal 4a is lowered to 'L'. Thus, a pulse Vd showing a central frequency can be extremely exactly taken out by suitably setting the reference voltages V1 and V2 of the comparators 7 and 8 and the search stop can be exactly executed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、サーチ機能を有する受信装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a receiving device having a search function.

(従来の技術〕 この種の受信装置では、選局周波数(局部発振周波数)
を連続変化(サーチ)させて、放送を受信した時点でそ
のサーチを停止させるサーチ機構が採用されている。そ
してこのサーチ停止は、FM検波回路から取り出した8
字特性の電圧の零点を検出して行っている。
(Prior art) In this type of receiving device, the tuning frequency (local oscillation frequency)
A search mechanism is adopted in which the search is continuously changed (searched) and the search is stopped when a broadcast is received. And this search stop is the 8
This is done by detecting the zero point of the voltage with the characteristic

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながらこのサーチ機構では、8字特性の零点検出
に誤検出が生じ、誤ったサーチ停止が発生し易いという
問題があった。
However, this search mechanism has a problem in that erroneous detection occurs in the zero point detection of the character 8 characteristic, and erroneous search stops are likely to occur.

本発明の目的は、サーチ停止を正確に行うことができる
ようにすることである。
An object of the present invention is to enable the search to be stopped accurately.

〔課題を解決するための手段〕[Means to solve the problem]

このために本発明は、サーチ機能を有する受信装置にお
いて、FM検波回路から得られる8字特性電圧の零点検
出信号と、中間周波回路のレベル検出信号との論理積を
とる第1の論理回路を具備し1.該第1の論理回路から
の信号によりサーチ停止を行うように構成した。
To this end, the present invention provides, in a receiver having a search function, a first logic circuit that takes the AND of the zero point detection signal of the figure-8 characteristic voltage obtained from the FM detection circuit and the level detection signal of the intermediate frequency circuit. Equipped with 1. The configuration is such that the search is stopped by a signal from the first logic circuit.

〔実施例〕〔Example〕

以下、本発明の実施例について説明する。第1図はその
一実施例のチェーナ部を示す図である。
Examples of the present invention will be described below. FIG. 1 is a diagram showing a chainer portion of one embodiment.

lは高周波信号(5〜8.5 MHz)の信号を増幅す
る高周波増幅回路、2はその増幅回路1からの周波数信
号とPL’L回路3からの局部発振周波数信号とを混合
して10.7M)Izの中間周波信号を取り出す混合回
路、4は中間周波増幅回路、5はFM検波回路である。
1 is a high frequency amplifier circuit that amplifies a high frequency signal (5 to 8.5 MHz); 2 is a high frequency amplifier circuit that amplifies a high frequency signal (5 to 8.5 MHz); 7M) A mixing circuit for extracting an intermediate frequency signal of Iz, 4 is an intermediate frequency amplification circuit, and 5 is an FM detection circuit.

上記PLL回路3はマイクロコンピュータからなる制御
部6によって、内部の分周回路の分周率が変化され、混
合回路2に出力する周波数を変化させる。7はFM検波
回路5で得られるS字特定電圧Vsを基準電圧v1で比
較する非反転コンパレータ、8は同S字特定電圧Vsを
基準電圧■2で比較する反転コンパレータである。
In the PLL circuit 3, the frequency division ratio of an internal frequency dividing circuit is changed by a control section 6 made up of a microcomputer, and the frequency output to the mixing circuit 2 is changed. 7 is a non-inverting comparator that compares the S-shaped specific voltage Vs obtained by the FM detection circuit 5 with a reference voltage v1, and 8 is an inverting comparator that compares the S-shaped specific voltage Vs with a reference voltage 2.

9はそのコンパレータ7.8からの出力信号及び上記し
た中間周波回路4の中間周波信号レベル検出端子(レベ
ルメータ接続端子)4aの出力信号の論理積をとるナン
トゲートであり、このナントゲート9からの信号“H”
により、制御回路6がPLL回路3に対するサーチを停
止する。
Reference numeral 9 denotes a Nandts gate that takes the AND of the output signal from the comparator 7.8 and the output signal of the intermediate frequency signal level detection terminal (level meter connection terminal) 4a of the above-mentioned intermediate frequency circuit 4. signal “H”
As a result, the control circuit 6 stops searching for the PLL circuit 3.

さて、上記したFM検波回路5からは、第2図に示すよ
うな8字特性の電圧Vsが出力して、コンパレータ7.
8に入力するので、非反転コンパレータ7においては、
基準電圧■1よりも低い電圧Vsが入力するとその出力
電圧Vaが“L”となり、反転コンパレータ8において
は基準電圧V2よりも高い電圧Vsが印加するとその出
力vbが“L”となる。
Now, the above-mentioned FM detection circuit 5 outputs a voltage Vs having a figure-8 characteristic as shown in FIG.
8, so in the non-inverting comparator 7,
When a voltage Vs lower than the reference voltage 1 is input, the output voltage Va becomes "L", and when a voltage Vs higher than the reference voltage V2 is applied to the inverting comparator 8, the output vb becomes "L".

また、中間周波回路4では、中間周波信号が有効に存在
すれば端子4aの電圧Vcのレベルが“Lゝに低下する
Further, in the intermediate frequency circuit 4, if the intermediate frequency signal is effectively present, the level of the voltage Vc at the terminal 4a decreases to "L".

従って、正規の信号を受信した場合には、ナントゲート
9からは、第2図に示すように、零点の中心周波数を含
むΔfの周波数の範囲を示すパルスVdが出力して制御
部6に取り込まれ、これによりP L L回路3に対し
て周波数変化の停止(サーチ停止)が指令される。
Therefore, when a regular signal is received, the Nantes gate 9 outputs a pulse Vd indicating the frequency range of Δf including the center frequency of the zero point, as shown in FIG. As a result, the PLL circuit 3 is commanded to stop the frequency change (stop the search).

よって、コンパレータ7.8の基準!圧V1、■2を適
宜設定することにより、極めて正確に中心周波数を示す
パルスVdを取り出すことができ、正確なサーチ停止を
行うことができる。
Therefore, the standard for comparator 7.8! By appropriately setting the pressures V1 and (2), it is possible to extract the pulse Vd that indicates the center frequency extremely accurately, and it is possible to accurately stop the search.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、放送を受信した際
の中心周波数を極めて正確に検出することができ、正確
なサーチ停止を行うことができるようになるという利点
がある。
As explained above, according to the present invention, there is an advantage that the center frequency when a broadcast is received can be detected extremely accurately, and the search can be stopped accurately.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のチューナのブロック図、第
2図はその動作説明用のタイミングチャートである。 代理人 弁理士 長 尾 常 明 第2図 +V d H1 L−−」を−一一一
FIG. 1 is a block diagram of a tuner according to an embodiment of the present invention, and FIG. 2 is a timing chart for explaining its operation. Agent Patent Attorney Tsuneaki Nagao Figure 2 +V d H1 L--111

Claims (4)

【特許請求の範囲】[Claims] (1)、サーチ機能を有する受信装置において、FM検
波回路から得られるS字特性電圧の零点検出信号と、中
間周波回路のレベル検出信号との論理積をとる第1の論
理回路を具備し、該第1の論理回路からの信号によりサ
ーチ停止を行うことを特徴とする受信装置。
(1) A receiving device having a search function, comprising a first logic circuit that takes an AND of a zero point detection signal of an S-characteristic voltage obtained from an FM detection circuit and a level detection signal of an intermediate frequency circuit, A receiving device characterized in that a search is stopped by a signal from the first logic circuit.
(2)、上記零点検出のための回路が、上記S字特性電
圧を入力する非反転コンパレータと、同S字特性電圧を
入力する反転コンパレータと、両コンパレータからの出
力の論理積をとる第2の論理回路とからなり、上記非反
転コンパレータの基準電圧と上記反転コンパレータの基
準電圧を上記S字特性電圧の零点から若干ずらした電圧
に設定したことを特徴とする特許請求の範囲第1項記載
の受信装置。
(2) The circuit for zero point detection includes a non-inverting comparator to which the S-characteristic voltage is input, an inverting comparator to which the S-characteristic voltage is input, and a second Claim 1, characterized in that the reference voltage of the non-inverting comparator and the reference voltage of the inverting comparator are set to a voltage slightly shifted from the zero point of the S-characteristic voltage. receiving device.
(3)、上記非反転コンパレータの基準電圧と上記反転
コンパレータの基準電圧を上記S字特性電圧の零点から
反対方向にずらした電圧に設定したことを特徴すとる特
許請求の範囲第1項記載の受信装置。
(3) The reference voltage of the non-inverting comparator and the reference voltage of the inverting comparator are set to voltages shifted in opposite directions from the zero point of the S-characteristic voltage. Receiving device.
(4)、上記中間周波回路のレベル信号信号を、レベル
メータ端子から得ることを特徴とする特許請求の範囲第
1項記載の受信装置。
(4) The receiving device according to claim 1, wherein the level signal of the intermediate frequency circuit is obtained from a level meter terminal.
JP7379189A 1989-03-28 1989-03-28 Receiver Pending JPH02253714A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7379189A JPH02253714A (en) 1989-03-28 1989-03-28 Receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7379189A JPH02253714A (en) 1989-03-28 1989-03-28 Receiver

Publications (1)

Publication Number Publication Date
JPH02253714A true JPH02253714A (en) 1990-10-12

Family

ID=13528368

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7379189A Pending JPH02253714A (en) 1989-03-28 1989-03-28 Receiver

Country Status (1)

Country Link
JP (1) JPH02253714A (en)

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