KR890001481Y1 - Vertical hold circuit of double vertical frequency - Google Patents
Vertical hold circuit of double vertical frequency Download PDFInfo
- Publication number
- KR890001481Y1 KR890001481Y1 KR2019850018229U KR850018229U KR890001481Y1 KR 890001481 Y1 KR890001481 Y1 KR 890001481Y1 KR 2019850018229 U KR2019850018229 U KR 2019850018229U KR 850018229 U KR850018229 U KR 850018229U KR 890001481 Y1 KR890001481 Y1 KR 890001481Y1
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- vertical
- frequency
- resistor
- transistor
- hold
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
- H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
- H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Details Of Television Scanning (AREA)
Abstract
내용 없음.No content.
Description
제1도는 종래의 회로도.1 is a conventional circuit diagram.
제2도는 본 고안의 회로도.2 is a circuit diagram of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
Q1,Q2: 트랜지스터 R2, R3, R4:저항Q 1, Q 2 : Transistors R 2 , R 3 , R 4 : Resistance
M : 모우드신호 입력단자 IC : 수직편향 집적회로M: Mode signal input terminal IC: Vertical deflection integrated circuit
본 고안은 수직주파수가 모니터 내의 수직발진회로에 2중주파수(Dual Frequency)로 인가될 때에 각각의 주파수에 대하여 수직홀드(V-Hold)가 인정되도록 하기위한 2중수직 주파수의 수직홀드 회로에 괸한 것이다.The present invention is applied to the vertical hold circuit of the double vertical frequency to allow the vertical hold (V-Hold) to be recognized for each frequency when the vertical frequency is applied to the vertical oscillator circuit in the monitor. will be.
종래에는 제1도에 나타낸 바와 같이 수직편향 집적회로(IC)의 단자(8), (11)사이에 저항(R1), 가변저항(VR1)과 콘덴서(C1)에 의한 시정수 도안 수직홀드를 유지하도록 구성되었으나, 이는 제1 수직주파수(f1)에 의하여 조정된 회로에 제2수직 주파수(f2)가 입력되면 제1수직주파수(f1)와 제2수직주파수(f2)의 동기 신호차로 인하여 수직홀드가 흐트러지게 되는 결점이 있었다.Conventionally, as shown in FIG. 1 , a time-constant design by a resistor R 1 , a variable resistor VR 1 , and a capacitor C 1 is provided between terminals 8 and 11 of a vertical deflection integrated circuit IC. It has been configured to maintain a vertical hold, which is the first vertical frequency when a second vertical frequency (f 2) is input to the circuit adjusted by (f 1) a first vertical frequency (f 1) and the second vertical frequency (f 2 ), There is a drawback that the vertical hold is disturbed due to the synchronization signal difference of
본 고안은 이러한 점을 감안하여 동기신호차로 인한 수직홀드의 흐트러짐을 방지하여 안정동작을 수행할 수 있도록 안출한 것으로서, 이를 첨부한 도면에 의하여 상세히 설명하면 다음과 같다.The present invention is designed to perform a stable operation by preventing the disturbance of the vertical hold due to the synchronization signal difference in consideration of this point, described in detail by the accompanying drawings as follows.
제2도에서와 같이 모우드신호 입력단자(M)에 저항(R4)을 통하여 트랜지스터 (Q1)의 베이스를 접속하고, 그의 콜렉터에 저항(R3)을 통하여 트랜지스터 (Q2)의 베이스를 접속하며, 상기 트랜지스터(Q2)의 에미터측은 수직편향 집적회로(IC)의 단자 (8)에, 콜렉터측은 단자(11)에 접속하여 구성한 것이다.The connection to the base of the modal signal input transistor (Q 1) through the resistor (R 4) to (M) as shown in Figure 2, and the base of the transistor (Q 2) via the resistor (R 3) in its collector The emitter side of the transistor Q 2 is connected to the terminal 8 of the vertical deflection integrated circuit IC, and the collector side is connected to the terminal 11.
미설명부호 R1은 저항, VR1은 가변저항, C1은 콘덴서이다.Reference numeral R 1 is a resistor, VR 1 is a variable resistor, C 1 is a capacitor.
이와 같이 구성된 본 고안의 작용효과를 설명하면 다음과 같다.Referring to the effect of the present invention configured as described above are as follows.
제1수직주파수(f1)에서는 모우드 신호단자(M)에 로우신호가 인가되어, 트랜지스터(Q1)는 부도통상태이므로트랜지스터(Q2)도 부도통되어 이 경우에는 저항(R1)과 가변저항(VR1)의 직렬합성 저항값에 의하여 수직편향 집적회로(IC)가 동작하게 된다.A first vertical frequency (f 1) in is applied to the low signal to the modal signal terminal (M), the transistor (Q 1) is the default barrel state because the transistor (Q 2) also default barrel in this case the resistance (R 1) and The vertical deflection integrated circuit IC is operated by the series synthesis resistance value of the variable resistor VR 1 .
한편 제2수직주파수(f2)에서는 모우드신호단자(M)에 하이신호가 인가되어, 트랜지스터(Q1)를 도통시키게 되므로 트랜지스터(Q2)도 도통되어 수직편향 집적회로 (IC)의 단자(8), (11)사이의 저항치는 저항(R1)과 가변저항(VR1)의 직렬합성 저항값에 저항(R2)의 병렬합성 저항값으로 된다.On the other hand, at the second vertical frequency f 2 , a high signal is applied to the mode signal terminal M to conduct the transistor Q 1 , so that the transistor Q 2 is also conducting and thus the terminal of the vertical deflection integrated circuit IC ( 8) and (11) is the value of the parallel synthesis resistance of the resistor R 2 to the series synthesis resistance of the resistor R 1 and the variable resistor VR 1 .
즉 제1수직주파수(f1)에서는 저항(R1)+가변저항(VR1)과 콘덴서(C1)에 의한 시정수기간동안 수직홀드를 유지하고, 제2수직주파수(f2)에서는 합성저항과 콘덴서( C1)에 의한 시정수 기간동안 수직홀드를 유지하기 위하여 저항(R1)과 저항(R2)을 제1수직주파수(f1)와 제2수직주파수(f2)에 의하여 설정한 후에 주파수(f1), (f2)의 수직홀드 유지범위가 겹쳐지는 범위에서 가변저항(VR1)값을 조정하게 되면 f2>f1의 관계이므로 제2수직주파수(f2)의 수직홀드의 유진범위가제1수직주파수(f1)의 수직홀드 유지범위를 포함하게 되므로제1수직주파수( f1) 입력모우드에서 주파수(f1)에 비하여 가변저항(VR1)을 조정하여 수직홀드를 안정시키게 되면 제2수직주파수(f2)에서는 가변저항(VR1)을 다시 조정할 필요없이 제1수직주파수(f1) 모우드 신호에 의하여 수직홀드를 안정시키게 되는 것이다.That is, at the first vertical frequency f 1 , the vertical hold is maintained during the time constant period by the resistor R 1 + variable resistor VR 1 and the capacitor C 1 , and the synthesis is performed at the second vertical frequency f 2 . resistance The resistor R 1 and the resistor R 2 are set by the first vertical frequency f 1 and the second vertical frequency f 2 in order to maintain the vertical hold for the time constant by the capacitor and C 1 . After adjusting the value of the variable resistance VR 1 in the range where the vertical hold holding ranges of the frequencies f 1 and f 2 overlap, f 2 > f 1 , so the second vertical frequency f 2 by Eugene range of the vertical hold-adjust the variable resistor (VR 1) than the first vertical frequency of the first vertical frequency, so that a vertical hold holding range (f 1) (f 1) frequency in the input modal (f 1) When the vertical hold is stabilized, at the second vertical frequency f 2 , the vertical hold is stabilized by the first vertical frequency f 1 mode signal without having to adjust the variable resistor VR 1 again.
이와 같이 본 고안은 간단한 회로구성으로서, 수직주파수가, 모니터의 수직발진회로에 2중주파수로 인가 될때에 각각의 주파수에 대하여 수직홀드를 안정시킬 수가 있는 것이다.As described above, the present invention is a simple circuit configuration, and when the vertical frequency is applied as a double frequency to the vertical oscillation circuit of the monitor, the vertical hold can be stabilized for each frequency.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019850018229U KR890001481Y1 (en) | 1985-12-30 | 1985-12-30 | Vertical hold circuit of double vertical frequency |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019850018229U KR890001481Y1 (en) | 1985-12-30 | 1985-12-30 | Vertical hold circuit of double vertical frequency |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR870011522U KR870011522U (en) | 1987-07-18 |
| KR890001481Y1 true KR890001481Y1 (en) | 1989-04-05 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019850018229U KR890001481Y1 (en) | 1985-12-30 | 1985-12-30 | Vertical hold circuit of double vertical frequency |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR890001481Y1 (en) |
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1985
- 1985-12-30 KR KR2019850018229U patent/KR890001481Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR870011522U (en) | 1987-07-18 |
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