JPH02242231A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To prevent the dissolution of the conductive films of source electrodes and drain electrodes by providing a 2nd film having a metal, exclusive of aluminum, on a 1st film having aluminum of the source electrodes and the drain electrodes in such a manner that the end thereof exists on the side inner than the end of the 1st film. CONSTITUTION:The source electrode SD 1 and the drain electrode SD 2 are respectively constituted by successively superposing the conductive films d 1, d 2, d 3 from the lower layer side. A chromium film is used for the conductive film d 1 and an aluminum film for the conductive film d 2. The conductive film d 1 is positioned in such a manner that the end thereof intrudes more largely to the inner side (into a channel region) than the conductive films d 2, d 3 of the upper layers. The end on the channel side of the conductive film d 3 exists on the side inner than the end of the conductive film d 2 and, therefore, the generation of aluminum whiskers is obviated even if there is a misalignment between the conductive films d 2 and d 3. The dissolution of the conductive films d 2, d 3 by the processing liquid in the subsequent stages is thus obviated, and therefore, the deterioration in the property of the liquid crystal LC is obviated.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a liquid crystal display device, and particularly to an active matrix type liquid crystal display device using thin film transistors and the like.

[Prior art] Active matrix type liquid crystal display device. A nonlinear element (switching element) is provided corresponding to each of a plurality of pixel electrodes arranged in a matrix. Theoretically, the liquid crystal in each pixel is constantly activated (duty ratio 1.0), so compared to the so-called simple matrix method that uses a time-division drive method, the active method has better contrast, especially in color. It is becoming an indispensable technology. A typical switching element is a thin film transistor (TPT). In a conventional active matrix color liquid crystal display device, a second conductive film containing aluminum is formed on a first conductive film made of chromium for the source electrode and drain electrode of a thin film transistor, and an ITO film is formed on the second conductive film. (
A third conductive film made of a transparent conductive film is formed, and the end of the second conductive film on the channel side is aligned with the end of the third conductive film on the channel side. Active matrix liquid crystal display devices using TPT include, for example, "12.5-inch active matrix color liquid crystal display with redundant configuration",
Nikkei Electronics, pages 193-210. Published by Nikkei McGraw-Hill, December 15, 1986. [Problems to be Solved by the Invention] However, in such a liquid crystal display device, if there is a misalignment between the second conductive film and the third conductive film, a part of the second conductive film may overlap with the third conductive film. As a result, aluminum whiskers are generated, and the protective film provided on the third conductive film may be peeled off or holes may be formed in the protective film due to the aluminum whiskers. In this case, a processing solution in a subsequent process such as a resist developer for selectively etching the protective film reaches the third conductive film and the second conductive film, and this processing solution causes the third conductive film and the second conductive film to reach the third conductive film and the second conductive film. 2 The conductive film may dissolve and the liquid crystal may change in quality. In addition, the second conductive film and the third
There is no misalignment with the conductive film (because the second conductive film is not covered by the resist when forming the third conductive film, the second conductive film is dissolved by the developer when forming the third conductive film). The present invention has been made to solve the above-mentioned problems, and provides a liquid crystal display device in which the liquid crystal does not change in quality and the conductive films of the source electrode and drain electrode do not dissolve. (Means for Solving the Problem) In order to achieve this object, the present invention provides an active matrix liquid crystal display device in which a thin film transistor and a pixel electrode are constituent elements of a pixel. A second film containing a metal other than aluminum is provided on the first film containing aluminum for the source and drain electrodes of the thin film transistor, and the end of the second film on the channel side is connected to the channel of the first film. [Function] In this liquid crystal display device, a second film containing a metal other than aluminum is provided on the first film containing aluminum, which is the source electrode and drain electrode of the thin film transistor. Since the end of the second film on the channel side is located inside the end of the first film on the channel side, even if there is misalignment between the first film and the second film, 1st
Since the film is covered with the second film, aluminum whiskers are not generated, and the first film is covered with the resist used when forming the second film. [Example] Hereinafter, the configuration of the present invention will be described together with an example in which the present invention is applied to an active matrix color liquid crystal display device. Note that throughout the description of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted. FIG. 1 is a plan view showing one pixel and its surroundings of an active matrix color liquid crystal display device to which the present invention is applied, and FIG. 2A is a cross section taken along the line IIB-nB in FIG. FIG. 2B is a cross-sectional view of the vicinity of the seal portion, and FIG. 2B is a cross-sectional view taken along the NC-NC cutting line in FIG. 1. Moreover, FIG. 3 (main part plan view) shows a plan view when a plurality of pixels shown in FIG. 1 are arranged. (Pixel arrangement) As shown in Figure 1, each pixel is connected to two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL and two adjacent video signal lines (drain signal lines or vertical signal line)D
It is arranged within the area of intersection with L (within the area surrounded by the four signal lines). Each pixel includes a thin film transistor TPT, a pixel electrode ITOI, and an additional capacitor Cadd. The scanning signal lines GL extend in the column direction, and a plurality of scanning signal lines GL are arranged in the row direction. The video signal lines DL extend in the row direction, and a plurality of video signal lines DL are arranged in the column direction. (Overall panel cross-sectional structure) As shown in FIG. 2A, a thin film transistor TPT and a transparent pixel electrode ITOI are formed on the lower transparent glass substrate 5UBI side with respect to the liquid crystal layer LC, and a color filter is formed on the upper transparent glass substrate 5UBZ side. FIL and a light-shielding black matrix pattern BM are formed. The lower transparent glass substrate 5UBl side has, for example, 1.1 [mml
It is made up of a certain thickness. The central part of Figure 2A shows a cross section of one pixel,
The left side shows a cross section of the left edge portion of the transparent glass substrates 5UBI and 5UB2 where external lead wiring is present. The right side shows a cross section of the right edge portion of the transparent glass substrates 5UBI and 5UB2 where no external lead wiring is present. The sealing material SL shown on the left and right sides of FIG. 2A is configured to seal the liquid crystal LC, and is designed to seal the entire periphery of the transparent glass substrates 5UBI and 5UB2 except for the liquid crystal sealing opening (not shown). is formed along. The sealing material SL is made of, for example, epoxy resin. The common transparent pixel electrode ITO2 on the side of the upper transparent glass substrate 5UBZ is connected to an external lead wiring formed on the side of the lower transparent glass substrate 5UBI by a silver paste material SIL at at least one place. This external lead wiring is formed in the same manufacturing process as each of the gate electrode GT, source electrode SDI, and drain electrode SD2 described above. Alignment film ○RII and 0RI2, transparent pixel electrode ITO1
Common transparent pixel electrode IT○, protective film PSV1 and PSV
2. Each layer of the insulating film GI is formed inside the sealing material SL. The polarizing plate POL has a lower transparent glass substrate 5
UBI is formed on each outer surface of the upper transparent glass substrate 5UB2. The liquid crystal LC has a lower alignment film 0R that sets the direction of the liquid crystal molecules.
II and the upper alignment film 0RI2, and sealed by a sealing portion SL. The lower alignment film ○RII is formed on the protective film PSVI on the side of the lower transparent glass substrate 5UBI. On the inner surface (liquid crystal side) of the upper transparent glass substrate 5UB2, a light shielding film BM, a color filter FIL, and a protective film PSV are provided.
2. A common transparent pixel electrode (COM) IrO2 and an upper alignment film RI2 are sequentially laminated. This liquid crystal display device has a lower transparent glass substrate 5UB1 side,
Each layer on the upper transparent glass substrate 5UB2 side is formed separately, and then the upper and lower transparent glass substrates 5UBI and 5
It is assembled by overlapping the UB2 and sealing the liquid crystal LC between them. (Thin film transistor TPT> The thin film transistor TPT operates in such a way that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and drain becomes small, and when the bias is reduced to zero, the channel resistance becomes large.Thin film transistor of each pixel TPT is 3 within a pixel.
It is divided into two (plurality) of thin film transistors (divided thin film transistors) TFTI, TFT2, and TFT3. Each of the thin film transistors TPTI to TFT3 has substantially the same size (channel length and width are the same). Each of the divided thin film transistors TPTI to TFT3 mainly includes a gate electrode GT, a gate insulating film G1 . Type I (intrinsic, 1ntrins)
ic, an i-type semiconductor JliAS made of amorphous silicon (Si) (not doped with conductivity type determining impurities), a pair of source electrode SDI and drain electrode SD2. Note that the source and drain I are originally determined by the bias polarity between them, and in the circuit of this display device, the polarity is reversed during operation, so it is understood that the source and drain are interchanged during operation. However, in the following explanation as well, for convenience, one side is fixed as a source and the other side is fixed as a drain. (Gate electrode GT> The gate electrode GT is as shown in detail in FIG. 4 (plan view depicting only layers g1, g2 and AS in FIG. 1).
It is configured in a shape that projects vertically (upward in FIGS. 1 and 4) from the scanning signal line GL (branched into a T-shape (v)). Gate electrode GT is thin film transistor TPTI~TFT
It is configured to protrude to each formation region of No. 3. The gate electrodes GTu± of the thin film transistors TPTI to TFT3 are integrally formed (as a common gate electrode), and are formed continuously with the scanning signal line GL. The gate electrode GT is a thin film transistor T
(No large steps are created in the PT formation region.) The first conductive film g1 is made of a single layer. First conductive film g
1 is formed using a chromium (Cr) film formed by sputtering, for example, to a thickness of about 1000 [layers]. As shown in FIGS. 1, 2A, and 4, the gate electrode GT is formed to be thicker than the semiconductor J15AS so as to completely cover it (as viewed from below). Therefore, when a backlight BL such as a fluorescent lamp is installed below the substrate 5UBI, this opaque Cr gate electrode G
Since T forms a shadow, the semiconductor layer As is not irradiated with backlight light, and a conductive phenomenon, that is, deterioration of the off-characteristics of the TPT due to light irradiation is less likely to occur. Note that the original size of the gate electrode GT is the minimum required size to span between the source/drain electrodes SDI and SD2 (including the alignment margin between the gate electrode and the source/drain electrodes), and the channel @ The depth length that determines W is determined by the ratio to the distance (channel length) L between the source and drain electrodes, that is, the factor W/L that determines the mutual conductance ga. The size of the gate electrode in this embodiment is of course larger than the original size mentioned above. Considering only the functional aspects of the gate and light shielding of the gate electrode GT, the gate electrode GT and the scanning signal line GL may be integrally formed in a single layer, and in this case, Si is contained as an opaque conductive material. A1, pure A1. A1 or the like containing Pd can be selected. (Scanning Signal Line OL> The scanning signal line OL is composed of a composite film consisting of a first conductive film g1 and a second conductive film g2 provided on top of the first conductive film g1. g1 is formed in the same manufacturing process as the first conductive film g1 of the gate electrode GT, and is configured integrally with the first conductive film g1.The second conductive film g2 is
For example, sputtered aluminum (A I
) [ is used to form a film with a thickness of about 100 to 5500 [human thickness]. The second conductive film g2 is configured to reduce the resistance value of the scanning signal line GL and increase the signal transmission speed (improve the writing characteristics of pixel information). Furthermore, in the scanning signal line OL, the width of the second conductive film g2 is smaller than the width of the first conductive film g1. That is, the scanning signal line GL has a gradual step shape on its side wall. (Gate insulating film GI> The insulating film GI is used as a gate insulating film for each of the thin film transistors TPTI to TFT3. Insulating film GI
is formed in the upper layer of the gate electrode GT, the scanning signal, and 1iGL. , 11! ! The lamina GI is. For example, a silicon nitride film formed by plasma CVD is used to have a film thickness of about 3000 [in]. (Semiconductor layer AS> As shown in FIG. 4, the i-type semiconductor layer AS is used as a channel formation region for each of the thin film transistors TPTI to TFT3 divided into a plurality of parts.I-type semiconductor layer A
S is formed of an amorphous silicon film or a polycrystalline silicon film, and is formed to have a film thickness of about 1800 C. This i-type semiconductor layer AS is made of Si by changing the components of the supplied gas.
3N, successively to the formation of the gate insulating film GI, it is formed in the same plasma CVD apparatus without being exposed to the outside from the apparatus. Also, P for ohmic contact
N''1dQ doped with (FIG. 2A) is similarly formed continuously to a thickness of approximately 400 mm.Then, the lower substrate 5UB1 is taken out from the cD device and subjected to photo processing technology. Accordingly, the N+ layer do and i/l AS are patterned into independent islands as shown in FIGS. 1, 2A, and 4. The i-type semiconductor layer AS is patterned as shown in FIGS. As shown in detail, the intersection of the scanning signal line GL and the video signal line DL (
The cross-over section) is also provided between the two. This intersection i-type semiconductor, IIAS, is configured to reduce short circuits between the scanning signal gGL and the video signal line DL at the intersection. (Source/drain electrode SDI, 5D23>The source electrode SDI and drain electrode SD2 of each of the thin film transistors TPT1 to TFT3 divided into a plurality of parts are shown in FIGS. 1, 2A, and 5 (layers d1 to 5D23 in FIG. As shown in detail in the plan view (plan view depicting only d3), they are provided separately on the semiconductor layer AS.The source electrode SDI and the drain electrode SD2 are each
A first conductive film d1, a second conductive film d2, and a third conductive film d3 are sequentially stacked one on top of the other from the lower layer side in contact with the N+ type semiconductor MdO. First conductive film d of source electrode SDI
1. The second conductive film d2 and the third conductive film d3 are formed in the same manufacturing process as the drain electrode SD2. The first conductive film d1 is a chromium film formed by sputtering, and is formed to have a thickness of 500 to 100 mm (in this embodiment, a thickness of approximately 600 mm). The thicker the chromium film is, the greater the stress will be, so
0 [Form the film within a range that does not exceed the thickness of a human body. The chromium film has good contact on the N+ type semiconductor Nd. The chromium film constitutes a so-called barrier layer that prevents aluminum of the second conductive film d2, which will be described later, from diffusing into the N+ type semiconductor layer dO. As the first conductive film d1, in addition to the chromium film, a high melting point metal (Mo, Ti, Ta, W) film, a high melting point metal silicide (MoSi2, T i S i 2
, TaSi, , WSi2) film. After patterning the first conductive film d1 by photo processing, the N+ layer do is removed using the same photo processing mask or using the first conductive film d1 as a mask. In other words, the portion of the N+ layer dO remaining on i Jl A S other than the first conductive film d1 is removed by the self-alignment. At this time, since N'' and IIdO are etched so that their entire thickness is removed, the i-layer AS is also slightly etched on its surface, but the extent can be controlled by the etching time. 2 conductive film d2 is formed by aluminum sputtering to a film thickness of 3000 to 5500 [in this example, a film thickness of about 3500].The aluminum film is less stressed than the chromium film. It is possible to form a small and thick film, and is configured to reduce the resistance values of the source electrode SDI, drain electrode SD2, and video signal line DL. Alternatively, the third conductive film d3 may be formed using an aluminum film containing silicon (Si) or copper (Cu) as an additive.After patterning the second conductive film d2 using a photoprocessing technique, a third conductive film d3 is formed. This third conductive film d3 is a transparent conductive film (Induim-T) formed by sputtering.
in-Oxide I T○: Nesa membrane),
00~zoooc person] film thickness (in this example, 1200
It is formed with a film thickness of about [a person]. This third conductive film d3
are source electrodes SD1. In addition to forming the drain electrode SD2 and the video signal line DL, the transparent pixel electrode ITO
It is designed to constitute I. First conductive film d1 of source electrode SD1. drain electrode SD
Each of the two first conductive films d1 has an upper second conductive film d1.
The conductive film d2 and the third conductive film d3 extend further inward (into the channel region). In other words, the first conductive film d1 in these parts is configured to be able to define the gate length of the thin film transistor TPT independently of the first layers d2 and d3. Furthermore, since the end of the third conductive film d3 on the channel side is located inside the end of the second conductive film d2 on the channel side, misalignment between the second conductive film d2 and the third conductive film d3 can be avoided. Even if there is, the second conductive film d2 is different from the third conductive film d.
3, no aluminum whiskers will occur. Therefore, the protective film PSVI provided on the third conductive film d3 will not be peeled off or holes will be formed in the protective film PSVI due to the aluminum whisker, so that the processing solution in the subsequent process will not be applied to the second conductive film d2 and the third conductive film d3. Conductive film d3
Since the treatment liquid does not reach the second conductive film d2. Since the third conductive film d3 does not dissolve,
The liquid crystal LC will not change in quality. Further, the third conductive film d3
Since the second conductive film d2 is covered with the resist when forming the third conductive film d2, the second conductive film d2 is not dissolved by the developer when forming the third conductive film d3. As described above, the source electrode SDI is connected to the transparent pixel electrode IT.
Connected to OI. The source electrode SDI has a step shape of the i-type semiconductor layer AS (thickness of the first conductive film g1, N"Md
It is configured along a step corresponding to the sum of the film thickness of O and the film thickness of the i-type semiconductor layer AS. Specifically, the source electrode SDI is connected to a first conductive film d1 formed along the step shape of the i-type semiconductor layer AS, and a transparent pixel electrode ITOI above the first conductive film d1. a second conductive film d2 formed with a smaller size on the opposite side;
The third conductive film d3 is connected to the first conductive film d1 exposed from the second conductive film. Source electrode SD
The second conductive film d2 of I cannot be formed thickly due to the increased stress of the chromium film of the first conductive film d1, and cannot overcome the stepped shape of the i-type semiconductor layer AS.
It is designed to overcome S. In other words, the step coverage is improved by forming the second conductive film d2 thickly. Since the second conductive film d2 can be formed thickly, it greatly contributes to reducing the resistance value of the source electrode SDI (the same applies to the drain electrode SD2 and the video signal line DL). Since the third conductive film d3 cannot overcome the step shape caused by the i-type semiconductor layer AS of the second conductive film d2, by reducing the size of the second conductive film d2, the exposed first conductive film d1 configured to connect. The first conductive film d1 and the third conductive film d3 not only have good adhesion but also have a small step shape at the connecting portion between them, so that they can be reliably connected. (Pixel electrode IT○1) The transparent pixel electrode ITOI is provided for each pixel, and constitutes one of the pixel electrodes of the liquid crystal display section. The transparent pixel electrode ITOI is divided into three transparent pixel electrodes (divided transparent pixel electrodes) El, E2, and E3 corresponding to each of the thin film transistors TPTI to TFT3 divided into a plurality of pixels. Each of the transparent pixel electrodes E1 to E3 is a thin film transistor TPT.
is connected to the source electrode SDI of. Each of the transparent pixel electrodes E1 to E3 is patterned to have substantially the same area. In this way, by dividing the thin film transistor TPT of one pixel into a plurality of thin film transistors TPTI to TFT3, and connecting each of the plurality of divided transparent pixel electrodes E1 to E3 to each of the plurality of divided thin film transistors TPTI to TFT3. Even if one divided part (for example, TFTl) becomes a point defect, it is no longer a point defect when looking at the entire pixel (TFT2 and TFT3 are not defective), so the probability of point defects can be reduced. , it can also make defects more difficult to see. . Further, by configuring each of the divided transparent pixel electrodes E1 to E3 of the pixel to have substantially the same area, each of the transparent pixel electrodes E1 to E3 and the common transparent pixel electrode I
Each liquid crystal capacitor (Cpix
) can be made uniform. (Protective film PSVI> A protective film PSVI is provided over the thin film transistor TPT and the transparent pixel electrode ITOI. The protective film PSVI is mainly formed to protect the thin film transistor TPT from moisture etc. The protective film PSVI is made of, for example, a silicon oxide film or a silicon nitride film formed by plasma CVD.
It is formed with a film thickness of about 0 [person]. (Light-shielding film BM> A shielding film BM is provided on the upper substrate 5UB2 side to prevent external light (light from above in FIG. 2A) from entering the i-type semiconductor/llAs used as a channel formation region, The pattern is as shown by the hatching in Fig. 6.The pattern shown in Fig. 6 is the ITO film layer d3 in Fig. 1.
, is a plan view depicting only the filter layer FIL and the light shielding film BM. The light-shielding film BM is formed of, for example, an aluminum film or a chromium film that has a high light-shielding property, and in this embodiment, the chromium film is formed by sputtering to a thickness of about 1300 [in]. Therefore, the common semiconductor layer AS of TPTI~3 is sandwiched between the upper and lower light shielding films BM and the thick gate electrode GT, and that portion is not exposed to external natural light or backlight light. The light shielding film BM is formed around the pixel as shown by the hatched area in FIG. There is. Therefore, the outline of each pixel becomes clear due to the light shielding film BM, and the contrast is improved. In other words, the light shielding film BM is
It has two functions: light shielding for the semiconductor layer AS and black matrix. In addition, the backlight is installed on the 5UBZ side and the 1.5UB
Li 1! It can also be set to the observation side (externally exposed side). (Common Electrode I To 2) The common transparent pixel electrode IT○2 is connected to the lower transparent glass substrate 5U.
Opposing the transparent pixel electrode ITOI provided for each pixel on the BI side, the optical state of the liquid crystal changes in response to the potential difference (electric field) between each pixel electrode ITOI and the common electrode IrO2. This common transparent pixel electrode ITO2 has a common voltage V c
ow is applied. Common voltage V
com is a low-level drive voltage Vdwin and a high-level drive voltage Vdma applied to the video signal line DL.
It is an intermediate potential with x. (Color filter FIL> The color filter FIL is constructed by coloring a dyed base material made of a resin material such as acrylic resin with a dye.The color filter FIL has a dot for each pixel at a position opposite to one pixel. (Fig. 7) is formed into a shape (Fig. 7) and is dyed separately (Fig. 7 depicts only the third conductive film layer d3 and color filter layer FIL in Fig. 3, and each of the R, G, and H filters is 45°, 135°, and cross hatches, respectively).The color filter FIL is formed thick so as to cover all of the pixel electrodes IT○1 (E1 to E3) as shown in FIG. , the light shielding film BM is a color filter FI
It is formed inside the periphery of the pixel electrode ITO1 so as to overlap with L and the edge portion of the pixel electrode IT○1. The color filter FIL can be formed in a linear manner. First, a dyed base material is formed on the surface of the upper transparent glass substrate 5UB2, and the dyed base material other than the red filter forming area is removed using photolithography technology. After this, the dyed base material is dyed with red dye. A fixing process is performed to form a red filter R. Next, a green filter G and a blue filter B are sequentially formed by performing similar steps. The protective film PSV2 is provided to prevent the dyes used to dye the color filter FIL into different colors from leaking into the liquid crystal LC. The protective film PSV2 is, for example,
It is made of transparent resin material such as acrylic resin or epoxy resin. (Pixel Arrangement) As shown in FIGS. 3 and 7, each pixel of the liquid crystal display section is arranged in plurality in the same column direction as the direction in which the scanning signal line GL extends, and one pixel column Xi, X2°X3 ．． X4. ...
It consists of each of the following. Each pixel column Xi, X2. X3
．． X4. . . . have thin film transistors TFT1 to TFT3 and transparent pixel electrodes E1 to E3 arranged in the same position. In other words, odd pixel row Xi
,X3. For each pixel, the thin film transistors TPTI to TFT3 are arranged on the left side, and the transparent pixel electrode E is placed on the left side.
1 to E3 are arranged on the right side. Odd pixel row Xi. X3. Each adjacent even-numbered pixel column X in the row direction
2. X4. Each pixel of ... is an odd pixel column X1
,X3. . . . each pixel of the video signal gDL.
It is composed of pixels that are symmetrical and upside down with respect to the direction in which it extends. That is, the pixel row X2°X4. ...
Each pixel of thin film transistors TPTI to TF
The arrangement position of T3 is arranged on the right side, and the arrangement position of transparent pixel electrodes E1 to E3 is arranged on the left side. and 5 pixel rows x2. X4. Each pixel in pixel rows Xi, X3 . For each pixel of...
In other words, each pixel interval in pixel column X is set to 1.0 (1,0
Pitch), the next pixel row X has a pixel interval of 1
．． 0, and the video signal line DL, which extends in the row direction between each pixel and is shifted by 0.5 pixel interval (0.5 pitch) in the column direction with respect to the previous pixel column , it is configured to extend in the column direction by half a pixel interval (0.5 pitches). As a result, as shown in FIG. 7, the pixels in the previous pixel row The pixels on which the same color filter is formed (for example, the pixel on which the red filter R of pixel row X4 is formed) are separated by 1.5 pixel intervals (1.5 pitch), and
The GB color filters FIL have a triangular arrangement. The RGB triangular arrangement structure of the color filter FIL can improve the mixing of each color, and therefore can improve the resolution of a color image. Moreover, since the video signal line DL extends in the column direction by only half a pixel interval between each pixel column X, it does not intersect with the adjacent video signal line DL. Therefore, video signal line D
It is possible to eliminate the routing of L and reduce its occupied area, and it is also possible to eliminate the detour of the video signal line DL and eliminate the multilayer wiring structure. (Equivalent circuit of the entire display panel) Both circuits of this liquid crystal display device are shown in FIG. X i G , X i + I G , . . . are video signal lines DL connected to pixels in which the green filter G is formed. XiB, Xi+IB, . . . are video signal lines DL connected to the pixels in which the blue filter B is formed. X i + I R, X i + 2 R, - are video signal lines D connected to the pixels where the red filter R is formed.
It is L. These video signal lines DL are selected by a video signal drive circuit. Yi is a scanning signal line GL that selects the pixel column X1 shown in FIGS. 3 and 7. Similarly, Yi+1. Yi+2. . . , each of pixel rows X2 . X3. . . . is a scanning signal tGL that selects each of the following. These scanning signal lines GL are connected to a vertical scanning circuit. (Structure of Additional Capacitance Cadd) Each of the transparent pixel electrodes E1 to E3 receives the adjacent scanning signal 4! at the end opposite to the end connected to the thin film transistor TPT. It is bent into an L shape so as to overlap with GL. As is clear from FIG. 2B, this superposition is achieved by using a storage capacitance element (capacitance element) Cadd
Configure. The dielectric film of this storage capacitor element Cadd is an insulating film GI used as a gate insulating film of the thin film transistor TPT.
It is composed of the same layer. As is clear from FIG. 4, the storage capacitor Cadd is formed in the widened portion of the first layer g1 of the gate line OL. Note that the portion of the layer g1 that intersects with the drain line DL is made thin in order to reduce the probability of short circuit with the drain line. Each of the transparent pixel electrodes E1 to E3 and the capacitor electrode line (gl
), similar to the source electrode SDI, there is a 1
An island region made up of the first conductive film d1 and the second conductive film d2 is provided so that the transparent pixel electrode ITOI is not disconnected when climbing over the step shape. This island region is configured to be as small as possible so as not to reduce the area (aperture ratio) of the transparent pixel electrode ITOI. (Additional capacitance Cadd circuit and its operation) The circuit of the pixel shown in FIG. 1 is shown in FIG. In FIG. 9, Cgs is a parasitic capacitance formed between the gate electrode GT and source electrode SDI of the thin film transistor TPT. The dielectric film of the parasitic capacitance Cgs is an insulating film GI. Cp
ix is a liquid crystal capacitance formed between the transparent pixel electrode ITOI (PIX) and the common transparent pixel electrode IT○2 (COM). The dielectric film of the liquid crystal capacitor Cpix includes the liquid crystal LC1 protective film psv1 and the alignment film ORI 1. It is OR42. V
lc is the midpoint potential. The storage capacitor element Cadd functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the TFT switches. Expressing this situation using the formula, ΔV lc = (Cgs/ (Cgs+Cadd+C
pix)) XΔVg. Here, ΔVlc is ΔVg
represents the change in midpoint potential due to This change Δv1c
causes a DC component applied to the liquid crystal, but the retention capacity Ca
The larger dd is, the smaller its value can be. In addition, the holding capacitor Cadd also has the effect of lengthening the discharge time, so that video information is stored for a long time after the TPT is turned off. Reducing the DC component applied to the liquid crystal LC can improve the life of the liquid crystal LC and reduce so-called burn-in, in which the previous image remains when switching liquid crystal display screens. As mentioned above, since the gate electrode GT is enlarged to completely cover the semiconductor RAS, the overlap area with the source/drain electrodes SDI and SD2 increases, and therefore the parasitic capacitance Cgs increases, and the midpoint potential Vlc becomes lower than that of the gate electrode. The opposite effect occurs in that it becomes more susceptible to the influence of the (scanning) signal Vg. However, by providing the holding capacitor Cadd, this disadvantage can also be eliminated. The storage capacitance of the storage capacitor element Cadd is 4 to 8 times the liquid crystal capacitance Cpix (4・Cp
ix<Cadd<8・Cpix), 8 to 32 times the superposition capacitance Cgs (8・Cgs<Cadd<
Set to a value of about 32 Cgs). (Connection method of additional capacitor Cadd electrode line) The final stage scanning signal line GL (or first stage scanning signal IGL) used only as a capacitor electrode line is connected to the common transparent pixel electrode (Vcom) as shown in FIG. Connect to IrO2. As shown in FIG. 2A, the common transparent pixel electrode IT○2 is connected to an external wiring at the peripheral edge of the liquid crystal display device by means of a silver paste material SL. Furthermore, a part of the conductive wire /W (gl and g2) of this external lead wiring is constructed in the same manufacturing process as the scanning signal line OL. As a result, the final stage capacitor electrode line GL can be easily connected to the common transparent pixel electrode TO2. Alternatively, as shown by the dotted line in FIG. 8, the final stage (first stage) capacitor electrode line OL may be connected to the first stage (final stage) scanning signal line GL. This can be done by wiring or external wiring. (DC cancellation by additional capacitance Cadd scanning signal) This liquid crystal display device is based on the DC cancellation method (DC cancellation method) described in Japanese Patent Application No. 62-95125 previously filed by the applicant of the present invention. Diagram (time chart)
As shown in FIG. 3, by controlling the active voltage of the scanning signal line DL, the DC component applied to the liquid crystal LC can be further reduced. In FIG. 10, Vi is the drive voltage of an arbitrary scanning signal line GL, and V i +1 is the drive voltage of the scanning signal line GL at the next stage. Vee is a low-level active voltage V d +ain applied to the scanning signal line GL, and Vdd is a high-level drive voltage V d wa applied to the scanning signal line GL.
It is x. Midpoint potential Vl at each time 1=11 to t4
The voltage changes Δv1 to Δv4 of c (see Figure 9) are as follows6 ΔV, -(Cgs/C)・V2 ΔV2=+(Cgs/C)(V1+V2)-(Cadd
/ C)・V 2 ΔVs= (Cgs/C)・V1 + (C: add/C) (V 1 + V 2 ) Δ
V, = -(Cadd/C)・V Also, the total capacitance of pixels: C= Cgs+ Cpix+Cadd Here, if the drive voltage applied to the scanning signal vIAGL is sufficient (see Note 1 below), the liquid crystal The DC voltage applied to the LC is ΔV, +ΔV, = ('Cadd・■2− Cgs−V
1)/C, so Cadd-V2=C
If gs・V is 1. The DC voltage applied to the liquid crystal LC becomes zero.

[Note] At time t and t2, the change in the scanning line Vi affects the midpoint potential vlc, but during the period from t2 to t1, the midpoint potential v1c is made the same potential as the video signal potential through the signal line Xi. (Enough writing of video signal). The potential applied to the liquid crystal is almost determined by the potential immediately after the TPT is turned off (the TPT off period is overwhelmingly longer than the on period). Therefore, when calculating the DC component applied to the liquid crystal, one period t~t can be almost ignored, and the potential immediately after the TPT is turned off,
That is, it is only necessary to consider the influence of the transition at time 1, t4. Note that the polarity of the video signal Vi is inverted for each frame or line, and the DC component due to the video signal itself is zero. In other words, the DC cancellation method uses the drive voltage applied to the storage capacitance element Cadd and the next scanning signal line GL (capacitance electrode line) to push up the drop caused by the pull in of the midpoint potential Vlc by one superimposed capacitance Cgs. The DC component applied to the LC can be made extremely small. As a result, the life of the liquid crystal LC of the liquid crystal display device can be improved. Of course, if the gate GT is increased in size to improve the light shielding effect, the value of the storage capacitor Cadd may be increased accordingly. Next, a method for manufacturing the liquid crystal display device shown in FIG. 1 and the like will be explained. First, a film thickness of 1100 [λ
A first conductive film g1 made of chromium is provided by sputtering. Next, by selectively etching the first conductive film g1 using a photolithography technique using a ceric ammonium nitrate solution as an etching solution, the first layer of the scanning signal line GL, the gate electrode GT, and the storage capacitor Cadd are etched. electrode PLI is formed. Next, after removing the resist with stripping liquid 5502 (trade name), 02 ashing is performed for 1 minute. Next, a second conductive film g2 made of aluminum-palladium, aluminum-silicon, aluminum-silicon-titanium, aluminum-silicon-copper, etc. with a thickness of 1000 mm is provided by sputtering. Next, the second layer of the scanning signal line GL is formed by selectively etching the second conductive film g2 by photolithography using a mixed acid of phosphoric acid, nitric acid, and acetic acid as an etching solution. Next, SF and gas are introduced into a dry etching device to remove residues such as silicon, and then the resist is removed. Next, ammonia gas, silane gas, and nitrogen gas were introduced into the plasma CVD apparatus to form a silicon nitride film with a film thickness of 3500 mm, and then silane gas, hydrogen gas, and phosphine gas were introduced into the plasma CVD apparatus. , an i-type amorphous silicon film with a thickness of 2100 [people], and an N + -type silicon film with a thickness of 300 [people]. Next, the N+ type silicon film and the J type amorphous silicon film are selectively etched by photolithography using SFG and CCl4 as a dry etching gas, thereby forming an i type semiconductor layer AS. Next, after removing the resist, the silicon nitride film is selectively etched by photolithography using SF as a dry etching gas, thereby forming an insulating film GI. Next, after removing the resist, the film thickness was 600 [people].
A first conductive film d1 made of chromium is formed by sputtering.Next, the first conductive film d1 is selectively etched using a photolithographic technique to form video signal lines DL,
A first layer of a source electrode SDI and a drain electrode SD2 is formed. Next, before removing the resist, CCU, SF are introduced into a dry etching apparatus to selectively etch the N+ type silicon film, thereby forming an N+ type semiconductor layer do. Next, after removing the resist, 0□ ashing is performed for 1 minute. Next, the film thickness is 35
00 [The second conductive film d2 is provided by sputtering. Next, the second conductive film d2 is selectively etched using photolithography to form a second layer of the video signal line DL, source electrode SD1, and drain electrode SD2. Next, after removing the resist, apply 02 asher 1
Next, a third conductive film d3 made of IT○ having a film thickness of 1200 mm is formed by sputtering. Next, by selectively etching the third conductive film d3 using a photolithography technique using a mixed acid of hydrochloric acid and acetic acid as an etching solution, the video signal line DL and the source electrode SD1 are etched.
．． A third layer of the drain electrode SD2 and a transparent pixel electrode ITOI are formed. Next, I removed the resist.
Ammonia gas, silane gas, and nitrogen gas are introduced into a plasma CVD apparatus to provide a silicon nitride film having a thickness of 1[-]. Next, a protective film PSVI is formed by selectively etching the silicon nitride film by photolithography using SF as a dry etching gas. As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course. For example, in this example, a reverse staggered structure is shown in which gate electrode formation → gate insulating film formation → semiconductor layer formation → source/drain electrode formation, but the present invention is also effective in a staggered structure in which the vertical relationship or the order of formation is reversed. be. Further, in the above embodiment, the case where the second film is the third conductive film d3 made of ITO was explained, but the second film was made of 5nO
8 film, Cr film, etc.

【Effect of the invention】

As explained above, in the liquid crystal display device according to the present invention, since the channel-side end of the second film is located inside the channel-side end of the first film, Even if there is misalignment between the film and the second film, the first film is covered by the second film, so no aluminum whiskers will occur. For this reason, the film provided on the second film will not be peeled off by the aluminum whisker or holes will be formed in the film, so that the processing liquid in the subsequent process will not reach the first film and the second film. Since the processing liquid does not dissolve the first film and the second film, the liquid crystal does not change in quality.Furthermore, the resist used to form the second film does not dissolve the first film. Since the first film is covered, the first film will not be dissolved by the developer when forming the second film. As described above, the effects of this invention are remarkable.

[Brief explanation of drawings]

FIG. 1 is a plan view of a main part showing one pixel of a liquid crystal display section of an active matrix color liquid crystal display device according to an embodiment of the present invention, and FIG. 2A is a plan view taken along the nB-nB cutting line in FIG. 2B is a sectional view taken along the NC-NC cutting line in FIG. 1, and FIG. 3 is a plan view of the main part of the liquid crystal display section in which a plurality of pixels shown in FIG. 1 are arranged. 4 to 6 are plan views depicting only predetermined layers of the pixel shown in FIG. 1, and FIG. 7 is a plan view depicting only the pixel electrode layer and color filter layer shown in FIG. 3. 8 is an equivalent circuit diagram showing the liquid crystal display section of an active matrix color liquid crystal display device; FIG. 9 is an equivalent circuit diagram of the pixels shown in FIG. 1; FIG. 10 is a time chart showing the driving voltage of the scanning signal line using the DC cancellation method. SUB...Transparent glass substrate GL...Scanning signal line DL...Video signal line GI...Insulating film GT...Gate electrode AS...J-type semiconductor layer SD...Source electrode or drain electrode psv...
Protective film BM...Light shielding film LC...Liquid crystal TPT...Thin film transistor ITO...Transparent pixel electrode g+d...Conductive film Cadd...Holding capacitor element Cgs...Superposition capacitance Cpix...Liquid crystal Capacity Agent Patent Attorney Junnosuke Nakamura

Claims (1)

[Claims] 1. In an active matrix type liquid crystal display device in which a thin film transistor and a pixel electrode are one component of a pixel, a first film having a metal other than aluminum on the first film having aluminum as the source electrode and drain electrode of the thin film transistor is used. 1. A liquid crystal display device comprising: a second film, the channel-side end of the second film being located inside the channel-side end of the first film.