JPH02237019A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH02237019A
JPH02237019A JP5691489A JP5691489A JPH02237019A JP H02237019 A JPH02237019 A JP H02237019A JP 5691489 A JP5691489 A JP 5691489A JP 5691489 A JP5691489 A JP 5691489A JP H02237019 A JPH02237019 A JP H02237019A
Authority
JP
Japan
Prior art keywords
film
substrate
exposure
resist
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5691489A
Other languages
Japanese (ja)
Inventor
Yasushi Ema
泰示 江間
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5691489A priority Critical patent/JPH02237019A/en
Publication of JPH02237019A publication Critical patent/JPH02237019A/en
Pending legal-status Critical Current

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  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To secure the accuracy of pattern by focussing the light of exposure by a method wherein a first film and a second film are patternized almost same as the pattern of a resist film using a patternized resist film as a radical, and the patternized first and the second films are formed into the mask for processing of the substrate. CONSTITUTION:A photoresist is coated on the whole surface of a wiring layer 3, and a first film 21 consisting of a resist is formed by patterning in such a manner that the resist will be left only on the lower step region of the step of the wiring 3 by conducting exposing and developing operations. Then, a second film 22 consisting of resist is formed by coating the same resist as the first film 21 on the whole surface. Subsequently, a third film 23 consisting of SOG is formed by spin-coating spin-on-glass(SOG) on the whole surface, and besides, a resist film for exposure is formed by spin-coating a photoresist on the whole surface. As the surface of the second film 22 is almost plane, the resist film for exposure 24 has the almost plane surface, a focussing can be conducted on the whole area when a patterning exposure is performed, and the accuracy of pattern of the mask for substrate processing can be secured.

Description

【発明の詳細な説明】 〔概 要〕 半導体装置の製造方法、特に、表面に段差を有する基板
に対して、基板表面上にパターン化した基板加工用マス
クを形成する方法に関し、上記パターン化のホトリソグ
ラフィに用いる露光用レジスト膜に対し、上記段差の存
在にもかかわらず全域に渡り露光の焦点を合わせ得るよ
うにして、上記基板加工用マスクのパターン精度を確保
することを目的とし、 基{反加工のマスクとなり得て基板に対し選択的に除去
可能な材料で、基板表面の段差下段域上に表面の高さが
基板表面の段差上段域にほぼ等しい第1膜を形成してか
ら、基板加工のマスクとなり得て基板に対し選択的に除
去可能な材料で、基板上の全面に表面がほぼ平面をなす
第2膜を形成する行程と、第2膜上に厚さがほぼ均一な
露光用レジスト膜を形成して、露光及び現像により該レ
ジスト膜をパターン化する行程と、パターン化された該
レジスト膜を基にして、第2膜及び第1膜を該レジスト
膜のパターンにほぼ等しくパターン化する行程とを含ん
で、パターン化された第1膜及び第2膜を上記基板加工
用マスクとするように構成する。
[Detailed Description of the Invention] [Summary] A method of manufacturing a semiconductor device, particularly a method of forming a patterned mask for processing a substrate on the surface of a substrate having a step on the surface. The purpose of this is to ensure the pattern accuracy of the substrate processing mask by making it possible to focus the exposure over the entire area despite the presence of the steps in the exposure resist film used in photolithography. After forming a first film on the lower step region of the substrate surface with a surface height approximately equal to the upper step region of the substrate surface using a material that can serve as an anti-processing mask and can be selectively removed from the substrate, A process of forming a second film with a substantially flat surface over the entire surface of the substrate using a material that can be used as a mask for substrate processing and can be selectively removed from the substrate; A process of forming a resist film for exposure and patterning the resist film by exposure and development, and forming a second film and a first film approximately in the pattern of the resist film based on the patterned resist film. The patterned first film and second film are configured to be used as a mask for processing the substrate.

〔産業上の利用分野〕[Industrial application field]

本発明は、半導体装置の製造方法に係り、特に、表面に
段差を有する基板に対して、基板表面上にパターン化し
た基板加工用マスクを形成する方法に関する。
The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a patterned substrate processing mask on the surface of a substrate having a step on the surface.

半導体装置は、集積化が高度になるに従って、加工する
パターンの微細化が進むと共に、例えばDRAMに見ら
れるように加工中の基板の表面に生ずる段差が大きくな
ってきている。
2. Description of the Related Art As semiconductor devices become more highly integrated, the pattern to be processed becomes finer, and the level difference formed on the surface of a substrate being processed becomes larger, as seen in, for example, a DRAM.

そこで、上記基板加工用マスクは、基板表面にこの段差
を有する場合にもパターン精度を確保する必要がある。
Therefore, it is necessary for the above-mentioned substrate processing mask to ensure pattern accuracy even when the substrate surface has this step difference.

〔従来の技術〕 半導体装置の製造において、基板表面上にバクーン化し
た基板加工用マスクを形成して行う基板加工には、例え
ば、半導体部分に拡散領域を形成するイオン注入、基板
上に被着した絶縁膜に電極窓又はイオン注入窓などを形
成するエッチング、その絶縁膜上に被着した配線層をパ
ターン化するエッチング、などがある。そこにおける基
板表面は、上記半導体部分、上記絶縁膜又は上記配線層
などの表面を指す。
[Prior Art] In the manufacture of semiconductor devices, substrate processing is performed by forming a mask for substrate processing on the surface of the substrate, for example, ion implantation to form a diffusion region in the semiconductor portion, deposition on the substrate, etc. This includes etching to form electrode windows or ion implantation windows in the insulating film, and etching to pattern a wiring layer deposited on the insulating film. The substrate surface herein refers to the surface of the semiconductor portion, the insulating film, the wiring layer, or the like.

その場合、基板加工用マスクの抜き領域が基板の加工領
域となりその加工領域のパターンが微細であることから
、そのマスクはホトリソグラフィを利用して形成してい
る。
In this case, the blank area of the substrate processing mask becomes the processing area of the substrate, and the pattern of the processing area is fine, so the mask is formed using photolithography.

即ち、基板表面上に露光用レジスト膜を例えばスピン塗
布により形成し、ホトマスクのパターンを転写する光照
射などにより上記レジスト膜に焦?合わせした露光を行
い、そのレジスト膜を現像によりパターン化して上記の
基板加工用マスクとするものである。
That is, a resist film for exposure is formed on the surface of a substrate by, for example, spin coating, and the resist film is focused by light irradiation to transfer a photomask pattern. The resist film is exposed to the same light, and the resist film is patterned by development to form the mask for processing the substrate.

或いは、トリレベル法(31レジスト法)と称せられる
もので、基板表面上にレジスト膜とSin2膜を順次形
成した後、上述のように露光用レジスト膜を形成してこ
れをパターン化し、この露光用レジスト膜をマスクにし
たエッチングでSiO■膜をパターン化し、更にこのS
in.膜をマスクにしたエッチングで下側のレジスト膜
をパターン化して、このレジスト膜を基板加工用マスク
とするものである。この方法は、下側レジスト膜を露光
用レジスl−膜よりも厚くなし得ること、また、基板表
面に幅の狭い凹部があってもその凹部を埋めて下側レジ
スト膜の表面がほぼ平坦になり得ること、の利点を有す
る。
Alternatively, in the so-called tri-level method (31 resist method), a resist film and a Sin2 film are sequentially formed on the substrate surface, and then a resist film for exposure is formed and patterned as described above. The SiO film is patterned by etching using the resist film as a mask, and then this S
in. The lower resist film is patterned by etching using the film as a mask, and this resist film is used as a mask for substrate processing. This method allows the lower resist film to be made thicker than the exposure resist film, and even if there is a narrow recess on the substrate surface, the recess is filled and the surface of the lower resist film is almost flat. It has the advantage of being able to become.

、〔発明が解決しようとする課題〕 しかしながら、基板加工用マスクを形成する際の上述し
た従来の方法は、例えば第2図の側断面図に示されるよ
うに、基板表面に幅の広い段差を有する場合に次に説明
する問題を抱えている。
, [Problem to be Solved by the Invention] However, the above-mentioned conventional method for forming a mask for processing a substrate does not require wide steps on the surface of the substrate, as shown in the side cross-sectional view of FIG. 2, for example. If you have one, you will have the following problem.

第2図は、DRAMにおける基板1上の絶縁膜2の上に
被着した配線N3をパターン化する場合であり、配線層
3上に形成する基板加工用マスクに用いる露光用レジス
ト膜11を形成したところを示す。
FIG. 2 shows a case where wiring N3 deposited on an insulating film 2 on a substrate 1 in a DRAM is patterned, and a resist film 11 for exposure used as a mask for processing the substrate is formed on the wiring layer 3. Show what you did.

このDRAMは、メモリセル領域4と周辺回路頭域5を
有し、メモリセルに積層構造のスタック型蓄積キャパシ
タ6を用いてメモリセル領域4が高く盛り上がっている
ために、配線層3の表面がメモリセル領域4と周辺回路
領域5との間に大きな段差を有している。
This DRAM has a memory cell area 4 and a peripheral circuit head area 5, and uses a stacked storage capacitor 6 with a laminated structure in the memory cell, so that the memory cell area 4 is raised high, so that the surface of the wiring layer 3 is There is a large step difference between the memory cell region 4 and the peripheral circuit region 5.

このことから、露光用レジスト膜11は、配線層3に倣
って表面に段差が生じており、パターン化の露光の際に
メモリセル領域4と周辺回路頭域5との間で一方に焦点
を合わせると他方の焦点が合わない状態になっている。
From this, the exposure resist film 11 has a step on its surface that follows the wiring layer 3, and during patterning exposure, the focus is focused on one side between the memory cell area 4 and the peripheral circuit head area 5. When one focuses, the other becomes out of focus.

そのために、レジスト膜11のパターン化は精度の悪い
ものとなり、それを用いた基板加工用マスクは、配線N
3の微細加工に適したものとなり難い。それは、加工パ
ターンが微細化されると、露光の焦点深度が浅くなるた
めに一層顕著になる。
For this reason, the patterning of the resist film 11 becomes inaccurate, and a mask for substrate processing using the resist film 11 is
It is difficult to make it suitable for the micro-machining described in No. 3. This becomes more noticeable as the processing pattern becomes finer because the depth of focus of exposure becomes shallower.

このことは、トリレベル法を採用しても同様である。そ
れは、基板表面の先に述べた凹部に相当する段差下段域
(周辺回路頭域5)が広いために、下側レジスト膜の表
面に配線層3に倣った段差が生じて、露光用レジスト膜
が上記と同様になるためである。
The same holds true even if the tri-level method is adopted. This is because the lower step area (peripheral circuit head area 5) corresponding to the above-mentioned concave portion on the substrate surface is wide, so a step similar to the wiring layer 3 is formed on the surface of the lower resist film, and the exposure resist film is the same as above.

そこで本発明は、半導体装置の製造方法、特に、表面に
段差を有する基板に対して、基板表面上にパターン化し
た基板加工用マスクを形成する方法において、上記パタ
ーン化のホトリソグラフイに用いる露光用レジスト膜に
対し、上記段差の存在にもかかわらず全域に渡り露光の
焦点を合わせ得るようにして、上記基板加工用マスクの
パターン精度を確保することを目的とする。
Therefore, the present invention provides a method for manufacturing a semiconductor device, in particular, a method for forming a patterned substrate processing mask on the surface of a substrate having a step on the surface, in which exposure light used in photolithography for patterning is provided. It is an object of the present invention to ensure pattern accuracy of the substrate processing mask by making it possible to focus exposure over the entire area of the resist film despite the presence of the steps.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的は、基板加工のマスクとなり得て基板に対し選
択的に除去可能、な材料で、基板表面の段差下段域上に
表面の高さが基板表面の段差上段域にほぼ等しい第1膜
を形成してから、基板加工のマスクとなり得て基板に対
し選択的に除去可能な材料で、基板上の全面に表面がほ
ぼ平面をなす第2膜を形成する行程と、第2膜上に厚さ
がほぼ均一な露光用レジスト膜を形成して、露光及び現
像により該レジスト膜をパターン化する行程と、パター
ン化された該レジスト膜を基にして、第2膜及び第1膜
を該レジスI・膜のパターンにほぼ等しくパターン化す
る行程とを含んで、パターン化された第1膜及び第2膜
を上記基板加工用マスクとする本発明の製造方法によっ
て解決される。
The above purpose is to form a first film on the lower step area of the substrate surface with a surface height approximately equal to the upper step area of the substrate surface using a material that can be used as a mask for substrate processing and can be selectively removed from the substrate. After the formation, there is a step of forming a second film with a substantially flat surface over the entire surface of the substrate using a material that can be used as a mask for substrate processing and can be selectively removed from the substrate, and a step of forming a second film on the second film with a substantially flat surface. A process of forming an exposure resist film with a substantially uniform thickness and patterning the resist film by exposure and development, and forming a second film and a first film on the resist film based on the patterned resist film. This problem is solved by the manufacturing method of the present invention, which includes the step of patterning the I film almost identically to the pattern of the film, and uses the patterned first film and second film as masks for processing the substrate.

〔作 用〕[For production]

上記第1膜の存在により、上記第2膜の表面が容易にほ
ぼ平面となるので、上記露光用レジスト膜は、基板表面
の段差にかかわりなく表面がほぼ平面となり、全域に渡
り露光の焦点を合わせ得るものとなる。
Due to the presence of the first film, the surface of the second film can easily become substantially flat, so that the surface of the resist film for exposure becomes almost flat regardless of the level difference on the substrate surface, and the focus of exposure can be maintained over the entire area. It becomes something that can be matched.

このことから、露光用レジスト膜を精度良くパターン化
することができて、パターン精度の確保された基板加工
用マスクが形成可能となる。
From this, the resist film for exposure can be patterned with high accuracy, and a mask for substrate processing with guaranteed pattern accuracy can be formed.

〔実施例〕〔Example〕

以下本発明による基板加工用マスクの形成の実施例につ
いて第1図の側断面図を用いて説明する。
An example of forming a substrate processing mask according to the present invention will be described below with reference to the side sectional view of FIG.

全図を通し同一符号は同一対象物を示す。The same reference numerals indicate the same objects throughout the figures.

この実施例は、第2図で述べたDRAMの基板1表面の
配線層3をパターン化する場合のものである。
This embodiment is for patterning the wiring layer 3 on the surface of the DRAM substrate 1 described in FIG. 2.

第1図において、配線層3に対してエッチングマスクと
なり然も選択的に除去し得るホトレジスト(例えばOF
PR800)を配線層3上の全面に塗布し、露光及び現
像により配線層3の段差下段域(周辺回路頭域5)上に
のみ残すようにパターン化してレジストからなる第1膜
21を形成する。
In FIG. 1, a photoresist (for example, OF
PR800) is applied to the entire surface of the wiring layer 3, and patterned by exposure and development so as to remain only on the lower step area (peripheral circuit head area 5) of the wiring layer 3, thereby forming the first film 21 made of resist. .

塗布は例えばスピン塗布により行い、その厚さは配線層
3表面の段差の高さ(メモリセル領域4と周辺回路領域
5との高さの差)に合わせて例えば?0.6μmである
。こうすることにより、露出している配線層3表面のメ
モリセル領域4上部分と第1膜21の表面がほぼ1千面
上に並び、両者の間に幅の狭い凹部が存在する状態にな
る。
The coating is performed, for example, by spin coating, and the thickness is adjusted according to the height of the step on the surface of the wiring layer 3 (difference in height between the memory cell region 4 and the peripheral circuit region 5), for example. It is 0.6 μm. By doing this, the exposed upper part of the memory cell region 4 on the surface of the wiring layer 3 and the surface of the first film 21 are aligned on approximately 1,000 planes, and a narrow recess exists between them. .

次いで、第1膜21と同じホトレジストをスピン塗布に
より厚さ約1μmに全面塗布してレジストからなる第2
膜22を形成する。上記の凹部は埋められて第2膜22
の表面はほぼ平面となる。
Next, the same photoresist as the first film 21 is coated on the entire surface by spin coating to a thickness of about 1 μm to form a second film made of resist.
A film 22 is formed. The above recess is filled with the second film 22.
The surface of is almost flat.

次いで、スビンオングラス(SOG:主成分がSiO■
)をスピン塗布により厚さ約0.2μmに全面塗布して
SOCからなる第3膜23を形成し、更にその上にホト
レジスト(例えばTSMR8800)をスピン塗布によ
り厚さ約0.2μmに全面塗布して露光用レジスト膜2
4を形成する。第2膜22の表面がほぼ平面であること
から、露光用レジスト膜24は、表面がほぼ平面となり
、パターン化の露光の際に全域に渡り焦点を合わせ得る
ものとなる。
Next, Subin-on-glass (SOG: the main component is SiO)
) is coated on the entire surface by spin coating to a thickness of about 0.2 μm to form the third film 23 made of SOC, and then a photoresist (for example, TSMR8800) is coated on the entire surface by spin coating to a thickness of about 0.2 μm. Resist film 2 for exposure
form 4. Since the surface of the second film 22 is substantially flat, the surface of the exposure resist film 24 is substantially flat, and can be focused over the entire area during patterning exposure.

第1図はその状態を示す。FIG. 1 shows the situation.

次いで、露光及び現像によりユ配線層3をパターン化す
るパターンに合わせて露光用レジスト膜24をパターン
化する。露光の焦点を全域に渡り合わせ得ることから、
このバクーン化は精度良く行うことができる。
Next, the exposure resist film 24 is patterned in accordance with the pattern of the wiring layer 3 by exposure and development. Because the focus of exposure can be adjusted over the entire area,
This Bakunization can be performed with high precision.

次いで、パターン化された露光用レジスト膜24をマス
クにしたCHFI +HzプラズマのRIB(反応性イ
オンエッチング)によりSOGの第3膜23をパターン
化し、更に、パターン化された第3膜23をマスクにし
た02プラズマのRIEによりレジストの第2膜22及
び第1膜21をパターン化して、所要の基板加工用マス
クを完成する。上記RIEが異方性であることから、形
成した基板加工用マスクは、露光用レジスト膜24のパ
ターンが忠実に転写されたものとなり、所望のパターン
精度が確保されている。
Next, the third SOG film 23 is patterned by RIB (reactive ion etching) using CHFI +Hz plasma using the patterned exposure resist film 24 as a mask, and further, using the patterned third film 23 as a mask. The second resist film 22 and the first resist film 21 are patterned by RIE using 02 plasma, thereby completing a mask for processing the required substrate. Since the above RIE is anisotropic, the pattern of the exposure resist film 24 is faithfully transferred to the formed substrate processing mask, ensuring desired pattern accuracy.

この基板加工用マスクは、配線N3をパターン化するエ
ッチングのマスクとして用いられた後除去される。その
除去は、周知の方法で容易に行うことができる。
This substrate processing mask is removed after being used as an etching mask for patterning the wiring N3. Its removal can be easily accomplished using well-known methods.

なお、この実施例で述べた基板加工用マスクの形成方法
は、基板表面の配線N3に段差を有する製造中のDRA
Mを対象にした場合であるが、この方法が基板表面に段
差を有する製造中の他の半導体装置を対象にする場合に
も有効であることは、改めて説明するまでもない。
Note that the method for forming the mask for substrate processing described in this embodiment is applicable to a DRA being manufactured that has a step in the wiring N3 on the surface of the substrate.
It goes without saying that this method is also effective when dealing with other semiconductor devices under manufacture that have steps on the substrate surface.

また、上述の説明から容易に理解されるように、第1膜
21及び第2膜22の材料は、基板表面の加工対象物に
対して加工のマスクとなり然も選択的に除去し得るもの
であれば良いので、実施例のレジストに限定されるもの
ではなく、両者が同一である必要もない。
Furthermore, as can be easily understood from the above explanation, the materials of the first film 21 and the second film 22 serve as a mask for processing the object to be processed on the surface of the substrate, and can be selectively removed. It is not limited to the resist of the embodiment, and it is not necessary that the resists are the same.

更に、第1膜21及び第2膜22の材料に対して露光用
レジスト膜24がエッチングマスクとなり得る際には、
第3膜23をを省略することができる。
Furthermore, when the exposure resist film 24 can serve as an etching mask for the materials of the first film 21 and the second film 22,
The third film 23 can be omitted.

〔発明の効果〕 以上説明したように本発明の構成によれば、半導体装置
の製造方法、特に、表面に段差を有する基板に対して、
基板表面上にパターン化した基板加工用マスクを形成す
る方法において、上記パターン化のホトリソグラフィに
用いる露光用レジスト膜に対し、上記段差の存在にもか
かわらず全域に渡り露光の焦点を合わせ得るようになっ
て、上記基板加工用マスクのパターン精度を確保をるこ
とが可能となり、表面に段差を有する基板に対する微細
加工を容易にさせる効果がある。
[Effects of the Invention] As explained above, according to the configuration of the present invention, a method for manufacturing a semiconductor device, particularly for a substrate having a step on the surface, can be applied.
In a method of forming a patterned mask for processing a substrate on the surface of a substrate, the exposure resist film used for photolithography for patterning can be focused over the entire area despite the presence of the steps. This makes it possible to ensure the pattern accuracy of the substrate processing mask, and has the effect of facilitating microfabrication of a substrate having a step on its surface.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は実施例を説明する側断面図、 第2図は従来方法の問題を説明する側断面図、である。 23は第3膜、 11、24は露光用レジスト膜、 である。 図において、 1は基板、 2は絶縁膜、 3は配線層、 4はメモリセル領域、 5は周辺回路領域、 6は蓄積キャパシタ、 21は第1膜、 22は第2膜、 FIG. 1 is a side sectional view explaining the embodiment; FIG. 2 is a side sectional view illustrating the problems of the conventional method. 23 is the third membrane; 11 and 24 are resist films for exposure; It is. In the figure, 1 is the board, 2 is an insulating film, 3 is the wiring layer, 4 is a memory cell area, 5 is the peripheral circuit area; 6 is a storage capacitor, 21 is the first film; 22 is a second film;

Claims (1)

【特許請求の範囲】  半導体装置の製造において、表面に段差を有する基板
に対して、基板表面上にパターン化した基板加工用マス
クを形成する方法であって、 基板加工のマスクとなり得て基板に対し選択的に除去可
能な材料で、基板表面の段差下段域上に表面の高さが基
板表面の段差上段域にほぼ等しい第1膜を形成してから
、基板加工のマスクとなり得て基板に対し選択的に除去
可能な材料で、基板上の全面に表面がほぼ平面をなす第
2膜を形成する行程と、 第2膜上に厚さがほぼ均一な露光用レジスト膜を形成し
て、露光及び現像により該レジスト膜をパターン化する
行程と、 パターン化された該レジスト膜を基にして、第2膜及び
第1膜を該レジスト膜のパターンにほぼ等しくパターン
化する行程とを含んで、 パターン化された第1膜及び第2膜を上記基板加工用マ
スクとすることを特徴とする半導体装置の製造方法。
[Claims] A method for forming a patterned substrate processing mask on the surface of a substrate having a step in the manufacturing of semiconductor devices, the method comprising: forming a patterned substrate processing mask on the substrate surface; On the other hand, after forming a first film using a selectively removable material on the lower step area of the substrate surface, the surface height of which is approximately equal to the upper step area of the substrate surface, the first film can be used as a mask for substrate processing. On the other hand, a process of forming a second film with a substantially flat surface on the entire surface of the substrate using a selectively removable material, and forming a resist film for exposure with a substantially uniform thickness on the second film, A step of patterning the resist film by exposure and development; and a step of patterning a second film and a first film substantially equal to the pattern of the resist film based on the patterned resist film. . A method of manufacturing a semiconductor device, characterized in that the patterned first film and second film are used as masks for processing the substrate.
JP5691489A 1989-03-09 1989-03-09 Manufacture of semiconductor device Pending JPH02237019A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5691489A JPH02237019A (en) 1989-03-09 1989-03-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5691489A JPH02237019A (en) 1989-03-09 1989-03-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02237019A true JPH02237019A (en) 1990-09-19

Family

ID=13040740

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5691489A Pending JPH02237019A (en) 1989-03-09 1989-03-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02237019A (en)

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