JPS5825234A - Formation of resist pattern - Google Patents

Formation of resist pattern

Info

Publication number
JPS5825234A
JPS5825234A JP56124319A JP12431981A JPS5825234A JP S5825234 A JPS5825234 A JP S5825234A JP 56124319 A JP56124319 A JP 56124319A JP 12431981 A JP12431981 A JP 12431981A JP S5825234 A JPS5825234 A JP S5825234A
Authority
JP
Japan
Prior art keywords
portions
exposure
pattern
resist
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56124319A
Other languages
Japanese (ja)
Inventor
Toru Okuma
徹 大熊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP56124319A priority Critical patent/JPS5825234A/en
Publication of JPS5825234A publication Critical patent/JPS5825234A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20Exposure; Apparatus therefor
    • G03F7/2022Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To accurately obtain a less-than-1mum minimal resist pattern by shifting the same pattern on a semiconductor wafer and exposing more than two times through the reduced projection type exposure method used mainly for loose devices of 2-3mum. CONSTITUTION:A positive photo resist 2 with a thickness of approx. 1mum is formed on a substrate 1, and a specified pattern is transferred to this resist using a reduced projection type exposure apparatus. Portions d of the resist 2 shown in the figure are the ultimately desired portions, while portions 3 are alkali-solubilized portions resulted from the first pattern transfer. Without removing the substrate 1 from the exposure apparatus after the first pattern transfer, an exposure position is shifted a specified length of less than 1mum and the same pattern is again transferred so that alkali-solubilized portions 4 are partially produced within the portions 3. Finally, the substrate is removed from the apparatus and subjected to development to remove the portions 3, 4 to retain the desired portions d on the substrate 1.

Description

【発明の詳細な説明】 本発明は半導体ウニノ−などの基板面に所定形状のレジ
ストパターンを形成する方法に関するもものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a resist pattern of a predetermined shape on the surface of a substrate such as a semiconductor unit.

各種デバイス、主に半導体装置の高密度化、高集積化に
伴ない、パターン寸法の微細化が要求されている。半導
体装置製造工程において各種薄膜を所定のパターン形状
にエツチング処理するためのエツチングマスクの微細化
が重要な課題となっている。このエツチングマスクは1
通常有機ポリマーレジストに所定形状のマスクパターン
を光転写し、現像処理を行うことによシ形成される。
2. Description of the Related Art As various devices, mainly semiconductor devices, become denser and more highly integrated, there is a demand for smaller pattern dimensions. In the manufacturing process of semiconductor devices, miniaturization of etching masks for etching various thin films into predetermined pattern shapes has become an important issue. This etching mask is 1
Usually, it is formed by photo-transferring a mask pattern of a predetermined shape onto an organic polymer resist and then performing a development process.

なお、光転写の方法として従来は、マスクと半導体ウェ
ハーを密着させ、紫外光により一括転写する方法が主流
であった。その後半導体ウェハーが大口径化し、半導体
装置の高密度化、高集積化に伴ないチップ面積も大型化
し、パターン寸法の微細化が進み光転写方法も密着露光
方式から反射投影型露光方式さらに縮小投影型露光方式
へと移行しつつある。
Note that, conventionally, the mainstream phototransfer method has been to bring a mask and a semiconductor wafer into close contact with each other and perform batch transfer using ultraviolet light. Later, the diameter of semiconductor wafers became larger, and as semiconductor devices became more dense and highly integrated, chip areas also became larger. Pattern dimensions became smaller, and optical transfer methods changed from contact exposure to reflective projection exposure, and then to reduction projection. There is a shift towards a type exposure method.

しかし光を使用した露光方式では、使用する光の波長の
関係で1μm程度の解像力を得るのが限界である。この
ため、遠紫外光を用いた露光方式や電子ビームによるウ
ェハー直接露光方式、X線を使用した露光方式が検討さ
れているがいずれも実用段階には至っていない。
However, in the exposure method using light, the limit is to obtain a resolution of about 1 μm due to the wavelength of the light used. For this reason, an exposure method using deep ultraviolet light, a wafer direct exposure method using an electron beam, and an exposure method using X-rays are being considered, but none of them have reached the practical stage.

本発明は、2〜3μmルールデバイスの主流といわれる
縮小投影型露光方式を用い、同一マスクを半導体ウェハ
ー等の基板上でシフトさせて2回以上露光処理を行うこ
とによ91μm以下の微細レジストパターンを精度良く
形成しようとするものである。
The present invention uses a reduction projection exposure method, which is said to be the mainstream for 2 to 3 μm rule devices, and uses the same mask on a substrate such as a semiconductor wafer to perform exposure processing two or more times to create a fine resist pattern of 91 μm or less. The aim is to form the image with high precision.

以下に1本発明の方法により微細レジストパターンを形
成する場合について実施例の断面図を参照しつつ説明す
る。
Hereinafter, a case in which a fine resist pattern is formed by the method of the present invention will be described with reference to cross-sectional views of embodiments.

まず第1図に示すように、シリコン基板1上に厚さ約1
μmのポジ型フォトレジスト2を形成・シたものを準備
する。このレジスト2のうちdで示す部分が最終的に残
したい部分である。このシリコン基板1に縮小投影型露
光装置で所定パターンを転写する。
First, as shown in FIG.
A positive type photoresist 2 of μm size is formed and prepared. The portion indicated by d in this resist 2 is the portion that is ultimately desired to remain. A predetermined pattern is transferred onto this silicon substrate 1 using a reduction projection type exposure device.

第2図はパターン転写後の様子を示す図であり図中3は
紫外光により分離し、アルカリ可溶になったレジスト部
分である。その後、シリコン基板2を露光itより取出
すことなく露光位置を第1露光位置より所定寸法(たと
えば1μm以下の寸法)シフトさせ上記と同一のパター
ンを転写する。
FIG. 2 is a diagram showing the state after pattern transfer, and 3 in the figure is a resist portion that has been separated by ultraviolet light and has become alkali-soluble. Thereafter, without taking out the silicon substrate 2 from the exposure unit, the exposure position is shifted from the first exposure position by a predetermined dimension (for example, a dimension of 1 μm or less) and the same pattern as described above is transferred.

この時のシフト量の精度は、縮小投影型露光装置のステ
ージ精度で決定されるが、本装置のステージ精度は0.
06μm以下と高精度である。第3図に2度目め露光後
のレジスト状態を示す。図中4は2度目の露光により光
分解しアルカリ可溶となっタレシスト部分を示す。この
後、シリコン基板を露光装置よシ欧り出し、現像処理を
行う。
The accuracy of the shift amount at this time is determined by the stage accuracy of the reduction projection exposure apparatus, but the stage accuracy of this apparatus is 0.
High accuracy of 0.06 μm or less. FIG. 3 shows the state of the resist after the second exposure. In the figure, 4 indicates a part of Talecyst that is photodecomposed and becomes alkali-soluble by the second exposure. Thereafter, the silicon substrate is taken out of the exposure apparatus and subjected to development processing.

第4図に現像処理後のレジスト断面を示す。この現像処
理では二度の露光処理によっても光照射がなされなかっ
た部分を残し他の全てのレジストの露光作業によシ得ら
れるパターンに比較して非常に寸法精度の良いものであ
った。又本実施例でハホシ型フォトレジストを使用した
がネガ型フォトレジストにおいても同様の効果をうろこ
とができる。
FIG. 4 shows a cross section of the resist after development. In this development process, even after the double exposure process, the pattern which was not irradiated with light remained and the pattern had very good dimensional accuracy compared to the pattern obtained by the exposure process of all other resists. Further, although a halo-type photoresist is used in this embodiment, the same effect can be obtained with a negative-type photoresist.

なお、マスクの移動は一方向ならびにこれと直角の方向
に任意に動かすことができ、高精度に様々なフォトレジ
ストパターンを形成することができる。
Note that the mask can be moved arbitrarily in one direction or in a direction perpendicular to this direction, and various photoresist patterns can be formed with high precision.

以上説明してきたように、本発明の方法により半導体基
板上に形成されたレジストノ(ターンは通常の露光によ
シ得られるレジストノ(ターンに比較して精度が良く、
シかも再現性の良いものである。
As explained above, the resist pattern (turn) formed on a semiconductor substrate by the method of the present invention has better precision than the resist pattern (turn) obtained by normal exposure.
It also has good reproducibility.

また本発明の方法によれば微小寸法のレジストパターン
を容易に得ることができるとともに、露光位置のシフト
量を自由に制御できることから種々の寸法を持つレジス
トパターンを任意に得られるすぐれた効果を発揮するこ
とができる。
Furthermore, according to the method of the present invention, it is possible to easily obtain resist patterns with minute dimensions, and since the shift amount of the exposure position can be freely controlled, it exhibits the excellent effect of arbitrarily obtaining resist patterns with various dimensions. can do.

以上1本発明を半導体基板上へのレジストノ(ターンの
形成を例に説明したのであるが、本発明の方法は他の基
板上へのレジストノ(ターンの形成にも適用できること
勿論である。また、第2の露光処理も1回である必要は
なく、2回以上であってもよい。
Although the present invention has been explained above using the formation of resist turns on a semiconductor substrate as an example, it goes without saying that the method of the present invention can also be applied to the formation of resist turns on other substrates. The second exposure process also does not need to be performed once, and may be performed twice or more.

【図面の簡単な説明】[Brief explanation of the drawing]

第1〜第4図は本発明の一実施例にかかるレジストパタ
ーンの形成工程断面図である。 1・・・・・・シリコン基板、2・・・・・・ポジ型フ
ォトレジストh3・・・・・・第1露光により感光され
たフォトレジスト部分、4・・・・・・第2露光により
感光されたフォトレジスト部分。
1 to 4 are cross-sectional views showing the process of forming a resist pattern according to an embodiment of the present invention. 1...Silicon substrate, 2...Positive photoresist h3...Photoresist portion exposed by first exposure, 4...... by second exposure Exposed photoresist area.

Claims (2)

【特許請求の範囲】[Claims] (1)基板面に被着したフォトレジスト膜に露光マスク
を介して縮小投影露光法でパタンを形成するに際し、前
記基板面の1位置に露光マスクを整合して露光を行う第
1の露光処理を施したのち前記位置から前記露光マスク
を所定寸法シフトさせて露光を行う第2の露光処理を施
し、こののち現像処理を施すことを特徴とするレジスト
パターンの形成方法。
(1) When forming a pattern on a photoresist film deposited on a substrate surface through an exposure mask using a reduction projection exposure method, a first exposure process in which the exposure mask is aligned at one position on the substrate surface and exposed. A method for forming a resist pattern, the method comprising: performing a second exposure process in which the exposure mask is shifted by a predetermined dimension from the above position, and then a development process is performed.
(2)第2の露光処理が、露光マスクの平行シフトと露
光とからなるステップを2回以上含んでいることを特徴
とする特許請求の範囲第1項に記載のレジストパターン
の形成方法。
(2) The method for forming a resist pattern according to claim 1, wherein the second exposure process includes a step consisting of parallel shift of an exposure mask and exposure two or more times.
JP56124319A 1981-08-08 1981-08-08 Formation of resist pattern Pending JPS5825234A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56124319A JPS5825234A (en) 1981-08-08 1981-08-08 Formation of resist pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56124319A JPS5825234A (en) 1981-08-08 1981-08-08 Formation of resist pattern

Publications (1)

Publication Number Publication Date
JPS5825234A true JPS5825234A (en) 1983-02-15

Family

ID=14882385

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56124319A Pending JPS5825234A (en) 1981-08-08 1981-08-08 Formation of resist pattern

Country Status (1)

Country Link
JP (1) JPS5825234A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6358825A (en) * 1986-08-29 1988-03-14 Sony Corp Pattern formation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6358825A (en) * 1986-08-29 1988-03-14 Sony Corp Pattern formation

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