JP2004087715A - Method for exposing to electron beam, semiconductor device, method for processing exposure pattern data, and program - Google Patents

Method for exposing to electron beam, semiconductor device, method for processing exposure pattern data, and program Download PDF

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Publication number
JP2004087715A
JP2004087715A JP2002245671A JP2002245671A JP2004087715A JP 2004087715 A JP2004087715 A JP 2004087715A JP 2002245671 A JP2002245671 A JP 2002245671A JP 2002245671 A JP2002245671 A JP 2002245671A JP 2004087715 A JP2004087715 A JP 2004087715A
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Japan
Prior art keywords
pattern
rectangular
electron beam
step
exposure
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Pending
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JP2002245671A
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Japanese (ja)
Inventor
Yoichi To
塘 洋一
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Semiconductor Leading Edge Technologies Inc
株式会社半導体先端テクノロジーズ
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Priority to JP2002245671A priority Critical patent/JP2004087715A/en
Publication of JP2004087715A publication Critical patent/JP2004087715A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for exposing to an electron beam which can improve a throughput while a pattern creating function is utilized and to provide a semiconductor device manufactured by using the same, a method for processing exposure pattern data and a program for processing the exposure pattern data. <P>SOLUTION: The method for exposing to the electron beam includes a step of exposing an integrated circuit pattern having a rectangular pad pattern disposed by cutting a wiring pattern on a substrate to the beam. The method includes a first step of dividing a plurality of rectangular patterns A', B' having an overlap at the position of the pad pattern (c) extending from divided wiring patterns (a), (b) and pad pattern (c) extending from these wiring patterns (a), (b) into a plurality of rectangular patterns having a size of the maximum shot size or less of the beam, and a second step of sequentially multiple exposing the plurality of the rectangular patterns divided in the first step to multiple expose at the position of the pad pattern (c). <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an electron beam exposure method, a semiconductor device, an exposure pattern data processing method, and a program for processing exposure pattern data.
[0002]
[Prior art]
In the conventional semiconductor integrated circuit manufacturing technology, a light exposure technology using a reticle has been mainstream. This is because the transfer throughput by light is very high and the productivity is high.
[0003]
However, in recent years, as the degree of integration of semiconductor devices has increased, the dimensions of individual elements have been miniaturized, and the dimensions of semiconductor regions constituting each element have also been miniaturized. Accordingly, in the light exposure technology, the pattern size is approaching the limit resolution, so that development of a higher resolution exposure technology is urgently required. Under these circumstances, the electron beam exposure technology has an inherently excellent resolution, so that it has been applied to the development of leading-edge devices represented by DRAM (Dynamic Random Access Memory), and has been partially applied to ASIC (Electronic Random Access Memory). It is also used in the production of Application Specific Integrated Circuits.
[0004]
[Problems to be solved by the invention]
However, the electron beam exposure technique has a problem that it is not suitable for mass production of devices because the electron gun has to draw each circuit in one stroke with an electron gun and the throughput is low.
[0005]
The first proposal to overcome the above problem is the variable shaped beam method. This method focuses on the point that a plurality of points are required to expose a pattern having a relatively large area when performing exposure with a normal point beam, and the first and second rectangular shapes are used. By using the edge portion of the aperture to generate a rectangular electron beam having an arbitrary vertical and horizontal dimension, the throughput is improved. According to the variable shaped beam method, a rectangular electron beam having an arbitrary size is generated within a range not exceeding the maximum shot size, and the electron beam is exposed by one shot. Improvement was realized. However, even with this technique, it was not possible to catch up with the improvement in the degree of integration of the semiconductor integrated circuit, and a method capable of further improving the throughput was sought.
[0006]
Subsequently, the partial batch method was proposed. This method has been given various names, such as a character projection method, a cell projection method, or a block exposure method, depending on the device manufacturer developed, but all have the same principle. The partial batch method focuses on reducing the number of shots as an important point in improving throughput, and creates a pattern that repeatedly appears a certain number of times or more as an aperture that is stored in a predetermined range. is there. That is, according to the partial batch method, a pattern having a large number of repetitions is exposed using an aperture, while a pattern having a small number of repetitions is exposed by the above-described variable shaping beam method. Therefore, the number of shots can be reduced as compared with the case where all patterns are exposed by using the variable shaped beam method, so that the throughput can be further improved. In this case, the aperture in which the pattern has been formed in advance looks like a reticle, but the reticle is provided for each specific layer in a specific device, whereas the aperture in the partial batch method uses the same pattern. The reticle is essentially different from the reticle because it is used for a plurality of devices.
[0007]
FIG. 4 shows a configuration example of an apparatus for performing electron beam exposure using the partial batch method. The electron beam 4 emitted from the electron source 3 is shaped into a rectangular shape by a first aperture 5 for beam shaping. Thereafter, the electron beam 4 that has passed through the first aperture 5 is polarized by a polarizer (not shown) so as to pass through a selected pattern on the second aperture 6. On the second aperture 6, a pattern previously extracted as a pattern to be subjected to partial batch exposure is formed. After that, the electron beam 4 is reduced by an objective lens and a polarizer (not shown), and then the pattern on the second aperture 6 is transferred to a desired position on the wafer 7. Subsequently, the stage 8 on which the wafer 7 is mounted moves, and exposure is performed on a region different from the region on which exposure was previously performed.
[0008]
As described above, the pattern on the semiconductor chip is divided and arranged on the aperture, and the electron beam moves relative to the wafer for each shot, whereby a desired pattern is drawn.
[0009]
However, as described above, in the partial batch method, a pattern with a large number of repetitions is exposed using an aperture, whereas a pattern with a small number of repetitions is exposed by a variable shaped beam method. A conventional example of forming a pattern with a small number of repetitions will be described below.
[0010]
FIG. 5 is an example of a plan view of a wiring pattern transferred onto a semiconductor chip. In the figure, reference numeral 9 denotes a pad pattern electrically connected to the electrode terminals of the semiconductor chip. Reference numerals 10 and 11 denote linear wiring pattern portions provided to be connected to the pad portion pattern 9. That is, the wiring pattern 12 in the figure represents an example in which the pad portion pattern 9 is formed between the linear wiring pattern portions 10 and 11. In such a case, conventionally, for example, after the linear wiring pattern portion 10 is shot, the electron beam is moved to shoot the pad portion pattern 9 and the electron beam is further moved to shoot the linear wiring pattern portion 11. To form the wiring pattern 12. That is, a total of three shots were required to form the wiring pattern 12.
[0011]
FIG. 6 is another example of a plan view of a wiring pattern transferred onto a semiconductor chip. In the illustrated wiring pattern 13, a pad portion pattern 15 is formed at an end of a linear wiring pattern portion 14. Even in such a case, the wiring pattern 13 is conventionally formed by, for example, shooting the linear wiring pattern 14 and then moving the electron beam to shoot the pad portion pattern 15. That is, a total of two shots were required to form the wiring pattern 13. Further, since these shots were performed with the same exposure amount, an exposure time equal to (exposure time required for one shot) × (number of shots) was required.
[0012]
As described above, the partial batch method can reduce the total number of shots as compared with the variable shaped beam method, but it is necessary to perform exposure using the variable shaped beam method for a pattern with few repetitions. Therefore, the improvement of the throughput was not enough. For example, the processing speed of an 8-inch size wafer is about several wafers per hour, which is far from practical use in terms of productivity.
[0013]
On the other hand, in the electron beam exposure technology, as in the case of the light exposure technology, there has been a growing interest in introducing a reticle having the same image as that of a semiconductor chip. Under these circumstances, an electron beam projection lithography technique has been proposed, which attempts to realize a throughput similar to that of the photolithography technique by collectively transferring a reticle image. For example, it is being embodied as a technique called SCALPEL by a group of AT & T Bell Laboratories, and a technique called PREVAIL by a joint research and development organization of Nikon Corporation and IBM Japan, Ltd. However, this method completely eliminates the pattern creation function, which is the greatest feature of the electron beam exposure technique, and has a problem that the success or failure of the technique depends on the mask.
[0014]
The present invention has been made in view of such a problem. That is, the present invention provides an electron beam exposure method capable of improving the throughput while utilizing the pattern creation function, a semiconductor device manufactured using the electron beam exposure method, an exposure pattern data processing method, and an exposure pattern It is an object to provide a program for processing data.
[0015]
Other objects and advantages of the present invention will become apparent from the following description.
[0016]
[Means for Solving the Problems]
The present invention provides an electron beam exposure method for exposing an integrated circuit pattern having a rectangular pad portion pattern positioned by dividing a wiring pattern onto a substrate surface with an electron beam. Performing a first step of dividing a plurality of rectangular patterns extending and overlapping at the position of the pad portion pattern into a plurality of rectangular patterns having dimensions equal to or less than the maximum shot size of the electron beam; A second step of performing multiple exposure at the position of the pad pattern by sequentially exposing a plurality of rectangular patterns divided in the step is characterized. The electron beam may be applied to a thin film formed on the substrate. For example, the semiconductor substrate may be irradiated with an electron beam. The rectangular pattern is a pattern connected to the wiring pattern, and a plurality of rectangular patterns are positioned so as to overlap at the position of the pad pattern.
[0017]
According to the present invention, the area of the pad portion pattern can be controlled by changing the area where a plurality of rectangular patterns extending from each wiring pattern overlap in the first step.
[0018]
The present invention also relates to an electron beam exposure method for exposing an integrated circuit pattern having a rectangular pad portion pattern connected at an end of one wiring pattern to a substrate surface with an electron beam. Performing a first step of dividing the pattern to which the rectangular pattern is added into a plurality of rectangular patterns having dimensions equal to or smaller than the maximum shot size of the electron beam, and then exposing the plurality of rectangular patterns divided in the first step to a predetermined exposure A second step of exposing the pad portion pattern to a rectangular pattern having a predetermined dimension added to the wiring pattern with an exposure amount smaller than the exposure amount, while exposing the pad portion pattern sequentially. The electron beam may be applied to a thin film formed on the substrate. For example, the semiconductor substrate may be irradiated with an electron beam.
[0019]
The present invention also relates to an electron beam exposure method for exposing an integrated circuit pattern having a rectangular pad portion pattern connected at an end of one wiring pattern to a substrate surface with an electron beam. Performing a first step of dividing the pattern to which the rectangular pattern is added into a plurality of rectangular patterns having a size equal to or smaller than the maximum shot size of the electron beam, and then forming a pad portion pattern having a size equal to or smaller than the maximum shot size of the electron beam; A second step of dividing into a plurality of rectangular patterns is performed, and further, the rectangular patterns divided in the first step are sequentially exposed at a predetermined exposure amount, and the plurality of rectangular patterns divided in the second step are subjected to this exposure. The third step is to perform a third step of exposing a rectangular pattern of a predetermined size added to the wiring pattern with an exposure amount smaller than the exposure amount. To. The electron beam may be applied to a thin film formed on the substrate. For example, the semiconductor substrate may be irradiated with an electron beam.
[0020]
The wiring pattern can be a groove wiring pattern, and in that case, a film made of a positive resist can be formed on the substrate surface.
[0021]
The wiring pattern may be a wiring pattern other than the groove wiring, and in that case, a film made of a negative resist can be formed on the substrate surface.
[0022]
The present invention also relates to a semiconductor device manufactured by using the above-mentioned electron beam exposure method.
[0023]
Further, the present invention provides an exposure pattern data processing method used for an electron beam exposure apparatus, wherein a first step of extracting a rectangular pad portion pattern located by dividing a wiring pattern from the exposure pattern data; Each wiring pattern divided by the pad pattern extracted in the process and a plurality of rectangular patterns extending from the respective wiring patterns and overlapping at the position of the pad pattern are dimensioned to be smaller than the maximum shot size of the electron beam. A second step of dividing into a plurality of rectangular patterns, a third step of extracting a rectangular pad pattern connected at an end of one wiring pattern from the exposure pattern data, and a third step of extracting the same. A pattern obtained by adding a rectangular pattern with a predetermined size to the wiring pattern connected to the pad pattern A fourth step of dividing the pad pattern extracted in the third step into a plurality of rectangular patterns each having a size equal to or smaller than the first size, and a fifth step of giving the pad portion pattern extracted in the third step an exposure amount smaller than that of the rectangular pattern divided in the fourth step And a sixth step of dividing a wiring pattern not connected to the pad portion pattern extracted in the first step or the third step into a plurality of rectangular patterns having a size equal to or less than the maximum shot size of the electron beam. The present invention relates to an exposure pattern data processing method characterized by having: Here, the rectangular pattern is a pattern connected to the wiring pattern, and a plurality of rectangular patterns are positioned so as to overlap at the position of the pad pattern.
[0024]
Further, the present invention provides an exposure pattern data processing method used for an electron beam exposure apparatus, wherein a first step of extracting a rectangular pad portion pattern located by dividing a wiring pattern from the exposure pattern data; Each of the wiring patterns divided by the pad pattern extracted in the process and a plurality of rectangular patterns extending from the respective wiring patterns and overlapping at the positions of the pad patterns have dimensions smaller than the maximum shot size of the electron beam. A second step of dividing into a plurality of rectangular patterns, a third step of extracting a rectangular pad pattern connected at an end of one wiring pattern from the exposure pattern data, and a pad extracted in the third step The pattern that is obtained by adding a rectangular pattern of a predetermined size to the wiring pattern connected to the A fourth step of dividing the pad pattern extracted in the third step into a plurality of rectangular patterns having a size equal to or less than the maximum shot size of the electron beam; A step of providing the rectangular pattern divided in the fifth step with a smaller exposure amount than the rectangular pattern divided in the fourth step, and a pad extracted in the first step or the third step And a seventh step of dividing a wiring pattern that is not connected to the external pattern into a plurality of rectangular patterns having a size equal to or less than the maximum shot size of the electron beam. Here, the rectangular pattern is a pattern connected to the wiring pattern, and a plurality of rectangular patterns are positioned so as to overlap at the position of the pad pattern.
[0025]
Further, the present invention is a program for processing exposure pattern data used for an electron beam exposure apparatus, wherein a first pattern for extracting a rectangular pad portion pattern positioned by dividing a wiring pattern from the exposure pattern data is provided. The processing is performed by dividing each wiring pattern divided by the pad pattern extracted in the first processing and a plurality of rectangular patterns extending from each wiring pattern and overlapping at the position of the pad pattern with the maximum shot of the electron beam. A second process of dividing into a plurality of rectangular patterns having a size equal to or smaller than the size, a third process of extracting a rectangular pad portion pattern connected at an end of one wiring pattern from the exposure pattern data, A pattern obtained by adding a rectangular pattern of a predetermined size to the wiring pattern connected to the pad pattern extracted in the process A fourth process for dividing the pattern into a plurality of rectangular patterns having a size equal to or less than the maximum shot size of the system, and providing the pad portion pattern extracted in the third process with an exposure amount smaller than the rectangular pattern divided in the fourth process. Fifth processing and sixth processing of dividing the wiring pattern not connected to the pad pattern extracted in the first processing or the third processing into a plurality of rectangular patterns having a size equal to or less than the maximum shot size of the electron beam. And a program for causing a computer to execute the processing. Here, the rectangular pattern is a pattern connected to the wiring pattern, and a plurality of rectangular patterns are positioned so as to overlap at the position of the pad pattern.
[0026]
Further, the present invention is a program for processing exposure pattern data used in an electron beam exposure apparatus, wherein a program for extracting a rectangular pad portion pattern positioned by dividing a wiring pattern from the exposure pattern data is provided. Processing, a plurality of wiring patterns divided by the pad pattern extracted in the first processing, and a plurality of rectangular patterns extending from the wiring patterns and overlapping at the positions of the pad patterns are formed by the maximum of the electron beam. A second process of dividing into a plurality of rectangular patterns having a size equal to or smaller than the shot size, a third process of extracting a rectangular pad portion pattern connected at an end of one wiring pattern from the exposure pattern data, A pattern obtained by adding a rectangular pattern of a predetermined dimension to the wiring pattern connected to the pad pattern extracted in the process of Step 3 Fourth processing for dividing into a plurality of rectangular patterns having a size equal to or less than the maximum shot size of the child beam, and a plurality of rectangular patterns having a size equal to or less than the maximum shot size for the electron beam A sixth process of giving the rectangular pattern divided by the fifth process an exposure amount smaller than that of the rectangular pattern divided by the fourth process; a first process or a third process And a seventh process of dividing a wiring pattern not connected to the pad pattern extracted in step (b) into a plurality of rectangular patterns having a size equal to or smaller than the maximum shot size of the electron beam. Here, the rectangular pattern is a pattern connected to the wiring pattern, and a plurality of rectangular patterns are positioned so as to overlap at the position of the pad pattern.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0028]
Embodiment 1 FIG.
FIG. 1A is a plan view of a wiring pattern transferred according to the present embodiment. As shown in the drawing, the wiring pattern 1 according to the present embodiment has a structure in which a rectangular pad pattern c is formed between linear wiring patterns a and b. In other words, the pad portion pattern c is located by dividing the wiring pattern having the linear wiring pattern portions a and b. Here, the pad portion refers to a region in which a connection hole such as a contact hole or a through hole is provided, and has a size larger than a wiring width defined by a design rule in consideration of a positional accuracy of superposition with the connection hole. Refers to a part that is formed as follows. The connection hole may be formed above the wiring layer or may be formed below the wiring layer.
[0029]
FIG. 1B is a plan view for explaining a method of forming the wiring pattern 1 shown in FIG. 1A according to the present embodiment.
[0030]
In the present embodiment, first, the linear wiring pattern portions a and b generated by dividing the wiring pattern portion by the pad portion pattern c, and the pad extending from the linear wiring pattern portions a and b are formed. A rectangular pattern overlapping at the position of the partial pattern c (rectangular patterns A ′ and B ′ in FIG. 1B) is divided into a plurality of rectangular patterns having dimensions smaller than the maximum shot size of the electron beam. Next, multiple exposure is performed at a position corresponding to the pad portion pattern c by sequentially exposing the plurality of divided rectangular patterns. Hereinafter, this will be described in detail with reference to FIG.
[0031]
In forming the wiring pattern 1 shown in FIG. 1A, first, a first shot is performed on the rectangular pattern A shown in FIG. 1B. At this time, the dimension L in the longitudinal direction of the rectangular pattern A 1 1A is a longitudinal dimension l of the linear wiring pattern portion a in FIG. 1 And a predetermined dimension L is added to the value. Here, the predetermined dimension L is shorter than the dimension 1 of the pad pattern c.
[0032]
Next, a second shot for the rectangular pattern B is performed by changing the irradiation position of the electron beam. The movement of the irradiation position of the electron beam may be achieved by moving an XY stage on which a wafer (not shown) is mounted, or may be achieved by applying polarized light to the electron beam. . Similarly to the first shot, the dimension L in the longitudinal direction of the rectangular pattern B 2 1A is a longitudinal dimension l of the linear wiring pattern portion b in FIG. 2 And a predetermined dimension L ′. Here, the predetermined dimension L 'is smaller than the dimension l' of the pad portion pattern c.
[0033]
In the present embodiment, the first shot and the second shot are arranged such that the rectangular pattern A 'having the predetermined dimension L in the rectangular pattern A and the rectangular pattern B' having the predetermined dimension L 'in the rectangular pattern B overlap. Is performed. Note that the order of the first shot and the second shot may be reversed. Further, the rectangular patterns A and B need to have a size smaller than the maximum shot size of the electron beam. When these dimensions are equal to or larger than the maximum shot size of the electron beam, after dividing into smaller rectangular patterns, shots are sequentially performed on these rectangular patterns.
[0034]
By doing so, a portion where the rectangular pattern A 'and the rectangular pattern B' overlap (hereinafter, referred to as an overlapping portion) is double-exposed. That is, the overlapping portion is irradiated with the electron beam having an exposure amount twice as large as the exposure amount required to form the rectangular patterns A and B. Therefore, the overlap portion that is excessively exposed has a larger size due to the stored energy than the portion other than the overlap portion that has been exposed with an appropriate amount (the portion that is not double-exposed).
[0035]
For example, if a negative resist is used to pattern the underlying thin film, the insolubilized area of the resist with respect to the developer in the double-exposed portion becomes larger than in the other portions, so that the resist remains after the resist is peeled off. The dimension of the underlying thin film becomes large in the double exposure portion, that is, in the portion corresponding to the pad portion pattern. On the other hand, when a positive resist is used to form the grooved wiring, on the other hand, the area of the resist exposed to the double exposure becomes solubilized in the developing solution as compared with the other parts, so that the pad The dimensions of the portion corresponding to the partial pattern are increased.
[0036]
The present invention is characterized in that the overlap portion having the increased size is used as a pad portion pattern c shown in FIG. That is, according to the method of the present embodiment, only the first shot and the second shot for forming the rectangular patterns A and B are performed without performing the shot for forming the pad portion pattern. Since the pad portion pattern is formed by using the overlap of the rectangular pattern A 'and the rectangular pattern B' formed by the above, the number of shots conventionally required three times can be reduced to two.
[0037]
The dimension L of the rectangular pattern A 'and the dimension L' of the rectangular pattern B 'are set to appropriate values based on the design value of the pad pattern and the sensitivity of the resist used. Here, since the dimensions L and L 'are correlated with the area of the portion where the rectangular patterns overlap, the above can be paraphrased as follows. That is, the dimensional control of the pad portion pattern formed according to the present embodiment can be controlled by controlling the area of a portion where these rectangular patterns overlap. More specifically, if the first shot and the second shot are set so that the area of the overlapping portion becomes large, the area of the double-exposed portion becomes large. Can be formed. Conversely, if the first shot and the second shot are set so that the area of the overlapping portion is reduced, the area of the double-exposed portion is reduced, so that a pad pattern with a small size is formed. be able to. At this time, if the sensitivity of the resist used is high, the area of the pad portion pattern formed by the double exposure becomes large even if the area of the overlapping portion is small.
[0038]
In the present embodiment, an example in which a pad portion pattern is formed by performing double exposure has been described, but the present invention is not limited to this. Any device that forms a pad pattern by multiple exposure is included in the scope of the present invention. For example, when forming a wiring pattern in which three linear wiring pattern portions are connected to a pad portion pattern, the three linear wiring pattern portions should be overlapped near the wiring ends, respectively. A first shot, a second shot, and a third shot are performed. By doing so, the portion where the shots overlap is triple-exposed and the dimensions increase, so if the overlapping portion with the increased dimensions is used as a pad pattern, a wiring pattern can be formed in a total of three shots. Can be. That is, the number of shots, which was conventionally required four times, can be reduced to three times.
[0039]
The dimensions of the formed pad portion pattern also vary depending on the number of times of multiple exposure. For example, since the number of exposures is different between the double exposure and the triple exposure, the size of the formed pad portion pattern is larger in the triple-exposed portion than in the double-exposed portion. In this case, in order to make the dimensions of the pad portion patterns the same, adjustments may be made such that the overlap of the linear wiring pattern portions in the triple exposure portion is reduced. However, even when a difference occurs in the area of the pad portion pattern due to a difference in the number of times of the multiple exposure, such a difference is within the range of the dimension specified by the design rule, and the alignment with the connection hole is not performed. If the required margin can be secured, the above adjustment is unnecessary.
[0040]
Further, in the present embodiment, an example has been described in which one linear wiring pattern portion connected to the pad portion pattern is perpendicular to another linear wiring pattern portion. It is not limited to. The present invention can be applied to any pad pattern positioned so as to divide the wiring pattern. For example, the present invention can be applied to an example in which linear wiring pattern portions are connected to a pad portion pattern so as to form an angle of 180 degrees with each other.
[0041]
As described above, according to the present embodiment, since the pad portion pattern is formed using multiple exposure, it is not necessary to perform the shot of the pad portion pattern, which has been conventionally performed independently. Therefore, the total number of shots can be reduced, and the throughput can be improved.
[0042]
Embodiment 2 FIG.
FIG. 2A is a plan view of a wiring pattern transferred according to the present embodiment. As shown in the drawing, the wiring pattern 2 in the present embodiment has a structure in which a rectangular pad pattern e is connected to an end of a linear wiring pattern d. Here, the pad portion refers to a region in which a connection hole such as a contact hole or a through hole is provided, and has a size larger than a wiring width defined by a design rule in consideration of a positional accuracy of superposition with the connection hole. Refers to a part that is formed as follows. The connection hole may be formed above the wiring layer or may be formed below the wiring layer.
[0043]
FIG. 2B is a plan view for explaining a method of forming the wiring pattern 2 shown in FIG. 2A according to the present embodiment.
[0044]
In this embodiment, first, a rectangular pattern C obtained by adding a rectangular pattern C ′ having a predetermined size in FIG. 2B to the linear wiring pattern portion d in FIG. It is divided into rectangular patterns having dimensions smaller than the size. Next, the divided rectangular patterns are sequentially exposed with a predetermined exposure amount, and the pad portion pattern D is exposed on the rectangular pattern C 'with an exposure amount smaller than this exposure amount. Hereinafter, this will be described in detail with reference to FIG.
[0045]
In forming the wiring pattern 2 shown in FIG. 2A, first, a first shot is performed on the rectangular pattern C shown in FIG. 2B. At this time, the dimension L in the longitudinal direction of the rectangular pattern C 3 1A is a longitudinal dimension l of the linear wiring pattern portion a in FIG. 3 And a predetermined dimension L ″. Here, the predetermined dimension L ″ is shorter than the length l ″ of the pad pattern e.
[0046]
Next, the irradiation position of the electron beam is changed, and a second shot for the pad portion pattern D is performed. Here, the exposure amount of the second shot is smaller than the exposure amount of the first shot. The movement of the irradiation position of the electron beam may be achieved by moving an XY stage on which a wafer (not shown) is mounted, or may be achieved by applying polarized light to the electron beam. The dimensions of the pad pattern D are determined from the dimensions of the pad pattern e to be formed in the same manner as in the related art.
[0047]
The present embodiment is characterized in that the first shot and the second shot are performed such that the rectangular pattern C ′ having a predetermined dimension L ″ in the rectangular pattern C and the pad portion pattern D overlap. In addition, the order of the first shot and the second shot may be reversed, and the rectangular pattern C and the pad portion pattern D need to be smaller than the maximum shot size of the electron beam. When these dimensions are equal to or larger than the maximum shot size of the electron beam, after dividing into smaller rectangular patterns, shots are sequentially performed on these rectangular patterns.
[0048]
By doing so, a portion where the rectangular pattern C ′ and the pad portion pattern D overlap (hereinafter, referred to as an overlap portion) is double-exposed. Therefore, the size of the overlapped portion becomes larger than the size of the portion not double-exposed due to the stored energy. The present invention is characterized in that the overlapping portion having the increased dimension is used as a pad portion pattern e shown in FIG.
[0049]
In the present embodiment, unlike the first embodiment, a second shot for forming a pad portion pattern is performed in addition to the first shot as in the conventional case. However, in the present embodiment, when the first shot is performed on the linear wiring pattern portion, the portion including the pad portion pattern is shot, and the energy accumulated at this time is used to form the pad portion pattern. Since the second shot is performed, the exposure amount when the pad pattern is shot can be reduced as compared with the related art. Here, since the exposure amount is controlled by the exposure time, the fact that the exposure amount can be reduced means that the exposure time can be shortened. That is, according to the present embodiment, although the number of shots is the same as in the conventional method, the overall exposure time required for forming the wiring pattern can be made shorter than in the conventional method, so that the throughput can be improved. it can.
[0050]
The degree to which the exposure amount of the second shot for forming the pad portion pattern can be made smaller than the exposure amount of the first shot for forming the linear wiring pattern depends on the resist used. Depends on the sensitivity. In general, the greater the sensitivity of the resist, the greater the dimensional variation can be obtained with a smaller exposure. Therefore, the exposure amount of the second shot can be reduced when a resist having a high sensitivity is used as compared with a case where a resist having a low sensitivity is used. In the case of using a chemically amplified resist, a resist that positively utilizes diffusion, that is, a resist having a longer diffusion length can reduce the exposure amount of the second shot.
[0051]
The resist used in the present embodiment may be a negative type or a positive type. For example, when using a negative resist to pattern the underlying thin film, the insolubilized area of the resist with respect to the developer in the double-exposed portion becomes larger than other portions, and thus remains after the resist is stripped. The dimension of the underlying thin film becomes large in the double exposure portion, that is, in the portion corresponding to the pad portion pattern. On the other hand, when a positive resist is used to form the grooved wiring, on the other hand, the area of the resist exposed to the double exposure becomes solubilized in the developing solution as compared with the other parts, so that the pad The dimensions of the portion corresponding to the partial pattern are increased.
[0052]
As described above, according to the present embodiment, since the pad portion pattern is formed using multiple exposure, the exposure amount of the second shot can be reduced as compared with the related art. Therefore, the exposure time can be shorter than the conventional exposure time equal to (exposure time required for one shot) × (the number of shots), so that the throughput can be improved.
[0053]
Embodiment 3 FIG.
FIG. 3 shows an exposure pattern data processing method used in the electron beam exposure method according to the present invention. As shown in FIG. 3, first, a pad portion pattern is extracted from the exposure pattern data. Specifically, a portion (contact node) where a connection hole is formed is detected from the integrated circuit design pattern data. Since the connection hole may be formed in either the upper part or the lower part of the wiring layer, the pad portion pattern is obtained by comparing the data of the target wiring layer with the data of the upper connection hole layer and the data of the lower connection hole layer. Is extracted.
[0054]
Next, if there is a pad portion pattern, a rectangular pad portion pattern located by dividing the wiring pattern is extracted from the pad portion pattern. Thereafter, each of the wiring patterns divided by the extracted pad portion pattern and a plurality of rectangular patterns extending from the respective wiring patterns and overlapping at the positions of the pad portion patterns are reduced in size to the maximum shot size of the electron beam. Into a plurality of rectangular patterns.
[0055]
Next, a rectangular pad portion pattern connected at the end of one wiring pattern is extracted. Thereafter, a pattern obtained by adding a rectangular pattern having a predetermined size to the wiring pattern connected to the extracted pad portion pattern is divided into a plurality of rectangular patterns having a size equal to or smaller than the maximum shot size of the electron beam. If the extracted pad portion pattern has a size larger than the maximum shot size of the electron beam, it is divided into rectangular patterns having a size smaller than this. Next, an exposure amount smaller than that of the rectangular pattern obtained by dividing the wiring pattern is applied to the pad pattern or the rectangular pattern (which is obtained by dividing the pad pattern).
[0056]
Subsequently, a normal rectangular division is performed on a wiring pattern that is not connected to a rectangular pad portion pattern that is located by dividing the wiring pattern or a rectangular pad portion pattern that is connected at an end of one wiring pattern. That is, it is divided into a plurality of rectangular patterns having a size equal to or smaller than the maximum shot size by a rectangular electron beam unique to each electron beam exposure apparatus.
[0057]
Next, these rectangular division data are converted into a format specific to the electron beam exposure apparatus to be used.
[0058]
The above processing is repeated until the last pattern.
[0059]
According to the present embodiment, since the pad portion is formed by extracting the pad portion formation portion and using the multiple exposure for the portion, the throughput can be improved as compared with the conventional method.
[0060]
Further, according to the present embodiment, frequent updating of the mask as in the light exposure technique is not required, which is effective for cost reduction.
[0061]
【Example】
Embodiment 1 FIG.
The wiring layout data was created using a CAD (SX9000) for integrated circuits manufactured by Seiko Instruments Inc. This data was converted into a GDS-II stream format (GDS-II format) and then converted into a format for Hitachi electron beam lithography (PFH). At this time, self-made data conversion software capable of outputting data to which the exposure method according to the present invention is applicable was used. Thereafter, the converted data was input to an electron beam drawing apparatus HL800D (manufactured by Hitachi, Ltd.). The total number of figures for one chip was 4,203,594.
[0062]
Assuming groove-type wiring, a positive resist pattern was formed in the following procedure.
[0063]
First, a silicon oxide film having a thickness of 0.5 μm was formed on the surface of an 8-inch silicon wafer, and the surface was hydrophobized with hexamethyldisilazane vapor. Next, ZEP-520 (electron beam positive type resist manufactured by Zeon Corporation) was applied thereon, and soft baked at 110 ° C. for 90 seconds to form a 0.5 μm-thick resist film.
[0064]
Next, the wafer was transferred to a vacuum chamber of an electron beam drawing apparatus HL800D, and after positioning, the data was drawn. After the drawing, the film was taken out of the vacuum chamber, developed with a dedicated developer (mainly methyl ethyl ketone) by a dipping method, and then rinsed. After drying, etching was performed using a chlorine-based gas plasma using a parallel plate type dry etching apparatus. After the resist was peeled off with an RA stripper, it was washed with water and dried to obtain a silicon oxide film having a grooved wiring pattern formed thereon.
[0065]
The line width distribution of the obtained pattern was determined using a line width measuring device. Specifically, the line width was automatically read from a photograph taken using an SEM (scanning electron microscope) by pattern recognition, and the numerical value was input to an input device provided in the line width measuring device. As a result, it was found that the grooved wiring pattern was formed normally.
[0066]
In the present embodiment, the exposure amount in another rectangular pattern having no linear wiring pattern portion and no pad portion is 70 μC / cm. 2 The exposure amount at the pad portion was set to a smaller value. When 40 chips were exposed on the wafer, an exposure time of 70 minutes was required.
[0067]
Embodiment 2. FIG.
The wiring layout data was created using a CAD (SX9000) for integrated circuits manufactured by Seiko Instruments Inc. This data was converted into a GDS-II stream format (GDS-II format) and then converted into a format for Hitachi electron beam lithography (PFH). At this time, self-made data conversion software capable of outputting data to which the exposure method according to the present invention is applicable was used. Thereafter, the converted data was input to an electron beam drawing apparatus HL800D (manufactured by Hitachi, Ltd.). The total number of figures for one chip was 4,203,594.
[0068]
Assuming normal aluminum (Al) wiring, a negative resist pattern was formed in the following procedure.
[0069]
First, after forming a silicon oxide film with a thickness of 0.1 μm on the surface of an 8-inch silicon wafer, an alloy of aluminum (Al) / silicon (Si) / copper (Cu) with a thickness of 0.5 μm Was formed. Next, the surface was hydrophobized with hexamethyldisilazane vapor. Thereafter, NEB-22 (electron beam negative type resist manufactured by Sumitomo Chemical Co., Ltd.), which is a chemically amplified resist, was applied thereon, and soft-baked at 110 ° C. for 90 seconds to form a 0.5 μm-thick resist film. .
[0070]
Next, the wafer was transferred to a vacuum chamber of an electron beam drawing apparatus HL800D, and after positioning, the data was drawn. After the drawing is completed, the substrate is taken out of the vacuum chamber and subjected to PEB (Post Eposure Bake) at 110 ° C. for 90 seconds, then developed by a dipping method with a 2.38% aqueous solution of TMAH (tetramethylammonium hydroxide), washed with water, and dried. went. Using a parallel plate type dry etching apparatus, etching was performed by utilizing plasma of a chlorine-based gas. After the resist was peeled off with an RA stripper, it was washed with water and dried to obtain a wafer on which an aluminum wiring pattern was formed.
[0071]
The line width distribution of the obtained pattern was determined using a line width measuring device. Specifically, the line width was automatically read from a photograph taken using an SEM (scanning electron microscope) by pattern recognition, and the numerical value was input to an input device provided in the line width measuring device. As a result, it was found that the aluminum wiring pattern was formed normally.
[0072]
In this embodiment, the exposure amount in another rectangular pattern having no linear wiring pattern portion and no pad portion is 14 μC / cm. 2 The exposure amount at the pad portion was set to a smaller value. When 40 chips were exposed on the wafer, an exposure time of 48 minutes was required.
[0073]
[Comparative example]
Comparative Example 1
The wiring layout data was created using a CAD (SX9000) for integrated circuits manufactured by Seiko Instruments Inc. This data was converted into a GDS-II stream format (GDS-II format) and then converted into a format for Hitachi electron beam lithography (PFH). At this time, the data conversion software CATS of Transcription Enterprise was used. Thereafter, the converted data was input to an electron beam drawing apparatus HL800D (manufactured by Hitachi, Ltd.). The total number of figures for one chip was 4,412,347.
[0074]
Assuming groove-type wiring, a positive-type resist pattern was formed in the same procedure as in Example 1, and then a groove-type wiring pattern was formed on the silicon oxide film by etching.
[0075]
In this comparative example, the exposure amount was 70 μC / cm 2 And When 40 chips were exposed on the wafer, an exposure time of 88 minutes was required.
[0076]
Comparative Example 2.
The wiring layout data was created using a CAD (SX9000) for integrated circuits manufactured by Seiko Instruments Inc. This data was converted into a GDS-II stream format (GDS-II format) and then converted into a format for Hitachi electron beam lithography (PFH). At this time, the data conversion software CATS of Transcription Enterprise was used. Thereafter, the converted data was input to an electron beam drawing apparatus HL800D (manufactured by Hitachi, Ltd.). The total number of figures for one chip was 4,412,347.
[0077]
Assuming normal aluminum (Al) wiring, a negative resist pattern was formed in the same procedure as in Example 2, and then an aluminum wiring pattern was formed on the wafer by etching.
[0078]
In this comparative example, the exposure amount was 14 μC / cm 2 And When 40 chips were exposed on the wafer, an exposure time of 57 minutes was required.
[0079]
【The invention's effect】
According to the present invention, since a rectangular pad portion pattern positioned by dividing a wiring pattern is formed by using multiple exposure, it is necessary to perform a shot for forming a pad portion pattern, which has been conventionally performed independently. Gone. Therefore, the total number of shots can be reduced, and the throughput can be improved.
[0080]
Further, according to the present invention, since a rectangular pad portion pattern connected at the end of one wiring pattern is formed by using multiple exposure, the entire exposure time can be reduced as compared with the related art. Therefore, the throughput can be improved.
[Brief description of the drawings]
FIG. 1A is a plan view of a wiring pattern transferred according to a first embodiment, and FIG. 1B is a diagram illustrating a method of forming a wiring pattern according to the first embodiment.
FIG. 2A is a plan view of a wiring pattern transferred according to a second embodiment, and FIG. 2B is an explanatory diagram of a method of forming a wiring pattern according to the second embodiment.
FIG. 3 is a view showing an exposure pattern data processing method used in the electron beam exposure method according to the present invention.
FIG. 4 is a configuration diagram of an apparatus that performs electron beam exposure using a partial batch method.
FIG. 5 is a plan view of a conventional wiring pattern transferred onto a semiconductor chip.
FIG. 6 is a plan view of a conventional wiring pattern transferred onto a semiconductor chip.
[Explanation of symbols]
1, 2, 12, 13 wiring pattern, 3 electron source, 4 electron beam, 5 first aperture, 6 second aperture, 7 wafer, 8 stage, 9, 15, pad portion pattern, 10, 11, 14 linear Wiring pattern section.

Claims (11)

  1. An electron beam exposure method for exposing an integrated circuit pattern having a rectangular pad portion pattern positioned by dividing a wiring pattern to a substrate surface with an electron beam,
    Dividing each divided wiring pattern and a plurality of rectangular patterns extending from the respective wiring patterns and overlapping at the position of the pad portion pattern into a plurality of rectangular patterns having a size equal to or less than the maximum shot size of the electron beam. A first step of
    A second step of sequentially exposing a plurality of rectangular patterns divided in the first step to perform multiple exposure at the position of the pad portion pattern.
  2. 2. The electron beam exposure method according to claim 1, wherein an area of the pad portion pattern is controlled by changing an area where the plurality of rectangular patterns extending from each of the wiring patterns overlap in the first step.
  3. An electron beam exposure method for exposing an integrated circuit pattern having a rectangular pad portion pattern connected at an end of one of the wiring patterns to a substrate surface by an electron beam,
    A first step of dividing a pattern obtained by adding a rectangular pattern having a predetermined size to the wiring pattern into a plurality of rectangular patterns having a size equal to or smaller than a maximum shot size of the electron beam;
    A second step of sequentially exposing the plurality of rectangular patterns divided in the first step at a predetermined exposure amount and exposing the pad portion pattern to the rectangular pattern of the predetermined size with an exposure amount smaller than the exposure amount; And an electron beam exposure method.
  4. An electron beam exposure method for exposing an integrated circuit pattern having a rectangular pad portion pattern connected at an end of one of the wiring patterns to a substrate surface by an electron beam,
    A first step of dividing a pattern obtained by adding a rectangular pattern having a predetermined size to the wiring pattern into a plurality of rectangular patterns having a size equal to or smaller than a maximum shot size of the electron beam;
    A second step of dividing the pad pattern into a plurality of rectangular patterns having a size equal to or less than a maximum shot size of the electron beam;
    The plurality of rectangular patterns divided in the first step are sequentially exposed at a predetermined exposure amount, and the plurality of rectangular patterns divided in the second step are exposed at a smaller exposure amount than the rectangular pattern of the predetermined size. And a third step of sequentially exposing the substrate to the electron beam.
  5. 5. The electron beam exposure method according to claim 1, wherein the wiring pattern is a groove wiring pattern, and a film made of a positive resist is formed on the substrate surface.
  6. 5. The electron beam exposure method according to claim 1, wherein the wiring pattern is a wiring pattern other than the groove wiring, and a film made of a negative resist is formed on the substrate surface.
  7. A semiconductor device manufactured by using the electron beam exposure method according to claim 1.
  8. In an exposure pattern data processing method used for an electron beam exposure apparatus,
    A first step of extracting, from the exposure pattern data, a rectangular pad portion pattern that is located by dividing the wiring pattern;
    The maximum shot size of the electron beam is obtained by dividing each wiring pattern divided by the pad pattern extracted in the first step and a plurality of rectangular patterns extending from each wiring pattern and overlapping at the position of the pad pattern. A second step of dividing into a plurality of rectangular patterns having the following dimensions;
    A third step of extracting a rectangular pad pattern connected at an end of one wiring pattern from the exposure pattern data;
    A fourth step of dividing a pattern obtained by adding a rectangular pattern of a predetermined size to the wiring pattern connected to the pad pattern extracted in the third step into a plurality of rectangular patterns having a size equal to or less than the maximum shot size of the electron beam; Process and
    A fifth step of giving the pad portion pattern extracted in the third step a smaller amount of exposure than the rectangular pattern divided in the fourth step;
    And a sixth step of dividing the wiring pattern not connected to the pad portion pattern extracted in the first step or the third step into a plurality of rectangular patterns having a size equal to or less than the maximum shot size of the electron beam. An exposure pattern data processing method comprising:
  9. In an exposure pattern data processing method used for an electron beam exposure apparatus,
    A first step of extracting, from the exposure pattern data, a rectangular pad portion pattern that is located by dividing the wiring pattern;
    The maximum shot size of the electron beam is obtained by dividing each wiring pattern divided by the pad pattern extracted in the first step and a plurality of rectangular patterns extending from each wiring pattern and overlapping at the position of the pad pattern. A second step of dividing into a plurality of rectangular patterns having the following dimensions;
    A third step of extracting a rectangular pad pattern connected at an end of one wiring pattern from the exposure pattern data;
    A fourth step of dividing a pattern obtained by adding a rectangular pattern of a predetermined size to the wiring pattern connected to the pad pattern extracted in the third step into a plurality of rectangular patterns having a size equal to or less than the maximum shot size of the electron beam; Process and
    A fifth step of dividing the pad pattern extracted in the third step into a plurality of rectangular patterns having a size equal to or less than the maximum shot size of the electron beam;
    A sixth step of providing the rectangular pattern divided in the fifth step with a smaller exposure than the rectangular pattern divided in the fourth step;
    And a seventh step of dividing the wiring pattern not connected to the pad portion pattern extracted in the first step or the third step into a plurality of rectangular patterns having a size equal to or less than the maximum shot size of the electron beam. An exposure pattern data processing method comprising:
  10. A program for processing exposure pattern data used in an electron beam exposure apparatus,
    A first process of extracting a rectangular pad portion pattern positioned by dividing a wiring pattern from the exposure pattern data;
    Each of the wiring patterns divided by the pad pattern extracted in the first process and a plurality of rectangular patterns extending from the respective wiring patterns and overlapping at the positions of the pad patterns are defined as the maximum shot size of the electron beam. A second process of dividing into a plurality of rectangular patterns having the following dimensions;
    A third process of extracting a rectangular pad portion pattern connected at an end of one wiring pattern from the exposure pattern data;
    A fourth step of dividing a pattern obtained by adding a rectangular pattern having a predetermined size to the wiring pattern connected to the pad pattern extracted in the third process into a plurality of rectangular patterns having a size equal to or smaller than the maximum shot size of the electron beam; Processing,
    A fifth process of giving the pad portion pattern extracted in the third process an exposure amount smaller than that of the rectangular pattern divided in the fourth process;
    A sixth process of dividing a wiring pattern not connected to the pad portion pattern extracted in the first process or the third process into a plurality of rectangular patterns having a size equal to or less than the maximum shot size of the electron beam. Program to be executed.
  11. A program for processing exposure pattern data used in an electron beam exposure apparatus,
    A first process of extracting a rectangular pad portion pattern positioned by dividing a wiring pattern from the exposure pattern data;
    Each of the wiring patterns divided by the pad pattern extracted in the first process and a plurality of rectangular patterns extending from the respective wiring patterns and overlapping at the positions of the pad patterns are defined as the maximum shot size of the electron beam. A second process of dividing into a plurality of rectangular patterns having the following dimensions;
    A third process of extracting a rectangular pad portion pattern connected at an end of one wiring pattern from the exposure pattern data;
    A fourth step of dividing a pattern obtained by adding a rectangular pattern having a predetermined size to the wiring pattern connected to the pad pattern extracted in the third process into a plurality of rectangular patterns having a size equal to or smaller than the maximum shot size of the electron beam; Processing,
    A fifth process of dividing the pad pattern extracted in the third process into a plurality of rectangular patterns having a size equal to or smaller than the maximum shot size of the electron beam;
    A sixth process of giving a smaller exposure amount to the rectangular pattern divided by the fifth process than the rectangular pattern divided by the fourth process;
    A seventh process of dividing the wiring pattern not connected to the pad portion pattern extracted in the first process or the third process into a plurality of rectangular patterns having a size equal to or less than the maximum shot size of the electron beam. Program to be executed.
JP2002245671A 2002-08-26 2002-08-26 Method for exposing to electron beam, semiconductor device, method for processing exposure pattern data, and program Pending JP2004087715A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100818713B1 (en) 2007-03-23 2008-04-02 주식회사 하이닉스반도체 Lithography method for suppressing scum in exposure process
KR20120017668A (en) * 2010-08-19 2012-02-29 삼성전자주식회사 Method for manufacturing semiconductor devices
EP3371639A4 (en) * 2015-11-03 2019-07-03 Orbotech Ltd Stitchless direct imaging for high resolution electronic patterning

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100818713B1 (en) 2007-03-23 2008-04-02 주식회사 하이닉스반도체 Lithography method for suppressing scum in exposure process
US7774738B2 (en) 2007-03-23 2010-08-10 Hynix Semiconductor Inc. Lithography method for forming a circuit pattern
KR20120017668A (en) * 2010-08-19 2012-02-29 삼성전자주식회사 Method for manufacturing semiconductor devices
KR101646909B1 (en) 2010-08-19 2016-08-09 삼성전자주식회사 Method for manufacturing semiconductor devices
EP3371639A4 (en) * 2015-11-03 2019-07-03 Orbotech Ltd Stitchless direct imaging for high resolution electronic patterning
US10429742B2 (en) 2015-11-03 2019-10-01 Orbotech Ltd. Stitchless direct imaging for high resolution electronic patterning

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