JPH02234493A - Multi-layered board and manufacture thereof - Google Patents

Abstract

PURPOSE:To restrict the formation of a stepped potion due to multi-layering and hence improve flatness by forming a first layer conductor layer and further forming conductor layers on and after a second layer in an intermediate insulating layer. CONSTITUTION:An insulating substrate 11 is formed by etching and other methods, and a first layer conductor layer 31 connected to a via 13 of the insulating substrate 11 is buried in the insulating substrate 11 so as to be flush with the surface of the insulating substrate 11 to flatten the first layer. Further, a conductor layer formation part is formed in which part a conductor layer 63 is buried in laminated intermediate insulating layers 41, and is buried in the intermediate insulating layer 41 including a via communicating a lower layer conductor layer 31 so as to flush with the surface of the intermediate insulating layer 41 to flatten said each layer. The processing is repeated in response to the number of multi-layers. Hereby, a stepped portion produced owing to multilayers is prevented from being formed to improve the flatness.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a multilayer substrate, the purpose is to eliminate steps caused by multilayering and improve flatness, and the method involves forming multiple conductor layers having a predetermined pattern on an insulating substrate. In a method for manufacturing a multilayer board, a step of digging down a conductor layer forming portion in which a first conductor layer is formed at a position corresponding to a via provided in an insulating substrate; A step of embedding a first conductor layer in the same plane as the surface of an insulating substrate, and a step of laminating an intermediate insulating layer having a conductor layer forming portion in which the conductor layer is embedded and a via that conducts to the lower conductor layer. , a step of embedding a conductor layer in the via and conductor layer forming portion of the intermediate insulating layer in the same plane as the surface of the intermediate insulating layer.

[Industrial application field]

The present invention relates to a manufacturing method for improving the flatness of a multilayer substrate. [Conventional technology] A multilayer board is based on an insulating board (ceramic board).
A first layer thin film pattern (conductor layer) is created on top by a predetermined method, and an intermediate insulating layer (polyimide) having via holes connecting the thin film patterns of each layer is formed thereon. Thin film patterns and intermediate insulating layers are alternately laminated, and finally, thin film pads are placed to make contact with external components, and the product is completed by firing.

[Problem to be solved by the invention]

Incidentally, in recent years, multilayer boards have tended to have thicker conductor layers in order to improve power supply as electronic components to be mounted have become faster and more dense.

Therefore, in multilayer substrates manufactured using conventional manufacturing methods, the influence of the underlying thin film pattern is high. This increases the level difference in the thin film pattern in the upper layer, making it more likely to cause disconnection due to thermal expansion of the intermediate insulating layer, and the flatness of the outer conductor layer deteriorates due to the overlap, so the flatness of each layer pattern becomes large when multilayering. This has become an issue. On the other hand, in order to planarize each layer, a method of imparting flatness to polyimide as an intermediate insulating layer has been developed in recent years. In other words, polyimide is esterified to increase its molecular weight and increase the amount of resin components to absorb the unevenness of the thin film pattern and improve its flatness. It is not easy to obtain the same level of adhesion as the conventional method, and there is a problem in that the insulating layer peels off between the eyebrows.

Further, even when such polyimide is used, the flatness is not perfect, and at present, a step difference of several μm occurs. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a multilayer substrate that can eliminate steps caused by multilayering and improve flatness, and the multilayer substrate. [Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention.

The method of manufacturing a multilayer substrate according to the present invention, in which conductor layers having a predetermined pattern are formed in multiple layers on an insulating substrate, includes, in a first step, a conductor layer of the first layer being formed in a position corresponding to a via provided in the insulating substrate. Dig down the conductor layer forming area where the conductor layer will be formed.

In the second step, a first conductor layer is embedded in the conductor layer forming portion of the insulating substrate in the same plane as the surface of the insulating substrate.

In the third step, an intermediate insulating layer is laminated which has a conductor layer forming portion in which a via and a conductor layer are embedded, which are electrically connected to the underlying conductor layer.

In the fourth step, a conductor layer is embedded in the via and conductor layer forming portion of the intermediate insulating layer in the same plane as the surface of the intermediate insulating layer. Thereafter, the third step and fourth step are repeated to form multiple layers.

Note that the intermediate insulating layer is preferably formed using photosensitive polyimide by a repeat exposure method or a repeat coating method.

Further, it is preferable to include a step of forming a silicon dioxide layer on the insulating substrate and the first conductor layer, and etching away the silicon dioxide layer in the conductive via of the intermediate insulating layer laminated thereon.

In addition, a multilayer board has a conductor layer formed in the same plane as the surface of the insulating substrate at a position corresponding to the via provided in the insulating substrate, and a via that is electrically connected to the lower conductor layer, and is laminated. At the positions corresponding to the intermediate insulating layer and the vias in the intermediate insulating layer,
This structure includes a conductor layer formed in the same plane as the surface of the intermediate insulating layer.

[Function] According to the present invention, an insulating substrate is dug down by etching or other method, and the insulating substrate is flush with the surface thereof.
By embedding the first conductive layer connected to the vias of the insulating substrate, the first layer can be planarized.

In addition, a conductor layer forming part is formed in which the conductor layer is embedded in the intermediate insulating layer to be laminated, and each layer is flush with the surface of the intermediate insulating layer, including vias that conduct to the lower conductor layer. By embedding the conductor layer, each layer can be flattened. Note that this process is repeated depending on the number of layers.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings. FIG. 2 is a sectional view illustrating each step of a manufacturing method according to an embodiment of the present invention.

Figure 2 (1) shows a glass ceramic or other insulating substrate (
Hereinafter referred to as "ceramic". ) 11, and has a via metal 13 that serves as a signal path from the inside (opposite side).

FIG. 2(2) shows the state of the first layer thin film pattern forming part connected to the metal.

The thin film pattern forming section first polishes the surface of the ceramic 11, then applies a thick film of plasma-resistant resist, and forms a pattern by exposing and developing the resist. Next, using an ion milling device, ceramic 11? and via metal 13 to a predetermined thickness, and then using a RrE (reactive ion etching) device, a predetermined gas (C
F. +0■), the top portion of the metal 13 is etched away, and a portion for forming the first layer thin film pattern is formed.

Note that this process is used not only to form a first layer thin film pattern in the same plane as the ceramic surface, but also to avoid the possibility that the sintered density of the via metal obtained by firing becomes coarse and voids and other defects occur. This is done to repair the defect by plugging the dug-out area with a low-melting metal paste.

Next, the resist layer applied to the surface of the ceramic 11 is removed using the stripping solution, and the exposed alumina (Altos) that was mixed in the ceramic but was not ion-milled or etched is superimposed using Freon or other organic solvent. Remove with sonic cleaning.

FIG. 2(3) shows the state of surface treatment of the first layer thin film pattern 31 and ceramic 11 connected to the via metal.

The thin film pattern 31 of the first layer is formed by filling the formation area with a low melting point metal paste from the ceramic surface using a squeegee, wiping off the low melting point metal paste adhering to the surface other than the pattern, and then baking at 550 to 600°C. Create it. Further, the low melting point metal paste metallized on the surface is polished by boring to make it flush with the ceramic l1.

Note that it is desirable to use the same metal as the low melting point metal paste in order to prevent mismatch with the via metal 13.

Subsequently, in order to prevent diffusion of the polyimide of the intermediate insulating layer formed thereon and the copper of the low melting point metal paste, a chromium layer 33 is formed on the first layer thin film pattern 31 by a lift-off method. Furthermore, in order to prevent the diffusion of sodium oxide and polyimide in the ceramic, a silicon dioxide layer 35 is spatter-formed over the entire surface of the ceramic 11 including the thin film pattern. FIG. 2(4) shows the state of the intermediate insulating layer 41 formed on the first layer thin film pattern 31 and the formation portion of the second layer thin film pattern.

The intermediate insulating layer 4l is made of photosensitive polyimide, and is formed by a repeat exposure method or a repeat coating method to form a thin film pattern forming portion in which the thin film pattern of the second layer is embedded, and a via that is electrically connected to the thin film pattern 31 of the first layer. Create a forming part. In other words, in the repeat exposure method, when a negative type photosensitive polyimide is used, the third exposure method is first applied.
The shaded area (thin film pattern of the second layer) shown in Figure (1) is masked and exposed at a predetermined exposure amount A, and then as shown in Figure 3 (2).
Shaded area shown in (via that conducts to the thin film pattern of the first layer)
In this method, a thin film pattern forming portion of an intermediate insulating layer having conductive vias as shown in FIG. 3(3) is created by masking and exposing at a predetermined % exposure amount and then developing.

In addition, in the repeat coating method, the via formation portion that is electrically connected to the thin film pattern of the first layer shown in Figure 4 (1) is removed and calcined, and then the second layer shown in Figure 4 (2) is coated. By performing final firing after removing the thin film pattern forming part, an intermediate insulation with conductive vias can be created. This is a method of creating a thin film pattern forming portion of the layer.

In addition, in FIG. 2 (4), after the formation of the intermediate insulating layer 4l, there is a silicon dioxide layer 35 at the bottom of the conductive via, so it is removed by a predetermined method (CF4 + NZ + 0■ plasma etching). do.

Figure 2 (5) shows that a three-layer film of chromium, titanium, and copper is successively sputtered onto the entire surface of the substrate in the state shown in Figure 2 (4) in order to form a second layer thin film pattern. The plated base 5L is shown. Note that chromium is used to enhance the adhesion to the polyimide of the intermediate insulating layer 41, and titanium is used to enhance the adhesion effect between chromium and copper.

Next, a resist layer 61 as shown in FIG. 2(6) is created so as to expose only the part where the thin film pattern of the second layer is to be formed (electrodeposition part), and is placed on the same surface as the surface of the intermediate insulating layer 41. Copper plating and nickel plating are performed to form a second layer thin film pattern 63. Note that the leveling properties of copper and nickel are adjusted using a brightening agent or the like so that the flatness of each is improved.

Next, in order to remove the resist layer 61 and remove the plating base 5l outside the second layer thin film pattern 63, the second layer thin film pattern 63 is protected with a photoresist and etched.

FIG. 2(7) shows the state of the second layer thin film pattern 63 formed on the intermediate insulating layer 41.

Since the second layer thin film pattern 63 has a nickel surface, in order to improve the adhesion with the polyimide of the intermediate insulating layer laminated thereon, a lift-off film similar to that used for the first layer thin film pattern 31 is applied. A copper layer 7l is sputter-formed on the second layer thin film pattern 63 by a method.

In the above steps, the first layer thin film pattern 31, the intermediate insulating layer 41, and the second layer thin film pattern 63 are formed on the ceramic 11.
The formation of is completed, but the multilayering is as shown in Fig. 2 (4) to Fig. 2 (
This is carried out by repeating the step 7).

In this manner, the manufacturing method according to the present invention embeds the thin film pattern of each layer in the ceramic 11 or the intermediate insulating layer 41, and further improves the adhesion between the polyimide of the ceramic 11 or the intermediate insulating layer 41 and the thin film pattern. By stacking the layers on a flat surface, flattening of the multilayer structure is realized.

This example shows an example of the method and procedure for forming each part in each step, and the present invention can be implemented as long as it has the same effect, including the type of metal used. It is possible.

〔Effect of the invention〕

As described above, according to the present invention, the first conductor layer (thin film pattern) is formed within the insulating substrate, and the second and subsequent conductor layers (thin film pattern) are formed within the intermediate insulating layer (polyimide). By doing so, it is possible to minimize the occurrence of steps caused by multilayering and improve flatness.

Therefore, a multilayer substrate with high reliability and high density can be easily manufactured.

In addition, since it is easy to eliminate the level difference due to multilayering, a sputtered film that is weak against lateral stress can be used, and an all-dry process can be realized.

Furthermore, since defects in firing of vias provided in an insulating substrate can be repaired, blistering and disconnection of thin film patterns due to via voids can be prevented, which is extremely useful in practice.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a sectional view explaining each step of a manufacturing method according to an embodiment of the present invention, Fig. 3 is a diagram explaining the repeat exposure method, and Fig. 4 is a repeat coating. FIG. 4l 7l is a chromium layer, is a silicon dioxide layer, is an intermediate insulating layer, is a plating base, is a resist layer, is a second layer thin film pattern, is a copper layer. In the figure, 11 is a glass ceramic or other insulating substrate (ceramic), 13 is a via metal, 31 is a thin film pattern of the first layer, Figure 3 is a diagram explaining the repeat exposure method, Figure 1 is a diagram explaining the principle of the present invention, and Figure 1 is a repeat coating. Fig. 4 is a cross-sectional view illustrating each step of the manufacturing method according to an embodiment of the present invention.

Claims (4)

[Claims] (1) In a method for manufacturing a multilayer board in which a multilayer conductor layer having a predetermined pattern is formed on an insulating substrate, a first conductor layer is formed in a position corresponding to a via provided in the insulating substrate. a step of digging down the formation portion; a step of embedding a first conductor layer in the conductor layer formation portion of the insulating substrate in the same plane as the surface of the insulating substrate; and a step of forming a via conductive to the lower conductor layer; a step of laminating an intermediate insulating layer having a conductor layer forming part in which the conductor layer is embedded; and a step of embedding the conductor layer in the via and the conductor layer forming part of the intermediate insulating layer in the same plane as the surface of the intermediate insulating layer. A method for manufacturing a multilayer board, comprising: (2) The method for manufacturing a multilayer substrate according to claim (1), wherein the intermediate insulating layer is formed using photosensitive polyimide by a repeat exposure method or a repeat coating method. (3) Claims that include the step of forming a silicon dioxide layer on the insulating substrate and the first conductor layer, and etching away the silicon dioxide layer in the conductive via of the intermediate insulating layer laminated thereon. The method for manufacturing a multilayer substrate according to item (1). (4) At the position corresponding to the via provided in the insulating substrate,
A conductive layer formed in the same plane as the surface of the insulating substrate, an intermediate insulating layer that has vias that conduct to the lower conductive layer, and is laminated, and an intermediate insulating layer at a position corresponding to the via in the intermediate insulating layer. A multilayer board comprising a conductor layer formed in the same plane as the surface of the board.