TWI708542B - Adhesive copper foil build-up process - Google Patents
Adhesive copper foil build-up process Download PDFInfo
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- TWI708542B TWI708542B TW108120940A TW108120940A TWI708542B TW I708542 B TWI708542 B TW I708542B TW 108120940 A TW108120940 A TW 108120940A TW 108120940 A TW108120940 A TW 108120940A TW I708542 B TWI708542 B TW I708542B
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Abstract
Description
本發明是關於一種電路板技術,特別是關於一種電路板的增層技術。The invention relates to a circuit board technology, in particular to a layer build-up technology of a circuit board.
隨著電子產品的普及,電路基板的應用越來越廣,由於電路設計趨向複雜化、多層化,因此以往是利用多個單面或雙面形成有銅箔的聚丙烯板彼此壓合進行增層,然而,現有技術的板對板壓合增層方式不易製作,而且成本較高,有待改良。With the popularization of electronic products, the application of circuit substrates has become more and more extensive. As circuit design tends to become more complicated and multilayered, in the past, multiple polypropylene plates with copper foil formed on one or both sides were pressed together to increase However, the prior art board-to-board laminating method is not easy to produce, and the cost is relatively high, which needs to be improved.
有鑑於此,本發明之主要目的在於提供一種改用貼膜方式進行增層的製程。In view of this, the main purpose of the present invention is to provide a process for adding layers by changing to a filming method.
為了達成上述及其他目的,本發明提供一種背膠銅箔增層製程,其包括: (1)提供一基底電路板,基底電路板具有一增層面,增層面具有一第一電路層; (2)通過真空壓膜方式將一原呈收捲狀的背膠銅箔貼附於增層面,背膠銅箔具有一銅箔層及一絕緣膠層,絕緣膠層塗布於銅箔層上,且第一電路層接觸絕緣膠層但不接觸銅箔層; (3)在銅箔層上電鍍一電鍍銅層;以及 (4)將銅箔層及電鍍銅層圖形化為一第二電路層。 In order to achieve the above and other objectives, the present invention provides a back-adhesive copper foil build-up process, which includes: (1) Provide a base circuit board, the base circuit board has an augmented layer, and the augmented layer has a first circuit layer; (2) Adhesive-backed copper foil is attached to the build-up layer by vacuum lamination. The back-adhesive copper foil has a copper foil layer and an insulating adhesive layer, and the insulating adhesive layer is coated on the copper foil layer. , And the first circuit layer contacts the insulating adhesive layer but not the copper foil layer; (3) Electroplating an electroplated copper layer on the copper foil layer; and (4) The copper foil layer and the electroplated copper layer are patterned into a second circuit layer.
本發明通過將銅箔層及絕緣膠層預先成膜收捲,而後再利用真空壓膜方式將原呈收捲狀的背膠銅箔貼附於增層面進行增層,可以大幅提昇增層效率,簡化增層製程,解決以往以板對板進行壓合增層的問題。In the present invention, the copper foil layer and the insulating adhesive layer are preliminarily formed into a film and reeled, and then the reeled copper foil is attached to the build-up layer by vacuum lamination method, which can greatly improve the efficiency of the build-up. , Simplify the build-up process and solve the problem of the previous board-to-board laminating build-up.
本發明揭示一種背膠銅箔增層製程,其可用於電路板的增層作業,解決以往以板對板進行壓合增層的問題。The invention discloses a layer build-up process of a back-adhesive copper foil, which can be used for the build-up operation of a circuit board, and solves the problem of the previous board-to-board laminating buildup.
以下通過第1、2、5至8圖說明本發明其中一實施例的製程。Hereinafter, the manufacturing process of one embodiment of the present invention will be described with reference to Figures 1, 2, 5 to 8.
首先,如第1圖所示,提供一基底電路板10,該基底電路板10具有二增層面11A、11B,增層面11A、11B分別具有一第一電路層12A、12B。此外,基底電路板10還具有一連通孔13,連通孔13內有孔銅14以電性連接兩第一電路層12A、12B。First, as shown in Figure 1, a
接著,如第2、3圖所示,利用真空壓膜整平機以真空壓膜方式依序將二原呈收捲狀的背膠銅箔20貼附於分別增層面11A、11B,請進一步參考第4圖,背膠銅箔20具有一銅箔層21及一絕緣膠層22,絕緣膠層22塗布於銅箔層21上,且第一電路層12A、12B接觸絕緣膠層22但不接觸銅箔層21。當背膠銅箔20貼附前,還可進一步包括一保護膜23貼附於絕緣膠層22相反於銅箔層21的一面,用以避免絕緣膠層22污損或沾黏。如第3圖所示,保護膜23在背膠銅箔20貼附於增層面11A、11B之前被移除,且當背膠銅箔20貼附於增層面11A、11B後,絕緣膠層22可包括但不限於熱固化的方式被完全固化,藉此與增層面11A、11B形成永久性連接。Then, as shown in Figures 2 and 3, use a vacuum lamination leveler to sequentially attach the two original rolled back
如第5圖所示,為了使不同層的電路形成電性連接,可以形成一貫穿兩背膠銅箔20及基底電路板10的連通孔30,而後如第6圖所示,在連通孔30內形成孔銅31而使兩銅箔層21分別與兩第一電路層12A、12B電性連接。在其他可能的實施方式中,如果不需要讓不同層的電路形成電性連接,則第5、6圖所示的步驟可以省略。As shown in Figure 5, in order to electrically connect circuits of different layers, a
如第7圖所示,在兩銅箔層21分別電鍍一電鍍銅層24,而後如第8圖所示,分別將兩組銅箔層21及電鍍銅層24圖形化為二第二電路層25,圖形化電路的方式可選擇常規的貼附光刻膜、曝光、顯影、鹼性蝕刻、移除光刻膜的方式實現。As shown in Figure 7, the two
前述實施例中,基底電路板為一雙層板,但在其他可能的實施例中,基底電路板也可以是單層板或其他多層板,例如,可以將第8圖所示的結構作為基底電路板,再一次進行本發明的背膠銅箔增層製程。In the foregoing embodiments, the base circuit board is a double-layer board, but in other possible embodiments, the base circuit board can also be a single-layer board or other multilayer boards. For example, the structure shown in Figure 8 can be used as the base For the circuit board, the back-adhesive copper foil build-up process of the present invention is performed again.
前述實施例中,背膠銅箔增層製程是在雙層板的兩面同步進行,但在其他可能的實施方式中,背膠銅箔增層製程可以只在基底電路板的一側單獨進行。In the foregoing embodiment, the adhesive-backed copper foil build-up process is performed simultaneously on both sides of the double-layer board. However, in other possible embodiments, the back-adhesive copper foil build-up process can be performed solely on one side of the base circuit board.
10:基底電路板
11A、11B:增層面
12A、12B:第一電路層
3:連通孔1
14:孔銅
20:背膠銅箔
21:銅箔層
22:絕緣膠層
23:保護膜
24:電鍍銅層
25:第二電路層
30:連通孔
31:孔銅10:
第1、2、5至8圖為本發明其中一實施例的背膠銅箔增層製程的步驟示意圖。Figures 1, 2, 5 to 8 are schematic diagrams of the steps of the build-up process of back adhesive copper foil according to one embodiment of the present invention.
第3圖為背膠銅箔的剖面示意圖。Figure 3 is a schematic cross-sectional view of the back adhesive copper foil.
第4圖為真空壓膜的製程設備示意圖。Figure 4 is a schematic diagram of the vacuum lamination process equipment.
21:銅箔層 21: Copper foil layer
24:電鍍銅層 24: Electroplated copper layer
25:第二電路層 25: second circuit layer
Claims (5)
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Cited By (1)
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CN113382544A (en) * | 2021-05-27 | 2021-09-10 | 中国科学院微电子研究所 | Method for plugging inner-layer substrate through hole by using ABF build-up membrane |
Citations (2)
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CN100493302C (en) * | 2004-07-14 | 2009-05-27 | 燿华电子股份有限公司 | Manufacturing method of modular circuit board |
TW201640977A (en) * | 2015-05-15 | 2016-11-16 | Microcosm Technology Co Ltd | Build-up multilayer laminate |
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN100493302C (en) * | 2004-07-14 | 2009-05-27 | 燿华电子股份有限公司 | Manufacturing method of modular circuit board |
TW201640977A (en) * | 2015-05-15 | 2016-11-16 | Microcosm Technology Co Ltd | Build-up multilayer laminate |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113382544A (en) * | 2021-05-27 | 2021-09-10 | 中国科学院微电子研究所 | Method for plugging inner-layer substrate through hole by using ABF build-up membrane |
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