JP2849163B2 - Manufacturing method of electronic circuit board - Google Patents

Manufacturing method of electronic circuit board

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Publication number
JP2849163B2
JP2849163B2 JP14501790A JP14501790A JP2849163B2 JP 2849163 B2 JP2849163 B2 JP 2849163B2 JP 14501790 A JP14501790 A JP 14501790A JP 14501790 A JP14501790 A JP 14501790A JP 2849163 B2 JP2849163 B2 JP 2849163B2
Authority
JP
Japan
Prior art keywords
plating
plating layer
circuit board
solder
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP14501790A
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Japanese (ja)
Other versions
JPH0437187A (en
Inventor
信人 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
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Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP14501790A priority Critical patent/JP2849163B2/en
Publication of JPH0437187A publication Critical patent/JPH0437187A/en
Application granted granted Critical
Publication of JP2849163B2 publication Critical patent/JP2849163B2/en
Anticipated expiration legal-status Critical
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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は,高密度でファインな回路パターンを有する
電子回路基板の製造方法に関する。
Description: TECHNICAL FIELD The present invention relates to a method of manufacturing an electronic circuit board having a high-density and fine circuit pattern.

〔従来技術〕(Prior art)

近年,電子回路基板は,ファイン化の傾向が顕著とな
り,所定面積の基板上に出来る限り多くのパターン,ス
ルーホールを形成しなければならない。
2. Description of the Related Art In recent years, the tendency of finer electronic circuit boards has become remarkable, and it is necessary to form as many patterns and through holes as possible on a board having a predetermined area.

上記電子回路基板は,一般に半田剥離法により,製造
されている(実施例参照)。
The electronic circuit board is generally manufactured by a solder peeling method (see Examples).

ところで,パターンの間隔を小さくするには,めっき
層の厚さを出来る限り薄くすることが有効な手段の一つ
となる。例えば,パターン間隔が100μm以下の高密度
でファインな電子回路基板の製造方法において,無電解
Niめっき層の厚さを2μm程度にすれば,ブリッジ80の
発生(第14図及び第15図)を回避することが知られてい
る。ここで,ブリッジ80とは,隣接するパターン8,8の
基部相互間において,その端部が無電解ニッケルめっき
又は金めっき工程時に生ずる現象をいう。このブリッジ
80により,パターン8,8間は短絡し,絶縁不良となる。
Incidentally, in order to reduce the interval between the patterns, it is one of effective means to make the thickness of the plating layer as small as possible. For example, in a method for manufacturing a high-density and fine electronic circuit board with a pattern interval of 100 μm or less, an electroless
It is known that the generation of the bridge 80 (FIGS. 14 and 15) can be avoided by setting the thickness of the Ni plating layer to about 2 μm. Here, the bridge 80 refers to a phenomenon that occurs between the bases of the adjacent patterns 8, 8 at the end thereof during the electroless nickel plating or gold plating process. This bridge
Due to 80, the patterns 8 and 8 are short-circuited, resulting in insulation failure.

即ち,銅箔81の上に形成された銅めっき層82には,そ
の上に更にNiめっき層83及びAuめっき層84のNi−Auめっ
き層等のパターンめっき層が形成される。このとき,該
Niめっき層83の膜厚が厚くなるに伴い,上記ブリッジ80
が起こり易くなる。
That is, on the copper plating layer 82 formed on the copper foil 81, a pattern plating layer such as a Ni-Au plating layer of the Ni plating layer 83 and the Au plating layer 84 is further formed thereon. At this time,
As the thickness of the Ni plating layer 83 increases, the bridge 80
Is more likely to occur.

反面,該Niめっき層83の厚さが,例えば2μm以下と
薄くなると,上記ブリッジ80は起こらなくなることが知
られている。
On the other hand, it is known that the bridge 80 does not occur when the thickness of the Ni plating layer 83 is reduced to, for example, 2 μm or less.

〔解決しようとする課題〕[Problem to be solved]

しかしながら,上記従来技術には,次の問題点があ
る。
However, the above prior art has the following problems.

即ち,上記高密度でファインなパターンは,一定以上
の膜厚を必要とする場合がある。例えば,半導体又は発
光ダイオード(LED)とのワイヤボンディングにより電
気的に接続するパターン8又は端子,導体ランド85及び
これに連結するスルーホール90の内壁86である。これら
においては,ワイヤーボンディングに耐える強度,つま
りワイヤーボンディング耐久性が要求される。そのた
め,上記Niめっき層83の膜厚は,例えば5μm程度が最
低必要である。したがって,例えば無電解めっき法によ
るパターン8,LED端子等の形成に当っては,第14図及び
第15図に示すごとく,ブリッジ80を生じ易い。
That is, the high-density and fine pattern may require a certain thickness or more. For example, a pattern 8 or a terminal electrically connected to a semiconductor or a light emitting diode (LED) by wire bonding, a conductor land 85, and an inner wall 86 of a through hole 90 connected thereto. In these, strength that can withstand wire bonding, that is, wire bonding durability is required. Therefore, the minimum thickness of the Ni plating layer 83 is, for example, about 5 μm. Therefore, for example, in forming the pattern 8, the LED terminal, and the like by the electroless plating method, the bridge 80 is easily generated as shown in FIGS.

本発明は,かかる従来の問題点に鑑みてなされたもの
で,金属めっき時にブリッジを生じない,高密度でファ
インな回路パターンを有する電子回路基板の製造方法を
提供しようとするものである。
The present invention has been made in view of such conventional problems, and an object of the present invention is to provide a method of manufacturing an electronic circuit board having a high-density and fine circuit pattern, which does not generate a bridge during metal plating.

〔課題の解決手段〕[Solutions to solve the problem]

本発明は,絶縁回路基板上の回路パターンを形成する
に当たり,絶縁回路基板上に半田を用いたパターンめっ
きを行い,その後エッチング,半田剥離,金属めっきを
行う電子回路基板の製造方法において,上記エッチング
の後に絶縁回路基板の全面に樹脂を塗布し,硬化し,そ
の後該樹脂層の表面を除去して上記半田を露出させ,そ
の後上記半田剥離を行うことを特徴とする電子回路基板
の製造方法にある。
The present invention relates to a method for manufacturing an electronic circuit board, which comprises forming a circuit pattern on an insulated circuit board by performing pattern plating using solder on the insulated circuit board, and thereafter performing etching, solder peeling, and metal plating. A resin is applied to the entire surface of the insulated circuit board, cured, and then the surface of the resin layer is removed to expose the solder, and then the solder is peeled off. is there.

本発明において,最も注目すべきことは,上記エッチ
ングの後に絶縁回路基板の全面に樹脂を塗布し,硬化
し,その後に該樹脂層の表面を除去して上記半田を露出
させ,その後上記半田剥離を行うことにある。
In the present invention, the most remarkable thing is that after the above-mentioned etching, a resin is applied to the entire surface of the insulated circuit board, cured, and then the surface of the resin layer is removed to expose the above-mentioned solder, and then the above-mentioned solder peeling Is to do.

上記回路パターンは,例えば無電解めっきにより,一
定の膜厚のCu又はNiめっき層を形成する。
The above-mentioned circuit pattern forms a Cu or Ni plating layer of a certain thickness by, for example, electroless plating.

また,上記樹脂層を形成するに当たっては,例えば半
田を用いたパターンめっき部を含む絶縁回路基板全面
に,スプレー塗布方法,ロールコーター塗布方法,印刷
法等により,所望の厚さの樹脂膜を形成する。また,該
樹脂膜を硬化するに当たっては,例えば露光,電子線照
射,熱風乾燥等を用いる。また,樹脂としては,例えば
エポキシ樹脂,ポリイミド樹脂を用いる。
In forming the resin layer, a resin film having a desired thickness is formed on the entire surface of the insulated circuit board including the pattern plating portion using solder by a spray coating method, a roll coater coating method, a printing method, or the like. I do. In curing the resin film, for example, exposure, electron beam irradiation, hot-air drying, or the like is used. As the resin, for example, an epoxy resin or a polyimide resin is used.

また,樹脂層の表面を除去する方法としては,例えば
サンドペーバーを用いる研磨加工,樹脂塗布面を磨くポ
リッシャ加工,グリット(小粒子)を樹脂塗布面に投射
するショットブラスト加工法がある。
As a method of removing the surface of the resin layer, for example, there are a polishing process using a sand paver, a polisher process for polishing a resin applied surface, and a shot blasting method for projecting grit (small particles) onto the resin applied surface.

また,上記半田剥離法としては,上記パターンめっき
の表面に形成した半田層を,半田剥離液(酸液)を用い
て除去する方法がある。
Further, as the solder stripping method, there is a method of removing a solder layer formed on the surface of the pattern plating using a solder stripping solution (acid solution).

〔作用及び効果〕[Action and effect]

本発明においては,先ず絶縁回路基板上に無電解銅メ
ッキにより,回路パターンを形成する。次に,該回路パ
ターン以外の部分に,めっきレジスト膜を被覆する。次
いで,該回路パターン部分に,電解銅めっきを行う。そ
して,該回路パターンの表面に半田を電解半田めっきに
より,被覆しパターンめっきを行う。その理由は,該パ
ターンめっき層を形成した以降にエッチングを行い,不
要な銅張り部分を除去する必要があるからである。
In the present invention, first, a circuit pattern is formed on an insulated circuit board by electroless copper plating. Next, a portion other than the circuit pattern is coated with a plating resist film. Next, electrolytic copper plating is performed on the circuit pattern portion. Then, the surface of the circuit pattern is coated with solder by electrolytic solder plating and pattern plating is performed. The reason is that it is necessary to perform etching after the formation of the pattern plating layer to remove unnecessary copper-clad portions.

また,上記金属めっきとしては,上記半田剥離した後
のパターンめっき層の表面に,更に無電解めっきにより
Ni−Auめっき層を形成する。
In addition, as the metal plating, the surface of the pattern plating layer after the above-mentioned solder peeling is further subjected to electroless plating.
A Ni-Au plating layer is formed.

また,上記Ni−Auめっき層は,上記Niめっき層の上に
形成したAuめっき層を有する。そのため,耐久性,導電
性,ワイヤーボンディング性に優れる。
The Ni-Au plating layer has an Au plating layer formed on the Ni plating layer. Therefore, it has excellent durability, conductivity, and wire bonding properties.

また,上記Niめっき層は,樹脂層を隔てて形成するた
め,回路パターン間にブリッジを生ずることがない。そ
の理由は,上記樹脂層によって形成された凹部に,上記
Niめっき層を形成することになるからである。
Further, since the Ni plating layer is formed with the resin layer separated, no bridge is generated between circuit patterns. The reason is that the recess formed by the resin layer
This is because a Ni plating layer will be formed.

したがって,本製造方法によれば,金属めっき時にブ
リッジを生じない,高密度でファインな回路パターンを
有する電子回路基板を容易に製造することができる。
Therefore, according to the present manufacturing method, it is possible to easily manufacture an electronic circuit board having a high-density and fine circuit pattern without causing a bridge at the time of metal plating.

〔実施例〕〔Example〕

第1実施例 本発明の実施例にかかる電子回路基板の製造方法につ
き,第1図〜第13図を用いて説明する。
First Embodiment A method of manufacturing an electronic circuit board according to an embodiment of the present invention will be described with reference to FIGS.

本例の製造方法は,第2図〜第6図に示すごとく,半
田剥離法により絶縁回路基板9上に電解半田めっき層16
を用いたパターンめっきを行う。その後,第7図及び第
8図に示すごとく,剥離,エッチングを行い,更に第11
図〜第13図に示すごとく,半田剥離,Ni−Au等の金属め
っきを行うものである。
As shown in FIG. 2 to FIG. 6, the manufacturing method of the present embodiment employs an electrolytic solder plating layer 16 on the insulating circuit board 9 by a solder peeling method.
Is performed by using the pattern plating. Thereafter, as shown in FIGS. 7 and 8, peeling and etching are performed.
As shown in FIG. 13 to FIG. 13, solder plating and metal plating such as Ni-Au are performed.

また,上記エッチングの後に,第9図及び第10図に示
すごとく,上記絶縁回路基板9の全面に樹脂層4を塗
布,硬化し,その後該樹脂層4の表面を除去して上記電
解半田めっき層16を露出させ,その後上記半田剥離を行
うものである。
After the etching, as shown in FIGS. 9 and 10, a resin layer 4 is applied to the entire surface of the insulated circuit board 9 and cured, and then the surface of the resin layer 4 is removed and the electrolytic solder plating is performed. The layer 16 is exposed, and then the above-mentioned solder peeling is performed.

本例によって得られる電子回路基板は,第1図に模式
的に示すごとく,基板9上に回路パターン1を形成した
ものである。ここで,上記回路パターン1は,銅箔11
と,その上に順次形成された化学銅めっき層12と,電解
Cuめっき層13(膜厚が約10μm)と,無電解Niめっき層
14(膜厚が約5μm)と,Auめっき層15(膜厚が約0.5μ
m)とよりなる。
The electronic circuit board obtained in this example is one in which a circuit pattern 1 is formed on a substrate 9 as schematically shown in FIG. Here, the circuit pattern 1 is a copper foil 11
And a chemical copper plating layer 12 sequentially formed thereon,
Cu plating layer 13 (about 10μm thick) and electroless Ni plating layer
14 (thickness of about 5 μm) and Au plating layer 15 (thickness of about 0.5 μm)
m).

次に,電子回路基板の製造方法につき,第1図〜第13
図を用いて説明する。
Next, a method of manufacturing an electronic circuit board will be described with reference to FIGS.
This will be described with reference to the drawings.

まず,第1工程においては,第2図に示すごとく,銅
箔11張りガラスエポキシ基板9の表面に,塩酸系パラジ
ウム溶液を用いて活性化処理10を行う。
First, in the first step, as shown in FIG. 2, an activation process 10 is performed on the surface of the glass epoxy substrate 9 covered with the copper foil 11 using a hydrochloric acid-based palladium solution.

次に,第2工程においては,第3図に示すごとく,上
記銅箔11の上に無電解銅めっきにより,化学銅めっき層
12を形成する。また,第3工程においては,第4図に示
すごとく,スクリーン印刷によりめっきレジスト17を形
成し,露光現像する。
Next, in the second step, as shown in FIG. 3, a chemical copper plating layer is formed on the copper foil 11 by electroless copper plating.
Form 12. In the third step, as shown in FIG. 4, a plating resist 17 is formed by screen printing, and is exposed and developed.

次いで,第4工程においては,電解Cuめっきにより,
上記めっきレジスト17により覆われない化学銅めっき層
12の上に,第5図に示すごとく,電解Cuめっき層13(膜
厚10μm)を形成する。
Next, in the fourth step, by electrolytic Cu plating,
Chemical copper plating layer not covered by the plating resist 17
As shown in FIG. 5, an electrolytic Cu plating layer 13 (thickness: 10 μm) is formed on the surface of the substrate.

そして,第5工程においては,第6図に示すごとく,
上記電解Cuめっき層13上に,電解半田めっき膜16を被覆
する。更に,第7図に示すごとく,上記めっきレジスト
17を剥離する。
In the fifth step, as shown in FIG.
An electrolytic solder plating film 16 is coated on the electrolytic Cu plating layer 13. Further, as shown in FIG.
17 is peeled off.

次に,エッチング工程においては,第8図に示すごと
く,上記電解Cuめっき層13上に形成した電解半田めっき
膜16以外の部分をエッチング除去する。
Next, in the etching step, as shown in FIG. 8, portions other than the electrolytic solder plating film 16 formed on the electrolytic Cu plating layer 13 are removed by etching.

上記電解半田めっき膜16は,後述するごとく,膜厚さ
を10〜15μmにする。
The electrolytic solder plating film 16 has a thickness of 10 to 15 μm as described later.

その後,第9図に示すごとく,絶縁回路基板9に,樹
脂4を塗布する。即ち,上記絶縁回路基板9の回路パタ
ーン1上に電解半田めっき層16も覆われるように,樹脂
4を塗布し,硬化する。該樹脂4は,エポキシ樹脂を用
いる。そして,該樹脂4の硬化は,加熱硬化により行
う。
Thereafter, as shown in FIG. 9, the resin 4 is applied to the insulating circuit board 9. That is, the resin 4 is applied and cured so that the electrolytic solder plating layer 16 is also covered on the circuit pattern 1 of the insulating circuit board 9. The resin 4 uses an epoxy resin. The resin 4 is cured by heating.

次に,第10及び11図に示すごとく,樹脂層の表面をベ
ルトサンダーのごとき研磨機(図示略)により除去し,
電解半田めっき層16を露出させる。即ち,まず樹脂層4
が電解半田めっき膜16と同一面になるまで研磨し(第10
図),次いで,電解半田めっき層16を酸液により除去す
る(第11図)。
Next, as shown in FIGS. 10 and 11, the surface of the resin layer was removed by a grinder (not shown) such as a belt sander.
The electrolytic solder plating layer 16 is exposed. That is, first, the resin layer 4
Until it is flush with the electrolytic solder plating film 16 (10th
Next, the electrolytic solder plating layer 16 is removed with an acid solution (FIG. 11).

そして,その表面に,第1図に示すごとく,ソルダー
レジスト膜5を被覆する。
Then, the surface is coated with a solder resist film 5 as shown in FIG.

その後,第1図及び第13図に示すごとく,電解めっき
により,Ni−Auめっきを行う。
Thereafter, as shown in FIGS. 1 and 13, Ni-Au plating is performed by electrolytic plating.

即ち,上記電解半田めっき層16を剥離した部分に,第
13図に示すごとく,まずNiめっき層14を無電解めっきに
より形成する。次に,第1図に示すごとく,その上にAu
めっき層15を,同じく無電解めっきにより,形成する。
これにより,回路パターン1,1を有する電子回路基板を
得る。
That is, the portion where the electrolytic solder plating layer 16 has been peeled off is
As shown in FIG. 13, first, a Ni plating layer 14 is formed by electroless plating. Next, as shown in FIG.
The plating layer 15 is also formed by electroless plating.
Thus, an electronic circuit board having the circuit patterns 1 and 1 is obtained.

次に,効果につき説明する。 Next, the effects will be described.

本例においては,上記Niめっき層14及びAuめっき層15
の形成に当たり,第9図〜第13図に示すごとく,上記回
路パターン1と回路パターン1の間に,該回路パターン
1の膜厚さよりも厚い樹脂層4を形成している。そのた
め,膜厚が5〜7μmのNiめっき層14及び膜厚が0.5〜
1.0μmと比較的厚いAuめっき層15を形成することがで
きる。このとき回路パターン1相互間には,樹脂層4が
形成されているため,Ni,Auめっき時に,回路パターン1,
1相互間にブリッジを生じることがない。
In this example, the Ni plating layer 14 and the Au plating layer 15
In forming this, a resin layer 4 thicker than the circuit pattern 1 is formed between the circuit patterns 1 as shown in FIGS. 9 to 13. Therefore, the Ni plating layer 14 having a thickness of 5 to 7 μm and the thickness of 0.5 to
The Au plating layer 15 having a relatively large thickness of 1.0 μm can be formed. At this time, since the resin layer 4 is formed between the circuit patterns 1, the circuit patterns 1 and
1 No bridges are created between each other.

したがって,本製造方法によれば,Ni−Auめっき層の
金属めっき時に,回路パターン間1,1にブリッジを生じ
ない,高密度でファインな電子回路基板を容易に製造す
ることができる。
Therefore, according to the present manufacturing method, it is possible to easily manufacture a high-density and fine electronic circuit board which does not generate a bridge between the circuit patterns 1 and 1 at the time of metal plating of the Ni-Au plating layer.

なお,上記においては,回路パターン1の相互間隔は
50〜60μmとしたが,この範囲であればいずれの場合
も,ブリッジを生ずることがなかった。
In the above, the mutual interval between the circuit patterns 1 is
Although it was 50 to 60 μm, no bridge was formed in any case within this range.

また,上記半田めっき2の膜の厚みを10〜15μmと
し,上記Niめっき層14の膜厚さを5〜7μm,またAuめっ
き層15の膜厚さを0.5〜1.0μmとしたときにも,ブリッ
ジを生ずることがなかった。
Also, when the thickness of the solder plating 2 is 10 to 15 μm, the thickness of the Ni plating layer 14 is 5 to 7 μm, and the thickness of the Au plating layer 15 is 0.5 to 1.0 μm, No bridging occurred.

第2実施例 上記第1実施例の方法において,第1表に示すごと
く,各種基板を用い,電解半田めっき層の厚み,半田剥
離後のNiめっき層,Auめっき層の厚みを種々に変えて,
電子回路基板を作製した。
Second Embodiment In the method of the first embodiment, as shown in Table 1, various substrates were used, and the thickness of the electrolytic solder plating layer and the thickness of the Ni plating layer and the Au plating layer after the solder was peeled were variously changed. ,
An electronic circuit board was manufactured.

なお,上記基板において,化学銅めっき層12と電解Cu
めっき層の合計膜厚さは,いずれも10μmである。
In the above substrate, the chemical copper plating layer 12 and the electrolytic Cu
The total thickness of the plating layers is 10 μm.

第1表から明らかなごとく,Niめっき層とAuめっき層
との金属めっきの層の厚さは,剥離した半田層の膜厚さ
よりも薄く形成してある。しかし,Niめっき層,Auめっき
層の厚みは通常よりも厚くすることができる。また,パ
ターンのNi−Auめっき層間には,ブリッジは形成されて
いなかった。
As is clear from Table 1, the thickness of the metal plating layer of the Ni plating layer and the Au plating layer is formed smaller than the thickness of the peeled solder layer. However, the thickness of the Ni plating layer and Au plating layer can be made larger than usual. No bridge was formed between the Ni-Au plating layers of the pattern.

【図面の簡単な説明】[Brief description of the drawings]

第1図〜第13図は本発明の実施例を示し,第1図は本例
によって得られる電子回路基板の断面図,第2図〜第7
図はパターンめっき形成の工程概要図,第8図〜第13図
はブリッジのない金属めっき層を有する電子回路基板の
製造工程図,第14図及び第15図は従来例を示し,第14図
はプリント配線板の断面図,第15図はプリント配線板に
おける金属めっき層の断面図である。 1……回路パターン, 10……活性化処理, 11……銅箔, 12……化学銅めっき層, 13……電解Cuめっき層, 14……Niめっき層, 15……Auめっき層, 16……電解半田めっき層, 4……樹脂層, 5……ソルダーレジスト膜, 9……絶縁回路基板,
1 to 13 show an embodiment of the present invention, FIG. 1 is a cross-sectional view of an electronic circuit board obtained by this embodiment, and FIGS.
The figure is a schematic view of the process of pattern plating formation, FIGS. 8 to 13 show the manufacturing process of an electronic circuit board having a metal plating layer without a bridge, FIGS. 14 and 15 show a conventional example, and FIGS. Is a sectional view of a printed wiring board, and FIG. 15 is a sectional view of a metal plating layer in the printed wiring board. 1 ... circuit pattern, 10 ... activation treatment, 11 ... copper foil, 12 ... chemical copper plating layer, 13 ... electrolytic Cu plating layer, 14 ... Ni plating layer, 15 ... Au plating layer, 16 ... Electrolytic solder plating layer, 4 ... Resin layer, 5 ... Solder resist film, 9 ... Insulated circuit board,

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】絶縁回路基板上の回路パターンを形成する
に当たり,絶縁回路基板上に半田を用いたパターンめっ
きを行い,その後エッチング,半田剥離,金属めっきを
行う電子回路基板の製造方法において, 上記エッチングの後に絶縁回路基板の全面に樹脂を塗布
し,硬化し,その後該樹脂層の表面を除去して上記半田
を露出させ,その後上記半田剥離を行うことを特徴とす
る電子回路基板の製造方法。
1. A method of manufacturing an electronic circuit board, comprising: forming a circuit pattern on an insulated circuit board, performing pattern plating using solder on the insulated circuit board, and thereafter performing etching, solder peeling, and metal plating. A method of manufacturing an electronic circuit board, comprising applying a resin to the entire surface of an insulating circuit board after etching, curing the resin, removing the surface of the resin layer to expose the solder, and then performing the solder peeling. .
JP14501790A 1990-06-01 1990-06-01 Manufacturing method of electronic circuit board Expired - Lifetime JP2849163B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14501790A JP2849163B2 (en) 1990-06-01 1990-06-01 Manufacturing method of electronic circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14501790A JP2849163B2 (en) 1990-06-01 1990-06-01 Manufacturing method of electronic circuit board

Publications (2)

Publication Number Publication Date
JPH0437187A JPH0437187A (en) 1992-02-07
JP2849163B2 true JP2849163B2 (en) 1999-01-20

Family

ID=15375508

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14501790A Expired - Lifetime JP2849163B2 (en) 1990-06-01 1990-06-01 Manufacturing method of electronic circuit board

Country Status (1)

Country Link
JP (1) JP2849163B2 (en)

Also Published As

Publication number Publication date
JPH0437187A (en) 1992-02-07

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