JPH02234249A - Transfer data protection system - Google Patents

Abstract

PURPOSE:To prevent the destruction of the transfer data that is caused by the program runaway by protecting continuously the data stored in a main storage with the direct memory access DMA transfer of data carried out by a DMA access until the next memory writing operation is started by a program. CONSTITUTION:A DMA transfer system consists of a CPU 1, a main storage 2, an input/output controller 10, and an input/output device 11. The data stored in the storage 2 via the DMA transfer are protected at and after the end of the DMA transfer, and no writing operation is carried out to a memory block 3 storing the DMA transfer data unless a new data protection release signal is transmitted. As a result, the storage data are never destroyed despite the occurrence of the program runaway and the reliability and the efficiency are improved for a data processing system.

Description

[Detailed Description of the Invention] [Summary] Regarding a protection method for data transferred by direct memory access, data stored in the main storage device by data transfer by direct memory access is written to the next memory by a program. The purpose of this system is to provide a transfer data protection method that protects data until the start of the process. In a system that performs data transfer by memory access (hereinafter referred to as DMA transfer), when a DMA transfer from an input/output device to a main storage device is completed within a central processing unit, a DMA transfer completion signal is sent to the main storage device. DMA transfer completion signal sending means; data protection release signal sending means for sending a data protection release signal for releasing data protection when DMA transfer data is in a protected state in the main storage; each memory in the main storage; A block receives DMA from the central processing unit at the start of a DMA transfer.
DMA transfer storage means for receiving a transfer request signal and an address signal and storing information that a DMA transfer has been performed in a memory block selected by the address signal; and a DMA transfer is stored in the DMA transfer storage means. a data protection setting means for prohibiting writing to a memory section in the memory block when the DMA transfer completion signal is received from the central processing unit; data protection canceling means for erasing the storage information of the DMA transfer storage means and canceling the protection setting of the data protection setting means to cancel the prohibition of memory writing to the memory section; The configuration is such that the DMA transfer data is protected until the data protection release signal is sent out.

[Industrial Application Field] The present invention relates to a protection method for data transferred by direct memory access.

FIG. 3 is a diagram showing the configuration of the second direct memory access method.

In recent years, in systems such as data processing equipment or electronic exchanges that are composed of a central processing unit, main memory, input/output devices, etc., there is a direct connection between the main memory and input/output devices as shown in Figure 3. DMA transfer is often used to transfer data.

On the other hand, with conventional main memory devices that do not have a memory protection function, it is possible to write to the memory section of the main memory device without restriction based on instructions from the central processing unit. Even when an access is made, writing is performed and the stored data may be destroyed. This phenomenon occurs even when data transferred by DMA transfer is stored.

Although some important data is transferred from the input/output device 1, such as a hard disk device, to the main storage device by DMA transfer, such transferred data may also be destroyed due to program runaway.

If data is destroyed, system operation processing will be affected, so it is necessary to reread the data transferred by DMA transfer from the input/output device to the main storage device and restart the system. There were problems in terms of efficiency. Therefore, a method is required to protect data transferred by DMA transfer until the next write is performed by program processing.

[Conventional technology]

FIG. 4 is a block diagram of a conventional memory writing section.

In FIG. 4, 21 is a central processing unit, 22 is a main storage device, 2
3 is a memory block, 24 is a memory section within the memory block, 25 is an address signal line that sends a write destination address signal from the central processing unit to the main memory, and 26 is a memory write signal that also sends a memory write signal. line, 27
is the central processing unit 21 and other control devices and the main storage device 22
A data line that sends and receives data via a common bus between
8 is a decoder 29 which decodes the address signal in the main storage device 22, selects a memory block corresponding to the designated address, and sends a memory block selection signal to the selected memory block 23; 30 is a memory block selection signal line that sends the output information of the decoder 28 to the memory block 23;
This is an AND circuit provided within the block 23.

In FIG. 4, when a memory write is commanded by the central processing unit 21, first, an address signal is sent from the central processing unit 21 to the main memory 22 through the address signal line 25 to designate the address of the memory to be written to. . The decoder 28 receives and decodes the address signal to select a memory block to write to, for example, a memory block.
If block I is selected, the memory block 23
A memory block selection signal is sent to the memory block selection signal line 29 for the memory block selection signal line 29. Next, a memory write signal is sent from the central processing unit 21 through the memory write signal line 26, and this signal is sent to the AND circuit 30 in the memory block 23 together with the signal sent from the decoder 28 through the memory block selection signal line 29. is input. Therefore, the two inputs of the AND circuit 30 are both in a state where signals are input, and the output of the AND circuit 30 is sent to the memory section 24 as a memory write signal.
becomes ready to accept write data, and writes and stores the data sent through the data line 27.

In the case of DMA transfer from an input/output device, data is sent from the input/output device and input/output control device (not shown) to the data line 27 through the common bus, and the transferred data is stored in the memory section 24 as described above.

Even if an unauthorized memory write signal is sent from the central processing unit 21 due to a program runaway, etc., the memory write is performed as described above, so the data stored in the memory unit 24 will not be destroyed by the data written due to the runaway. The Rukoto. D when the system restarts after a runaway
Since the transfer data stored by MA transfer is used as correct data, if the transfer data is destroyed, the restart process becomes abnormal, resulting in a restart failure. For this reason,
This means that the DMA transfer must be performed again and the system restart process must be performed again.

[Problem to be solved by the invention]

As described above, in the conventional method, important data transferred by DMA transfer is not protected, so when a memory write signal is sent from the central processing unit due to a program runaway, the stored transferred data could be destroyed, resulting in failure to restart the system.

SUMMARY OF THE INVENTION An object of the present invention is to provide a transfer data protection method that protects data stored in a main storage device by DMA transfer until the start of the next memory write by a program.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention.

In the figure, 1 is a central processing unit, 2 is a main storage device, 3 is a memory block that is a storage unit of the main storage device 2 and also serves as a transfer unit in DMA transfer, and 4 is a memory block that stores data in the memory block 3. 5 is a means for sending a DMA transfer completion signal to the main storage device 2 when the DMA transfer is completed in the central processing unit 1; 6 is a means for the main storage device 2 to protect data in the central processing unit 1; means for sending a data protection release signal to cause the main storage device 2 to release the data protection when When memory block 3 is selected and a DMA transfer request signal is sent from the central processing unit 1, the DMA transfer request signal is sent to the memory block 3.
Means 8 is a data protection setting means for storing that MA transfer has been performed, and when a DMA transfer completion signal is sent from the central processing unit 1 while the DMA transfer storage means 7 is storing the DMA transfer. 9 is a data protection canceling unit which receives a data protection cancellation signal from the central processing unit 1 and deletes the information stored in the DMA transfer storage unit 7 and data means for canceling the protection setting in the protection setting means 8 to cancel the prohibition of writing to the memory unit 4;
1 is an input/output control device, and 11 is an input/output device including an auxiliary storage device such as a hard disk device.

[Effect]

In FIG. 1, when performing DMA transfer from the input/output device 11 to the main storage device 2, a DMA transfer request signal and an address signal are sent from the central processing unit 1 to the main storage device 2. When the main storage device 2 receives the address signal, it decodes it, selects a memory block in which to write the data transferred by DMA transfer, and outputs the data to the DMA transfer storage means 7 of the selected memory block 3. - Send a block selection signal. When the DMA transfer storage means 7 receives both the memory block selection signal and the DMA transfer request signal, the DMA transfer storage means 7 selects its own memory block 3.
It is stored that the DMA transfer was performed for the DMA transfer. DM
The stored information in the A-transfer storage means 7 is output to the data protection setting means 8, but the data protection setting means 8 does not operate with only the stored information. In this state, when a memory write signal is sent from the central processing unit 1, the memory write signal is sent to the memory section 4 through the data protection setting means 8, and the memory section 4 becomes in a state in which data can be written. Next, when DMA transfer data is sent from the input/output device 11 to the main storage device 2, the memory section 4 writes and stores it.

When the DMA transfer is completed, the central processing unit l receives a DMA transfer completion report from the input/output control unit 10, and sends a DMA transfer completion signal to the main storage device 2 from the DMA transfer completion signal sending means 5, and the DMA transfer completion signal is sent to the main storage device 2. The transfer completion signal is
It is input to the data protection setting means 8 of block 3. The data protection setting means 8 is configured to set data protection when signals are input to two input terminals at the same time.
Since it memorizes that the transfer has been performed and outputs the stored information to the data protection setting means 8, when the DMA transfer completion signal is input, the data protection setting means 8 sets data protection. .

In this state, even if a memory write signal is sent from the central processing unit l to the memory block 3, the memory unit 4
No write signal is sent to.

That is, memory writing to the memory unit 4 is prohibited, and the DMA transfer data already stored in the memory unit 4 is placed in a protected state that will not be destroyed by memory writing from now on.

When it becomes necessary for the central processing unit 1 to newly write to the memory block 3, the central processing unit 1 sends a data protection cancellation signal to the main storage device 2 from the data protection cancellation signal sending means 6. Send. When the data protection release means 9 of the memory block 3 of the main storage device 2 receives the data protection release signal, it sends a signal to the DMA transfer storage means 7 and the data protection setting means 8.
The stored information is erased, and the protection setting of the data protection setting means 8 is canceled. As a result, the data protection setting in the data protection setting means 8 is canceled, and when a memory write signal is sent from the central processing unit 1, the memory write signal passes through the data protection setting means 8 and is sent to the memory unit 4.
The data is sent to the memory unit 4, and the memory section 4 writes and stores the data that is then sent.

The data protection release signal is created to be sent by software means in combination with a regular program for memory writing. By using such means, it is possible to prevent a data protection release signal from being sent together with a memory write signal that occurs when a program runs out of control, so by combining it with data protection setting means using hardware means, DMA transfer Ensure your data is protected.
It will be done.

As described above, according to the present invention, data transferred by DMA transfer is protected until the central processing unit sends a data protection release signal, and even if a program goes out of control during this time, it will not be destroyed.

〔Example] FIG. 2 is a block diagram of an embodiment of the present invention.

In the figure, the same symbols as in Figure 1 are used, and 12 is DM.
14 is provided in the main storage device 2 and receives an address signal sent from the central processing unit 1, and selects a memory block to be written from the address information. decoder, 15
, 16.17 are AND circuits (AND., ANDt, AND2) in memory block 3, respectively.
, 18 and 19 are flip-flop circuits (FF
+. FFz).

When performing DMA transfer in FIG. 2, the central processing unit 1 sends an address signal specifying the address of the memory where the transfer data is to be stored. The content of the address signal is read by a decoder 14 in the main memory device 2, and a memory block to be written is selected. For example, when memory block (2) is selected, a memory block selection signal is sent as an output to output terminal I of the decoder. Memory block 3 in FIG. 2 shows the memory block 1, which is one of a plurality of memory blocks. The memory block selection signal operates the memory block 3 through the memory block selection signal line, and also operates the AND circuit 15 of the memory block 3.
is input to one input terminal of Further, a DMA transfer request signal is sent from the central processing unit 1 at the start of DMA transfer, and is input to the other input terminal of the same <AND circuit 15, so the AND circuit 15 sends out an output. The output is input to the S terminal of the flip-flop circuit 18, and the flip-flop circuit 18 is placed in a set state. The set state of the flip-flop circuit 18 is the memory block 3.
This is to store information that DMA transfer has been performed on the Q terminal, and the stored information is output from the Q terminal.

In this state, data is transferred by DMA transfer from the human output device (not shown) to the main storage device through the common bus, and is stored in the memory section 4 of the memory block 3. When the DMA transfer is completed, the input/output control device (not shown) reports the completion of the DMA transfer to the central processing unit 1, so the central processing unit 1 transmits the DMA transfer to the main storage device 2 from the DMA transfer completion signal sending unit 12. Sends a transfer completion signal. The DMA transfer completion signal is input to one input terminal of the AND circuit 16 of the memory block 3.

The output of the Q terminal of the flip-flop circuit l8 is input to the other input terminal of the AND circuit 16, but the flip-flop circuit l8 is in the set state as described above, and the output is not output to the Q terminal. Since it has been sent, applicable A
ND circuit l6 sends out an output signal. The output signal is input to the S terminal of the flip-flop circuit 19, and the flip-flop circuit 19 is set and the output signal is sent to the Q terminal. The output signal is further input to one input terminal of the AND circuit 17, and this input terminal is provided with a level inversion circuit to invert the level of the input signal.
AN when the flip-flop circuit 19 is in the set state
No signal is input from the input terminal of the D circuit 17. Therefore, in this state, even if a memory write signal from the central processing unit 1 is input to the other input terminal of the AND circuit 17, the write signal is not sent out from the AND circuit 17 to the memory section 4 as an output. That is, the setting of the flip-flop circuit 19 means that writing to the memory section 4 is prohibited, and the DMA stored in the memory section 4 is
Data transferred is protected.

Next, when it becomes necessary for the central processing unit 1 to write new data to the memory block 3 in which data is stored by DMA transfer, the central processing unit 1 writes the new data to the memory block 3 in which the data is stored by DMA transfer. and sends a data protection release signal to memory block 3. Since the data protection release signal is input to the R terminal which is the reset signal input terminal of the flip-flop circuits l8 and 19 of the memory block 3, the flip-flop circuits 18 and 19
Both circuits are reset. That is, the storage information of the DMA transfer is erased and the data protection setting is canceled. Therefore, when the memory write signal sent from the central processing unit 1 is input to the AND circuit 17, the AND circuit 1
7 sends a write signal to the memory section 4 as an output, and the memory section 4 becomes write-enabled and stores the data sent through the common bus. As a result, data previously stored by DMA transfer is lost.

The data protection release signal mentioned above is sent by software means in combination with a program that writes to memory.
If the program goes out of control, it will not be sent, and the DMA transfer data will be protected even if the program goes out of control. Therefore, when the central processing unit 1 performs restart processing, the DMA transfer data can be used as is.

〔Effect of the invention〕

As explained above, according to the present invention, data stored in the main storage device by DMA transfer is protected from the time the DMA transfer is completed, and the DMA transfer data is not stored unless a new data protection release signal is sent. Since no writing is performed to the stored memory block, stored data will not be destroyed even if the program runs out of control. Therefore, even if the stored DMA transfer data is used as is in system restart processing after a program runaway, there is little possibility that system restart will fail, which greatly contributes to improving the reliability and efficiency of such a processing system.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is a configuration diagram of an embodiment of the invention, FIG. 3 is a configuration diagram of a direct memory access system, and FIG. 4 is a configuration diagram of a conventional system. In the figure, 1 -・1～−---−・−・−・1・1 Central processing unit 2 −−−−−−−−−−−−−−1・1 Main storage device 3 ・・−・−・111・−・Memory block 4−−
−−−・−−−−−〜−・・−・Memory section 5 −−−
-------・----・-- DMA transfer completion signal sending means 6 --------- Data protection release signal sending means 7 --- DMA transfer storage means 8 --- ---Data protection setting means 9-----
−・・−・Data protection release means lO ・−・−・・−
・・・−・−・−・・Input/output control device 1 1 −−−
−−−−・・One person output device 12−・−・
・-・・-・-・DMA transfer completion signal sending unit 1 3--
---・-・−・−・−・1・− Data protection release signal sending unit 1 5 to 1 18. It is 1. --- Decoder --- AND circuit --- Flip Flow knob circuit Explanation of the principle of the present invention Direct memory access system structure Figure 5 Figure ρ Figure

Claims (1)

[Claims] Consisting of a central processing unit (1), a main storage device (2), an input/output control device (10), and an input/output device (11), direct communication between the main storage device and the input/output device is provided. In a system that performs data transfer by memory access, the central processing unit (1) includes a direct memory access controller (1) when data transfer from the input/output device (11) to the main storage device (2) by direct memory access is completed. Direct memory access transfer completion signal sending means (5) that sends an access transfer completion signal to the main storage device (2), and data transferred by direct memory access in the main storage device (2) is in a protected state. data protection release signal sending means (6) for sending a data protection release signal to release the data protection when the data protection is in the main storage device (2); Receives the direct memory access transfer request signal and address signal sent from the central processing unit (1) at the start of data transfer, and transfers data by direct memory access to the memory block (3) selected by the address signal. Direct memory access transfer storage means (7) stores information that data transfer has been performed, and direct memory access transfer storage means (7) stores information that data transfer has been performed by direct memory access. data protection setting means (8) for inhibiting writing to the memory section (4) in the memory block (3) when the direct memory access transfer completion signal is received from the central processing unit (1) while ), upon receiving a data protection cancellation signal from the central processing unit (1), erase the stored information in the direct memory access transfer storage means (7), and protect the data protection setting means (8); A data protection release means (9) is provided to release the setting and remove the prohibition of memory writing to the memory unit (4), and the central processing unit sends a data protection release signal upon completion of data transfer by direct memory access. A transfer data protection method is characterized in that data transferred by direct memory access is protected until then.