JPH056310A - Electronic device - Google Patents

Abstract

PURPOSE:To protect an operation program applied from the external and to prevent the program from being destructed. CONSTITUTION:The electronic device is provided with a RAM 42 for storing the operation program and a RAM 43 for storing other data. An output port 45 and a flip flop (FF) 46 both of which input a reset signal to clear terminals are connected so that the output of the output port 45 is supplied to the FF 46 as a clock. The input terminal of the FF 46 is fixed to an 'H' level. An AND gate 47 finds out AND between the output of the FF 46 and a write signal outputted from a CPU 41 and supplies its output to the RAM 42 as a write signal. The CPU 41 stores the operation program applied from a master device 1 in the RAM 42 at the ON of power, and at the time of completing the storage of the operation program, applies an 'H' level signal to the output port 45 to close the AND gate 47.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device which operates based on an operation program given by a main device.

[0002]

2. Description of the Related Art As one of systems consisting of a private branch exchange (PBX) and a multifunction telephone, there is a system in which the multifunction telephone operates based on an operation program given from the PBX.

FIG. 3 is a block diagram showing an example of the essential structure of such a system. In the figure, 1 is a main device such as a PBX, and 2 is a subordinate device such as a multifunction telephone. The slave device 2 includes a CPU 21, a communication control circuit 22, a RAM 23,
It has a ROM 24 and an address decoder 25.

The operation program of the slave device 2 is accommodated in the main device 1, and when the main device 1 and the slave device 2 are connected via the communication line 3, the main device 1 is connected via the communication line 3. The operation program is transmitted to the slave device 2. In the slave device 2, the communication control circuit 22 receives the operation program transmitted via the communication line 3, and the operation program is transmitted to the CPU 2
1 is stored in the RAM 23 based on the basic program stored in the ROM 24 in advance. When all the operation programs are stored in the RAM 23, the CPU 21 operates according to the operation programs stored in the RAM 23.

By the way, the RAM 23 is allocated a region as a register or the like for use when the CPU 21 operates, and various data is written in the RAM 23. Therefore, if the designated address is garbled in the storage area of the operation program due to malfunction of the CPU 21 or noise mixed in the address signal, the operation program will be destroyed.

[0006]

As described above, the prior art is as follows.
Since the operation program given from the outside and the other data are stored in the same RAM, there is a possibility that the operation program may be erroneously destroyed when the data is stored, and the operation may be disabled.

The present invention has been made in consideration of such circumstances, and an object thereof is to provide an electronic device capable of protecting an operation program given from the outside and preventing the operation program from being destroyed. is there.

[0008]

The present invention is provided by a first storage means for storing an operation program, a second storage means for storing data, and another device such as a main device. The operation program storage control means for storing the operation program in the first storage means, and all the operation programs given from the other device are stored in the first storage means by the operation program storage control means. And a capture end detecting means for detecting that all of the operating programs have been stored in the first storing means, and the subsequent storing means detects that all the operating programs have been stored in the first storing means. The writing of the above data is prohibited.

[0009]

By taking such means, the operation program given from the other device is stored in the first storage means by the operation program storage control means and is given from the other device by the capture end detecting means. In response to the fact that all of the operating programs stored in the operating program storage control means have been detected, the subsequent writing of data to the first storing means is prohibited. .. Therefore, no data is written to the first storage means after the operation program is stored.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a main configuration of a system configured by applying the electronic device according to the present embodiment. The same parts as those in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the figure, reference numeral 4 is a slave device to which the electronic device according to the present embodiment is applied. The slave device 4 includes a communication control circuit 22, a ROM 24, a bus 26, a CPU 41, and a RAM.
42, 43, address decoder 44, output port 45,
Flip-flop 46 and AND gate (negative logic) 4
It is configured to have 7.

Of these, the communication control circuit 22 and the ROM 2
4, the CPU 41, the RAMs 42, 43 are connected to each other via the bus 26. The RAM 42 corresponds to the first storage means and stores the operation program. The RAM 43 corresponds to the second storage means and stores various data. These RAM 42, 43 and ROM 24
Is alternatively selected by the data obtained by decoding the address signal (upper several bits) output from the CPU 41 with the address by the coder 44.

In the output port 45, the control signal output from the CPU 41 is input to the input terminal, and the reset signal which becomes "L" level when the power is turned on is input to the clear terminal. The output terminal is connected to the clock terminal of the flip-flop 46. Flip-flop 46
Has + 5V input to its input terminal and a reset signal input to its clear terminal. And the output terminal is AN
It is connected to one input terminal of the D gate 47. AN
The write signal output from the CPU 41 is input to the other input terminal of the D gate 47. The output terminal of the AND gate 47 is connected to the write signal input terminal of the RAM 42.

Next, the operation of the slave device 4 configured as described above will be described. First, when the slave device 4 is powered on, the reset signal becomes the “L” level, and the CPU 41,
The output port 45 and the flip-flop 46 are reset. When the output port 45 and the flip-flop 46 are reset, their outputs are both at "L" level.

After the reset, the CPU 41 performs the processing shown in FIG. 2 based on the basic program stored in the ROM 24. That is, first, in step a, the operation program output from the main device 1 and transmitted through the communication line 3 is loaded into the communication control circuit 2
2 to receive. Then, in step b, the CPU 41 stores the operation program received by the communication control circuit 22 in the RAM 42 for storing the operation program. That is, the basic program and CP stored in the ROM 24
The U41 constitutes an operation program storage control means.

Then, the CPU 41, in step c,
It is determined whether or not all reception and storage of the operation program given from the main device 1 have been completed, and the processes of step a and step b are repeated until completion. At this time, since the output of the flip-flop 46 is at the “L” level, the AND gate 47 is in the ON state, and the CPU 4
The write signal output from 1 can be supplied to the RAM 42, and the RAM 42 is in a writable state.

When the loading of all the operation programs is completed, the CPU 41 shifts the processing from step c to step d. In step d, the CPU 41 outputs the output port 4
The control signal for 5 is set to "H" level. Then, the output of the output port 45 changes from the "L" level to the "H" level. Therefore, the AND gate 47 is turned off, and the write signal output from the CPU 41 is cut off and not supplied to the RAM 42. Therefore, the RAM 42 is in a write-protected state. That is, the output port 45,
The flip-flop 46 and the AND gate 47 constitute a write-inhibiting means, and the basic program stored in the ROM 24 and the CPU 41 constitute an intake end detecting means.

After this, the CPU 41 executes the processing in step e.
Then, the operation is performed based on the operation program stored in the RAM 42. The CPU 41 stores in the RAM 43 the data to be handled during the operation based on this operation program.

As described above, according to this embodiment, when the data is stored in the RAM 43, even if the address is garbled to the address of the RAM 42 due to the malfunction of the CPU 41 or the mixing of noise, the write signal is sent to the RAM 42. Is not supplied, the data is not written in the RAM 42 and the operation program stored in the RAM 42 is protected. The present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the present invention.

[0020]

According to the present invention, the first storage means for storing the operation program, the second storage means for storing the data, and the operation given from another device such as the main device. An operation program storage control means for storing a program in the first storage means, and a detection that all the operation programs given from the other device are stored in the first storage means by the operation program storage control means Capturing end detecting means for storing data of all the operating programs stored in the first storing means, and subsequently storing data to the first storing means. Since the writing is prohibited, the electronic device can protect the operating program given from the outside and prevent the operating program from being destroyed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main configuration of a system configured by applying an electronic device according to an embodiment of the invention.

FIG. 2 is a flowchart showing a processing procedure of a CPU 41 in FIG.

FIG. 3 is a diagram illustrating a conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Main device, 3 ... Communication line, 4 ... Slave device, 22 ... Communication control circuit, 24 ... ROM, 26 ... Bus, 41 ... CPU, 4
2 ... RAM (for storing operation programs), 43 ... RAM
(For storing data), 44 ... Address decoder, 45 ... Output port, 46 ... Flip-flop, 47 ... AND gate (negative logic).

Claims (1)

Claim: What is claimed is: 1. It is necessary to receive an operation program given from another device at a predetermined time point, and thereafter operate based on this operation program, and store and hold various data during operation. In another electronic device, the first storage means for storing the operation program, the second storage means for storing the data, and the operation program given from the other device are the first storage means. An operation program storage control means for storing the operation program, an end-of-acquisition detection means for detecting that all the operation programs given from the other device are stored in the first storage means by the operation program storage control means, In response to the fact that all the operation programs are stored in the first storage means by the capture end detection means, Electronic apparatus characterized by comprising a write inhibiting means for inhibiting the kick writing data in the first storage means.