JPH02230773A - Thin film transistor element array - Google Patents
Thin film transistor element arrayInfo
- Publication number
- JPH02230773A JPH02230773A JP4992589A JP4992589A JPH02230773A JP H02230773 A JPH02230773 A JP H02230773A JP 4992589 A JP4992589 A JP 4992589A JP 4992589 A JP4992589 A JP 4992589A JP H02230773 A JPH02230773 A JP H02230773A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- element array
- insulating film
- film transistor
- gate insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 27
- 239000010408 film Substances 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 239000011521 glass Substances 0.000 abstract description 9
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 6
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052804 chromium Inorganic materials 0.000 abstract description 5
- 239000011651 chromium Substances 0.000 abstract description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 abstract description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 4
- 239000000463 material Substances 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 2
- 229910021529 ammonia Inorganic materials 0.000 abstract description 2
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910000077 silane Inorganic materials 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract 1
- 238000001182 laser chemical vapour deposition Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000010985 leather Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は薄膜トランジスタ素子アレイに関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor element array.
[従来の技術およびその課題1
液晶ディスプレイの画素駆動等に用いられる薄膜トラン
ジスタ素子アレイは、基板上に多数個の薄膜トランジス
タを一括形成することが要求される。従来このような薄
膜トランジスタ素子アレイは、砂田により、1985年
,プロシーディング・オブ・インターナショナル・ディ
スプレイ・リサーチ−]ンファレンス( Procee
ding of Iritel’rla−tional
Display Research Confere
nce) , 66真に報告ざれているように、例えば
順スタガ構造の場合、基板上に必要な数だけのソース,
トレイン電極を形成した俊、基板仝而に非晶質シリコン
層、引き続いてゲート絶縁膜層を形成し、ゲート電極を
形成した後にフォトリソグラフィーおよびエッチングに
よって各薄膜トランジスタに分割するという方法で製作
されてきた。[Prior art and its problems 1] A thin film transistor element array used for driving pixels of a liquid crystal display, etc. requires forming a large number of thin film transistors at once on a substrate. Conventionally, such a thin film transistor element array was described by Sunada in 1985, Proceedings of International Display Research Conference (Procee
ding of Iritel'rla-tional
Display Research Conference
For example, in the case of a staggered structure, as many sources as necessary can be placed on the substrate, as reported in 66.
The method used to form the train electrode was to form an amorphous silicon layer on the substrate, followed by a gate insulating film layer, and after forming the gate electrode, divide it into each thin film transistor by photolithography and etching. .
この製作法によると各薄膜トランシス夕べの分割の際、
ゲート電極と同じ幅に非晶貿シリコンをエッチングする
には、上層のゲート絶縁膜もエッチングする必要がある
。そのため完成した素子においては、ゲート絶縁膜側壁
を経て流れるリーク電流を無視できない。これに対し、
表面全体を保護絶縁膜で覆っても側壁部は絶縁耐圧不良
になり易いので、長期の素子動作にわたって、このよう
なリーク電流を防止することは困難である。According to this fabrication method, when dividing each thin film transistor,
In order to etch the amorphous silicon to the same width as the gate electrode, it is necessary to also etch the upper gate insulating film. Therefore, in the completed device, leakage current flowing through the sidewalls of the gate insulating film cannot be ignored. In contrast,
Even if the entire surface is covered with a protective insulating film, the sidewall portions are likely to have poor dielectric strength, so it is difficult to prevent such leakage current over long-term device operation.
本発明の目的は、このような従来技術の問題点を解決し
たゲートリーク電流か少ない薄膜トランジスタ素子アレ
イを提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor element array with reduced gate leakage current that solves the problems of the prior art.
[課題を解決するための手段]
本発明は、ソース電極およびトレイン電極間に半導体層
が形成され、該半導体層上にゲート絶縁膜およびゲート
電極が順次形成ざれた薄膜トランジスタを同一基板上に
複数個備えた薄膜トランジスタ素子アレイにおいて、ゲ
ート絶縁膜は基板の全面に一括形成されていることを特
徴とする薄膜トランジスタ素子アレイである。[Means for Solving the Problems] The present invention provides a plurality of thin film transistors on the same substrate, in which a semiconductor layer is formed between a source electrode and a train electrode, and a gate insulating film and a gate electrode are sequentially formed on the semiconductor layer. This thin film transistor element array is characterized in that the gate insulating film is formed all over the entire surface of the substrate.
[作用]
薄膜トランジスタにおいて、ゲート電極とゲト絶縁膜と
が同一形状,同一面積で膜厚方向に重なった構造では、
ゲート電極からゲート絶縁膜側壁を経て半導体層あるい
はドレイン,ソース電極へと至る距離がきわめて短いた
めに、この経路を流れるリーク電流が素子の電気的特性
に与える影響か大きい。しかし、ゲート絶縁膜の面積が
ゲト電極の面積に較べて十分に大きく、ゲート電極とゲ
ート絶縁膜側壁との間の距離が、ゲート絶縁膜厚に較べ
十分に大きければ、このような経路を通って流れるリー
ク電流の量はごく微量である。[Function] In a thin film transistor, in a structure in which the gate electrode and gate insulating film have the same shape and area and overlap in the film thickness direction,
Since the distance from the gate electrode to the semiconductor layer or the drain and source electrodes via the sidewalls of the gate insulating film is extremely short, leakage current flowing through this path has a large effect on the electrical characteristics of the device. However, if the area of the gate insulating film is sufficiently large compared to the area of the gate electrode, and the distance between the gate electrode and the sidewall of the gate insulating film is sufficiently large compared to the thickness of the gate insulating film, then such a path can be used. The amount of leakage current that flows is extremely small.
本発明においては、半導体層が各薄膜トランジスタのド
レイン,ソース電極間に選択的に形成ざれ、かつゲート
絶縁膜はこれら半導体層および半導体層間の上部に全面
一括で形成された構造の薄膜トランジスタ素子アレイと
する。このため、アレイを構成するいずれの薄膜トラン
ジスタにおいても、ゲート電極とゲート絶縁膜側壁との
間はゲト膜厚に較べて十分に長い距離で離れているので
、ゲート絶縁膜側壁を流れるリーク電流は、その影響が
無視できるほど小さくなる。In the present invention, a thin film transistor element array has a structure in which a semiconductor layer is selectively formed between the drain and source electrodes of each thin film transistor, and a gate insulating film is formed all over the top of these semiconductor layers and between the semiconductor layers. . Therefore, in any thin film transistor that makes up the array, the distance between the gate electrode and the side wall of the gate insulating film is sufficiently long compared to the gate film thickness, so the leakage current flowing through the side wall of the gate insulating film is The effect becomes so small that it can be ignored.
[実施例]
以下に本発明の実施例について図面を参照して詳細に説
明する。[Examples] Examples of the present invention will be described in detail below with reference to the drawings.
第1図は本発明による薄膜トランジスタ素子アレイの一
例の部分断面図でおる。各電極材料としてはクロム、ゲ
ート絶縁膜材料としてはSiN1半導体層としては非品
質水素化シリコンを用いた。FIG. 1 is a partial cross-sectional view of an example of a thin film transistor element array according to the present invention. Chromium was used as the material for each electrode, SiN was used as the gate insulating film material, and non-quality hydrogenated silicon was used as the semiconductor layer.
第2図は本発明の薄膜トランジスタ素子アレイの製造に
用いられる装置の一例を示す概略構成図である。第2図
において、基板3はレーザC V Dチャンバ5内に設
置され、ArFレーザ1からの出射光をマスク2および
合成石英窓4を通して、基板3上のドレイン,ソース電
極8間にパターン転写される。基板3はレーザCVDチ
ャンバ5と共に、XYステージ6によってマスク2との
相対的位置を変えられるようになっている。またレザC
VDチャンバ5はプラズマCVDチャンパ7に連結して
おり、成膜後の基板を移動させてゲト絶縁膜の一括形成
ができるようになっている。FIG. 2 is a schematic configuration diagram showing an example of an apparatus used for manufacturing the thin film transistor element array of the present invention. In FIG. 2, a substrate 3 is placed in a laser CVD chamber 5, and a pattern is transferred between the drain and source electrodes 8 on the substrate 3 through the light emitted from the ArF laser 1 through a mask 2 and a synthetic quartz window 4. Ru. The relative position of the substrate 3 and the mask 2 can be changed together with the laser CVD chamber 5 by an XY stage 6. Also leather C
The VD chamber 5 is connected to a plasma CVD chamber 7, and the gate insulating film can be formed all at once by moving the substrate after film formation.
以上のように構成ざれた成膜装置を用い、以下のように
して第1図に示す薄膜トランジスタ素子アレイを製造し
た。Using the film forming apparatus configured as described above, the thin film transistor element array shown in FIG. 1 was manufactured in the following manner.
まず第1図に示すガラス基板3上にクロム膜をスパッタ
リング法により成膜し、パターニングを行うことにより
、ソース電極10およびドレイン電4リ1を形成する。First, a chromium film is formed by sputtering on a glass substrate 3 shown in FIG. 1, and patterned to form a source electrode 10 and a drain electrode 41.
次にこのカラス基板3を第2図のレーザCVDチャンハ
5内に固定し、ArFレザ1からの出射光をマスク2,
合成石英窓4を通してソース電極10とドレイン電極1
1の間にパターン転写する。ジシラン(S!2H6)カ
スをArFレーザ1で光化学分解することにより、半導
体層9としてa−Si:HvAのパターン薄膜を形成し
た。次にガラス基板3をレーザCVDチャンバ5と共に
XYステージ6によって光照射を行った領域の幅だけ移
動させて同じ成膜工程を繰り返し、ガラス基板3の全面
に半導体層9のパターンを形成した。Next, this glass substrate 3 is fixed in a laser CVD chamber 5 shown in FIG.
Source electrode 10 and drain electrode 1 through synthetic quartz window 4
The pattern is transferred during 1. By photochemically decomposing disilane (S!2H6) scum using an ArF laser 1, a patterned thin film of a-Si:HvA was formed as a semiconductor layer 9. Next, the glass substrate 3 was moved along with the laser CVD chamber 5 by the width of the area irradiated with light by the XY stage 6, and the same film forming process was repeated to form a pattern of the semiconductor layer 9 on the entire surface of the glass substrate 3.
続いてガラス基板3をプラズマCVDチャンバ7に移動
させ、原料ガスとしてシランあよびアンモニアを用いて
SiN膜のプラズマCVDを行うことによりゲート絶縁
膜12を形成した。続いてスパッタリングしてカラス基
板3上にクロム膜を成膜し、パターニングを行うことに
よりゲート電極13を形成した。Subsequently, the glass substrate 3 was moved to the plasma CVD chamber 7, and the gate insulating film 12 was formed by plasma CVD of the SiN film using silane and ammonia as source gases. Subsequently, a chromium film was formed on the glass substrate 3 by sputtering and patterned to form the gate electrode 13.
以上の工程を経て作製した薄膜トランジスタ素子アレイ
においては、ゲート電極からゲート絶縁膜側壁を通って
流れるリーク電流は観測ざれなかった。In the thin film transistor element array manufactured through the above steps, no leakage current flowing from the gate electrode through the side walls of the gate insulating film was observed.
なおゲート絶縁膜には必ずしもSiNを用いる必要はな
く、SiO2でも構わない。また、各電極は必ずしもク
ロムである必要はなく、タンタル,アルミニウムでも構
わない。また、半導体層には必ずしもa−3i:l−1
を用いる必要はなく、ポリシリコンでも構わない。Note that it is not necessarily necessary to use SiN for the gate insulating film, and SiO2 may also be used. Furthermore, each electrode does not necessarily have to be made of chromium, but may also be made of tantalum or aluminum. In addition, the semiconductor layer does not necessarily have a-3i:l-1
It is not necessary to use polysilicon, and polysilicon may be used.
また、半導体層の形成には必ずしもレーザCVDを用い
る必要はなく、工程数は増えるかプラズマCVD等で基
板全面に一括形成した半導体薄膜を、フォトリソグラフ
イとエッチングによりパタニングしても構わない。Further, it is not always necessary to use laser CVD to form the semiconductor layer, and although the number of steps is increased, a semiconductor thin film that has been formed all over the substrate by plasma CVD or the like may be patterned by photolithography and etching.
なお、液晶ディスプレイ応用上、仝而に本発明のように
薄く絶縁膜が形成されていても、画素駆動や、ガラス基
板の透光性に支障を与えないことは明らかである。Note that in terms of liquid crystal display applications, it is clear that even if the insulating film is formed as thinly as in the present invention, it will not impede pixel drive or the translucency of the glass substrate.
[発明の効果]
以上説明したように、本発明の薄膜トランジスタ素子ア
レイは、ゲート電極からのリーク電流がほとんどなく、
長期にわたって良好な素子動作が可能である。[Effects of the Invention] As explained above, the thin film transistor element array of the present invention has almost no leakage current from the gate electrode.
Good device operation is possible over a long period of time.
第1図は本発明の一実施例の部分断面図、第2図は本発
明の薄膜トランジスタ素子アレイの製造に用いられる装
置の一例の概略構成図である。
1・・・ArFレーザ 2・・・マスク3・・・
(カラス)基板 4・・・合成石英窓5・・・レー
ザCVDチャンバ
6・・・XYステージ
7・・・プラズマCVDチャンバ
8・・・電極FIG. 1 is a partial sectional view of an embodiment of the present invention, and FIG. 2 is a schematic configuration diagram of an example of an apparatus used for manufacturing a thin film transistor element array of the present invention. 1...ArF laser 2...mask 3...
(Crow) Substrate 4... Synthetic quartz window 5... Laser CVD chamber 6... XY stage 7... Plasma CVD chamber 8... Electrode
Claims (1)
成され、該半導体層上にゲート絶縁膜およびゲート電極
が順次形成された薄膜トランジスタを同一基板上に複数
個備えた薄膜トランジスタ素子アレイにおいて、ゲート
絶縁膜は基板の全面に一括形成されていることを特徴と
する薄膜トランジスタ素子アレイ。(1) In a thin film transistor element array including a plurality of thin film transistors on the same substrate, in which a semiconductor layer is formed between a source electrode and a drain electrode, and a gate insulating film and a gate electrode are sequentially formed on the semiconductor layer, the gate insulating film is a thin film transistor element array characterized by being formed all over the entire surface of a substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4992589A JPH02230773A (en) | 1989-03-03 | 1989-03-03 | Thin film transistor element array |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4992589A JPH02230773A (en) | 1989-03-03 | 1989-03-03 | Thin film transistor element array |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02230773A true JPH02230773A (en) | 1990-09-13 |
Family
ID=12844592
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4992589A Pending JPH02230773A (en) | 1989-03-03 | 1989-03-03 | Thin film transistor element array |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02230773A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5767531A (en) * | 1994-08-29 | 1998-06-16 | Sharp Kabushiki Kaisha | Thin-film transistor, method of fabricating the same, and liquid-crystal display apparatus |
-
1989
- 1989-03-03 JP JP4992589A patent/JPH02230773A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5767531A (en) * | 1994-08-29 | 1998-06-16 | Sharp Kabushiki Kaisha | Thin-film transistor, method of fabricating the same, and liquid-crystal display apparatus |
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