KR100707024B1 - Method for fabricating array substrate of TFT-LCD - Google Patents

Abstract

The present invention discloses a method for manufacturing an array substrate of a thin film transistor liquid crystal display device. The disclosed method includes forming a gate line including a gate electrode on a glass substrate, and then depositing a gate insulating film, an a-Si film, an n + a-Si film, and a Mo film on a substrate to cover the gate line. Forming a halftone mask having a relatively thin thickness of a portion disposed on a channel region between a source electrode and a drain electrode while covering a data line formation region including a source / drain electrode on the Mo film; And etching the Mo film to form a data line by a dry etching process using the halftone mask, removing a halftone mask portion on the channel region by an etching process, SF ₆ and Cl for the substrate resultant. a _second gas using a dry etching process in the n + a-Si film and the a-Si film is etched to form the active layers of channels of the Mo film and the n + a-Si film is continuous With each to form the source / drain electrodes and a channel comprises the step of configuring the thin-film transistor. According to the present invention, an etching process in a 4-mask process is performed by performing an active etching process, a secondary etching process of a source / drain metal film, and an etching process of an n + a-Si film by dry etching using SF ₆ and Cl ₂ gas. Simplification can be obtained, so that productivity can be improved.

Description

Method for fabricating array substrate of thin film transistor liquid crystal display device

1A to 1E are cross-sectional views of respective processes for explaining a method of manufacturing an array substrate of a thin film transistor liquid crystal display according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

1 glass substrate 2 gate electrode

3: gate insulating film 4: amorphous silicon film

5: doped amorphous silicon film 6: metal film for source / drain

6a: source electrode 6b: drain electrode

7: halftone pattern 10: thin film transistor

The present invention relates to a method for manufacturing a thin film transistor liquid crystal display device, and more particularly, to an array substrate manufacturing method using a four-mask process.

Liquid crystal displays have been developed in place of CRT (Cathode Ray Tube) based on the advantages of low weight, low voltage driving and low power consumption. In particular, thin film transistor liquid crystal display (hereinafter referred to as TFT-LCD) has high image quality comparable to CRT. In recent years, it has been widely used in various fields as well as the notebook PC and monitor market because it has realized large size and colorization.

The TFT-LCD has a structure in which an array substrate including a thin film transistor and a pixel electrode, and a color filter substrate including a color filter and a counter electrode are bonded to each other under an intervening liquid crystal layer.

On the other hand, in such a TFT-LCD, it is very important to reduce the number of manufacturing steps thereof, in particular, the number of manufacturing steps of the array substrate. This is because as the number of manufacturing processes is reduced, the manufacturing cost of the TFT-LCD can be reduced, because a larger amount of TFT-LCD can be supplied at a lower price.

Here, the reduction of the number of manufacturing processes is usually realized by the reduction of the number of mask processes, and recently, TFT-LCDs are manufactured by 5-mask and 4-mask processes. The mask process may be understood as a process of forming a photoresist pattern which is an etch mask through photoresist coating, exposure and development processes.

Hereinafter, an array substrate manufacturing method using a conventional 4-mask process will be briefly described.

First, a gate metal film is deposited on a glass substrate, and then the metal film is patterned to form a gate line including a gate electrode.

Next, a gate insulating film, an undoped amorphous silicon (hereinafter, a-Si) film, a doped amorphous silicon (n + a-Si) film, and a source / drain metal film are formed on the entire surface of the substrate to cover the gate line. Deposition in turn.

Subsequently, a half-tone mask having a relatively thin thickness of a portion disposed on the channel region while covering the data line formation region including the source / drain electrodes on the source / drain metal film according to the third mask process is performed. ).

Thereafter, the source / drain metal film, the n + a-Si film, and the a-Si film are etched using a halftone mask to form a data line, and then the halftone mask portion on the channel region is removed through an etching process. Subsequently, the n + a-Si film and the a-Si film are etched to form an active layer, and the source / drain metal film is etched again to form a source / drain electrode. Then, the n + a-Si film is etched to form a channel, thereby forming a thin film transistor.

Next, after the protective film is applied on the substrate resultant up to the step, the protective film is etched through a third mask process to form a via hole exposing the source / drain electrodes.

Thereafter, an ITO metal film is deposited on the protective film including the via hole, and then the ITO metal film is patterned through a fourth mask process to form a pixel electrode, thereby completing the fabrication of the array substrate.

However, the method of manufacturing an array substrate using the conventional four-mask process as described above is performed by the primary etching of the source / drain metal film, the etching, the active etching, and the source / drain metal film during the etching process using a halftone mask. At least five etching processes, such as secondary etching and etching of the n + a-Si film, should be performed. In this case, each of the five etching processes should be performed by wet etching, dry etching, dry etching, wet etching, and dry etching. There is a hassle in the process of using alternating equipment and dry equipment.

In addition, even if the five etching processes are continuously etched by dry etching in a single chamber, although not described in detail, there is still a complicated problem because the etching gas must be continuously replaced for each layer.

As mentioned above, since the mask process includes photoresist coating, exposure and development processes, the conventional array substrate manufacturing process is not only complicated by itself, but still cost-effective, as long as it uses the 5-mask process, However, there is a limit to lowering product cost.

Accordingly, an object of the present invention is to provide a method for manufacturing an array substrate of a TFT-LCD, which can be obtained to solve the above problems and to simplify the etching process in a 4-mask process.

In order to achieve the above object, the present invention, forming a gate line including a gate electrode on a glass substrate; Depositing a gate insulating film, an a-Si film, an n + a-Si film, and an Mo film on a substrate so as to cover the gate line; Forming a halftone mask having a relatively thin thickness on a portion of the portion disposed on the channel region between the source electrode and the drain electrode while covering a data line formation region including a source / drain electrode on the Mo film; Etching the Mo film to form a data line by a dry etching process using the halftone mask; Removing the halftone mask portion on the channel region by an etching process; And etching the n + a-Si film and the a-Si film by dry etching using SF ₆ and Cl ₂ gas to the substrate product to form an active layer, and continuously etching the Mo film and the n + a-Si film of the channel portion. Forming a source / drain electrode and a channel to form a thin film transistor; and providing an array substrate manufacturing method of a TFT-LCD.

Here, the dry etching process using the SF ₆ and Cl ₂ gas is carried out in a reactive ion etching process with the composition of SF ₆ gas and Cl ₂ gas of 5 to 40% and 60 to 95%.

In addition, the method of the present invention, after the step of configuring the thin film transistor, the step of removing the remaining halftone mask; Depositing a protective film on the substrate resultant up to this step; Etching the passivation layer to form a via hole exposing a source / drain electrode; Depositing an ITO metal film on the protective film including the via hole; And forming a pixel electrode by patterning the ITO metal film.

According to the present invention, an etching process in a 4-mask process is performed by performing an active etching process, a secondary etching process of a source / drain metal film, and an etching process of an n + a-Si film by dry etching using SF ₆ and Cl ₂ gas. Simplification can be obtained, so that productivity can be improved.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1D are cross-sectional views illustrating processes for manufacturing an array substrate of a TFT-LCD according to an exemplary embodiment of the present invention.

Referring to FIG. 1A, after depositing a gate metal film on the glass substrate 1, the metal film is patterned by a first mask process to form a gate line including the gate electrode 2 (not shown). Then, the gate insulating film 3 is deposited on the entire region of the substrate 1 to cover the gate line including the gate electrode 2, and then the a-Si film 4 is sequentially on the gate insulating film 3. ), an n + a-Si film 5 and a Mo film 6 which is a metal film for source / drain are deposited.

Next, according to the second mask process, a halftone mask 7 having a relatively thin thickness of a portion disposed on the channel region while covering the data line formation region including the source / drain electrodes on the Mo film 6 is formed. Form.

Referring to FIG. 1B, the Mo film 6 is first etched by dry etching or wet etching using a mixed gas of SF ₆ , O _2, and He while using the halftone mask 7, and through this, a data line ( Not shown).

Referring to FIG. 1C, the halftone mask portion on the channel region is removed by performing an ashing process using O ₂ gas on the substrate resultant.

Referring to FIG. 1D, in the dry etching process using SF ₆ and Cl ₂ gas, the secondary etching of the Mo film, which is an active etching and a source / drain metal film, and the etching of the n + a-Si film 5 are collectively etched. The thin film transistor 10 is formed by forming an active layer, source / drain electrodes 6a and 6b, and a channel. At this time, the composition of the SF ₆ gas and Cl ₂ gas is 5 to 40% and 60 to 95% so that the Cl ₂ gas is excessive, and the dry etching is, for example, reactive ion etching (Reactive Ion Etch) Carried out in the process.

Here, the active etching, secondary etching of the Mo film and collective etching of the n + a-Si film is based on the following principle.

In general, plasma etching of SF ₆ and Cl ₂ has a high etch rate for silicon, whereas a slow etching rate for Mo film is not used for Mo etching. However, since the etching rate is relatively increased for the Mo film of the channel portion having a very small area to be etched, the SF ₆ and Cl ₂ gases can also be used for etching the Mo film. Therefore, when etching is performed using the SF ₆ and Cl ₂ gas, SF ₆ and Cl ₂ are mainly consumed in active etching at the initial stage of etching, so that the Mo film of the channel part is not etched much, but after the active etching is completed, the SF ₆ and Cl ₂ are consumed to etch the Mo film in the channel portion, so that the etch rate of the Mo film is increased, so that the Mo film in the channel portion is etched within a short time. Thereafter, since the n + a-Si film is continuously etched, the second etching of the Mo film, which is the active etching and the source / drain metal film, and the collective etching of the n + a-Si film are possible.

Therefore, in the present invention, since the active etching and the second etching of the Mo film, which is the source / drain metal film, and the collective etching of the n + a-Si film are possible, wet and dry equipment may be alternately used for the unit etching processes. Not only can the process troublesome be solved, but the process can be simplified.

Subsequently, although not shown, after the protective film is applied on the substrate resultant with the remaining halftone mask removed, the protective film is etched through a third mask process to form a via hole exposing the source / drain electrodes.

Thereafter, an ITO metal film is deposited on the protective film including the via hole, and then the ITO metal film is patterned through a fourth mask process to form a pixel electrode, thereby completing the fabrication of the array substrate.

As described above, the present invention uses a four-mask process, but the wet and dry equipment must be used alternately by performing the active etching, the second etching of the source / drain metal film, and the etching of the n + a-Si film by batch etching. The process hassle can be eliminated, and the process can be simplified through batch etching, thereby improving productivity.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (4)

Forming a gate line including a gate electrode on the glass substrate; Depositing a gate insulating film, an a-Si film, an n + a-Si film, and an Mo film on a substrate so as to cover the gate line; Forming a halftone mask having a relatively thin thickness on a portion of the portion disposed on the channel region between the source electrode and the drain electrode while covering a data line formation region including a source / drain electrode on the Mo film; Etching the Mo film to form a data line by a dry etching process using the halftone mask; Removing the halftone mask portion on the channel region by an etching process; And The n + a-Si film and the a-Si film are etched to form an active layer by dry etching using SF ₆ and Cl ₂ gas to the substrate resultant, and the Mo film and the n + a-Si film of the channel portion are continuously etched. / Forming a drain electrode and a channel to form a thin film transistor; Array substrate manufacturing method of a thin film transistor liquid crystal display device comprising a. The method of claim 1, The SF ₆ as a dry etching process using a Cl ₂ gas is an array substrate manufacturing method of a thin film transistor liquid crystal display device, characterized in that performing by the composition 5 to 40% and 60-95% of the SF ₆ and Cl ₂ gas. The method of claim 1, The dry etching process using the SF ₆ and Cl ₂ gas is a method of manufacturing an array substrate of a thin film transistor liquid crystal display device, characterized in that to perform a reactive ion etching (Reactive Ion Etch) process. The method of claim 1, After the step of configuring the thin film transistor, Removing the remaining halftone mask; Depositing a protective film on the substrate resultant up to this step; Etching the passivation layer to form a via hole exposing a source / drain electrode; Depositing an ITO metal film on the protective film including the via hole; And And forming a pixel electrode by patterning the ITO metal film.

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