JPS61188967A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPS61188967A JPS61188967A JP60029134A JP2913485A JPS61188967A JP S61188967 A JPS61188967 A JP S61188967A JP 60029134 A JP60029134 A JP 60029134A JP 2913485 A JP2913485 A JP 2913485A JP S61188967 A JPS61188967 A JP S61188967A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- thin film
- source
- entire surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims description 28
- 239000002184 metal Substances 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 239000010408 film Substances 0.000 claims description 33
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 10
- 238000001259 photo etching Methods 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000011109 contamination Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H01L29/78618—
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、液晶ディスプレイ装置に適用される薄膜トラ
ンジスタに関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a thin film transistor applied to a liquid crystal display device.
(従来の技術)
薄膜トランジスタの従来構造の一例を第6図(a)(b
)に示す。(Prior art) An example of the conventional structure of a thin film transistor is shown in FIGS. 6(a) and 6(b).
).
図面において、aは絶縁性基板、bはゲート電極、Cは
ゲート絶縁膜、dは半導体膜、eはn゛−アモルファス
Si膜、fはソース電極1gはドレイン電極、hは絵素
電極、iはチャンネル開口部である。絵素電極りはドレ
イン電極gの上面の一部を覆うように形成されている。In the drawing, a is an insulating substrate, b is a gate electrode, C is a gate insulating film, d is a semiconductor film, e is an n-amorphous Si film, f is a source electrode, 1g is a drain electrode, h is a pixel electrode, i is the channel opening. The picture element electrode layer is formed to cover a part of the upper surface of the drain electrode g.
この薄膜トランジスタの構造は、半導体膜dがチャンネ
ル開口部iを除いてソース電極fおよびドレイン電極g
と同じパターンであるため、ストレー容量を最小限に押
えることができるとともに。In the structure of this thin film transistor, the semiconductor film d has a source electrode f and a drain electrode g except for the channel opening i.
Since it has the same pattern as the previous one, it is possible to keep the storage capacity to a minimum.
半導体膜dとソース電極fおよびドレイン電極gとの接
触部分を、製造工程、において発生する汚染から保護す
ることができるという利点がある。There is an advantage that the contact portions between the semiconductor film d and the source electrode f and drain electrode g can be protected from contamination generated during the manufacturing process.
しかしながら1表示パネルの解像度を向上させるために
は絵素電極を増加する必要があり、必然的にソース電極
幅lの短縮化が要求される。However, in order to improve the resolution of one display panel, it is necessary to increase the number of picture element electrodes, which inevitably requires a reduction in the source electrode width l.
この場合、ソースパスラインの抵抗の増加を押えるとと
もに2表示パネルの製造の歩留りを向上させるため、ソ
ース電極fの断線対策および製造工程の簡素化が必要で
ある。In this case, in order to suppress the increase in the resistance of the source pass line and improve the manufacturing yield of two display panels, it is necessary to take measures against disconnection of the source electrode f and to simplify the manufacturing process.
(発明の目的)
零発鴫は、ソース電極の断線不良を防止するとともに、
ホトエツチング工程の短縮化を図り、安定で特性の優れ
た新規構造の薄膜トランジスタを提供することを目的と
している。(Purpose of the invention) The zero discharge prevents disconnection of the source electrode, and
The purpose is to shorten the photo-etching process and provide a thin film transistor with a new structure that is stable and has excellent characteristics.
(発明の構成) 本発明の薄膜トランジスタは、絶縁性基板上に。(Structure of the invention) The thin film transistor of the present invention is provided on an insulating substrate.
ゲート電極、ゲート絶縁膜、半導体膜、金属薄膜が順次
積層されるとともに、この金属薄膜がソース電極および
ドレイン電極に形成されたものにおいて、前記ソース電
極およびドレイン電極の面上に絵素電極を兼ねる透明導
電膜が重ねて形成されてなるものである。In a structure in which a gate electrode, a gate insulating film, a semiconductor film, and a metal thin film are sequentially laminated, and the metal thin films are formed on a source electrode and a drain electrode, the surface of the source electrode and drain electrode also serves as a picture element electrode. It is formed by overlapping transparent conductive films.
(作用)
ソース電極およびドレイン電極が金属薄膜と透明導電膜
の二層構造になるとともに、ソース電極。(Function) The source electrode and drain electrode have a two-layer structure of a metal thin film and a transparent conductive film, and the source electrode.
ドレイン電極、および絵素電極が同じホトエツチング工
程によって同時にパターン化される。The drain electrode and the pixel electrode are patterned simultaneously by the same photoetching process.
(実施例)
第1図fa) (b)は本発明にかかる薄膜トランジス
タの構造を示している。(Example) FIG. 1 fa) (b) shows the structure of a thin film transistor according to the present invention.
この薄膜トランジスタ1は、絵素電極9を兼ねる透明導
電膜10が、ソース電極7およびドレイン電極8の全面
に形成されたもので、その他の構造は前記した従来構造
と同様である。すなわち。In this thin film transistor 1, a transparent conductive film 10 which also serves as a picture element electrode 9 is formed on the entire surface of a source electrode 7 and a drain electrode 8, and the other structure is the same as the conventional structure described above. Namely.
2は絶縁性基板、3はゲート電極、4はゲート絶縁膜、
5は半導体膜(アモルファスSi膜)、6はn9−アモ
ルファスSi膜である。2 is an insulating substrate, 3 is a gate electrode, 4 is a gate insulating film,
5 is a semiconductor film (amorphous Si film), and 6 is an n9-amorphous Si film.
次に、第2図(a)(b)〜第5図(a) (b)を参
照して前記した薄膜トランジスタ1の製造工程を説明す
る。Next, the manufacturing process of the thin film transistor 1 described above will be explained with reference to FIGS. 2(a) and 5(b) to FIGS. 5(a) and 5(b).
■ ガラス基板等からなる絶縁性基板2の全面にスパッ
タリングもしくは電子ビーム蒸着によりTaもしくはA
I等の金属薄膜を形成し、ホトエツチングによりパター
ン化してゲート電極3を形成する〔第2図(a) (b
)参照〕。■ Ta or A is deposited on the entire surface of the insulating substrate 2 made of a glass substrate or the like by sputtering or electron beam evaporation.
A metal thin film such as I is formed and patterned by photoetching to form the gate electrode 3 [Fig. 2(a) (b)
)reference〕.
■ 次に、このゲート電極3を含む絶縁性基板2の全面
に、ゲート絶縁膜4となるSi3N4膜4aをプラズマ
CVDにより1000人の厚みに形成し、続いて、半導
体膜5となるアモルファスSi膜5aをプラズマCVD
により1500人の厚みに形成し、さらに、n“−アモ
ルファスSi膜6.およびソース電極7.ドレイン電極
8となる金属薄膜7aをプラズマCVDもしくはスパッ
タリングによりそれぞれ形成する〔第3図(a) (b
)参照〕。(2) Next, on the entire surface of the insulating substrate 2 including the gate electrode 3, a Si3N4 film 4a, which will become the gate insulating film 4, is formed to a thickness of 1000 nm by plasma CVD. 5a by plasma CVD
Furthermore, metal thin films 7a, which will become the n''-amorphous Si film 6, the source electrode 7, and the drain electrode 8, are formed by plasma CVD or sputtering [Fig. 3(a) (b)].
)reference〕.
■ 次に、金属薄膜7a、n”−アモルファスSi膜6
.アモルファスSi膜5a、5izN4膜4aを上層部
から連続してエツチングし、金属薄膜7aをチャンネル
開口部12 〔第1図(b)参照〕がまだ形成されてい
ないソース・ドレイン電極パターン13に形成する〔第
4図(a) (b)参照〕。■ Next, the metal thin film 7a, the n''-amorphous Si film 6
.. The amorphous Si film 5a and the 5izN4 film 4a are etched continuously from the upper layer, and the metal thin film 7a is formed in the source/drain electrode pattern 13 where the channel opening 12 [see FIG. 1(b)] has not yet been formed. [See Figures 4(a) and (b)].
■ 次に、ソース・ドレイン電極パターン13を含む絶
縁性基板2の全面に、絵素電極9となる透明導電膜(r
nzo*)10をスパッタリングもしくは電子ビーム蒸
着により形成する〔第5図fa) (b)参照〕。その
後、透明導電膜10の全面にホトレジストを塗布し、一
枚のホトマスクで。■ Next, a transparent conductive film (r
nzo*) 10 is formed by sputtering or electron beam evaporation [see FIG. 5 fa) (b)]. After that, photoresist is applied to the entire surface of the transparent conductive film 10 using a single photomask.
ソース電極7.ドレイン電極8.および絵素電極9のパ
ターンにホトレジスト11をパターン化し、つづいて透
明導電膜10. ソース・ドレイン電極パターン13.
n”−アモルファスSi膜6の順にそれぞれエツチング
して、第1図(al(b)に示す構造の薄膜トランジス
タ1を形成する。Source electrode7. Drain electrode8. Then, photoresist 11 is patterned in the pattern of picture element electrode 9, and then transparent conductive film 10. Source/drain electrode pattern 13.
The n''-amorphous Si film 6 is etched in order to form a thin film transistor 1 having the structure shown in FIG. 1 (al(b)).
(発明の効果)
以上説明したように2本発明の薄膜トランジスタによれ
ば、ソース電極およびドレイン電極の全面に形成される
透明導電膜と絵素電極となる透明導電膜を同時にパター
ン化することができるので。(Effects of the Invention) As explained above, according to the thin film transistor of the present invention, the transparent conductive film formed on the entire surface of the source electrode and the drain electrode and the transparent conductive film that becomes the pixel electrode can be patterned at the same time. So.
従来四枚必要であったホトマスクを三枚に減らすことが
できる。また、ソース電極が金属薄膜と透明導電膜の二
層構造になるので、ソース電極の断線が減少し、薄膜ト
ランジスタの歩留りを向上することができる。The number of photomasks that conventionally required four can be reduced to three. Furthermore, since the source electrode has a two-layer structure of a metal thin film and a transparent conductive film, disconnections of the source electrode are reduced, and the yield of thin film transistors can be improved.
第1図(a) (h)は本発明の薄膜トランジスタの平
面図および縦断面図、第2図(a) (b)〜第5図(
a) (b)は第1図(a) (blに示す薄膜トラン
ジスタの製造工程を説明する工程図セ、第2図(a)、
第3図(a)、第4図(a)。
第5図(a)は平面図、第2図(b)、第3図(b)、
第4図(b)、第5図(blは縦断面図、第6図(al
(blは従来の薄膜トランジスタの平面図および′#
1断面図である。
l・・・薄膜トランジスタ 5・・・半導体膜6・・
・no−アモルファスSi膜
7・・・ソース電% 7a・・・金属薄膜計
・・ドレイン電極 9・・・絵素電極10・・・
透明導電膜
ほか1名
第7図(a)
第2図(a)
第2図(b)
第3図s a )
第4図(a)
第4図(b)
第5囚(a)FIGS. 1(a) and (h) are a plan view and a vertical cross-sectional view of a thin film transistor of the present invention, and FIGS. 2(a) and (b) to FIG.
a) (b) are process diagrams explaining the manufacturing process of the thin film transistor shown in Fig. 1 (a) (bl), Fig. 2 (a),
Figures 3(a) and 4(a). Figure 5 (a) is a plan view, Figure 2 (b), Figure 3 (b),
Figure 4 (b), Figure 5 (bl is a vertical sectional view, Figure 6 (al
(bl is a plan view of a conventional thin film transistor and '#
FIG. 1 is a sectional view. l...Thin film transistor 5...Semiconductor film 6...
・No-amorphous Si film 7... Source voltage % 7a... Metal thin film meter... Drain electrode 9... Picture element electrode 10...
Transparent conductive film and 1 other person Figure 7 (a) Figure 2 (a) Figure 2 (b) Figure 3 s a ) Figure 4 (a) Figure 4 (b) Prisoner 5 (a)
Claims (1)
体膜、金属薄膜が順次積層されるとともに、この金属薄
膜がソース電極およびドレイン電極に形成されたものに
おいて、 前記ソース電極およびドレイン電極の面上 に絵素電極を兼ねる透明導電膜が重ねて形成されている
ことを特徴とする薄膜トランジスタ。[Claims] 1) A gate electrode, a gate insulating film, a semiconductor film, and a metal thin film are sequentially laminated on an insulating substrate, and the metal thin film is formed as a source electrode and a drain electrode, wherein: A thin film transistor characterized in that a transparent conductive film that also serves as a pixel electrode is formed on the surfaces of a source electrode and a drain electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60029134A JPH0797639B2 (en) | 1985-02-15 | 1985-02-15 | Display panel substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60029134A JPH0797639B2 (en) | 1985-02-15 | 1985-02-15 | Display panel substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61188967A true JPS61188967A (en) | 1986-08-22 |
JPH0797639B2 JPH0797639B2 (en) | 1995-10-18 |
Family
ID=12267818
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60029134A Expired - Lifetime JPH0797639B2 (en) | 1985-02-15 | 1985-02-15 | Display panel substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0797639B2 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01207721A (en) * | 1988-02-16 | 1989-08-21 | Sharp Corp | Matrix type liquid crystal display panel |
US5075674A (en) * | 1987-11-19 | 1991-12-24 | Sharp Kabushiki Kaisha | Active matrix substrate for liquid crystal display |
US6078365A (en) * | 1996-01-25 | 2000-06-20 | Kabushiki Kaisha Toshiba | Active matrix liquid crystal panel having an active layer and an intervening layer formed of a common semiconductor film |
US6707513B2 (en) | 2000-07-10 | 2004-03-16 | International Business Machines Corporation | Active matrix substrate and manufacturing method thereof |
JP2008209931A (en) * | 2008-03-12 | 2008-09-11 | Semiconductor Energy Lab Co Ltd | Liquid crystal display device |
JP4693219B2 (en) * | 2000-10-05 | 2011-06-01 | 三菱電機株式会社 | TFT array substrate for liquid crystal display device and manufacturing method thereof |
US9059045B2 (en) | 2000-03-08 | 2015-06-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6151878A (en) * | 1984-08-21 | 1986-03-14 | Seiko Instr & Electronics Ltd | Manufacture of thin-film transistor |
JPS61164268A (en) * | 1985-01-17 | 1986-07-24 | Nec Corp | Manufacture of thin film transistor |
-
1985
- 1985-02-15 JP JP60029134A patent/JPH0797639B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6151878A (en) * | 1984-08-21 | 1986-03-14 | Seiko Instr & Electronics Ltd | Manufacture of thin-film transistor |
JPS61164268A (en) * | 1985-01-17 | 1986-07-24 | Nec Corp | Manufacture of thin film transistor |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5075674A (en) * | 1987-11-19 | 1991-12-24 | Sharp Kabushiki Kaisha | Active matrix substrate for liquid crystal display |
JPH01207721A (en) * | 1988-02-16 | 1989-08-21 | Sharp Corp | Matrix type liquid crystal display panel |
US6078365A (en) * | 1996-01-25 | 2000-06-20 | Kabushiki Kaisha Toshiba | Active matrix liquid crystal panel having an active layer and an intervening layer formed of a common semiconductor film |
US9059045B2 (en) | 2000-03-08 | 2015-06-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US9368514B2 (en) | 2000-03-08 | 2016-06-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US9786687B2 (en) | 2000-03-08 | 2017-10-10 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US6707513B2 (en) | 2000-07-10 | 2004-03-16 | International Business Machines Corporation | Active matrix substrate and manufacturing method thereof |
KR100443804B1 (en) * | 2000-07-10 | 2004-08-09 | 인터내셔널 비지네스 머신즈 코포레이션 | Active matrix substrate and display device |
US6859252B2 (en) | 2000-07-10 | 2005-02-22 | International Business Machines Corporation | Active matrix substrate and manufacturing method thereof |
JP4693219B2 (en) * | 2000-10-05 | 2011-06-01 | 三菱電機株式会社 | TFT array substrate for liquid crystal display device and manufacturing method thereof |
JP2008209931A (en) * | 2008-03-12 | 2008-09-11 | Semiconductor Energy Lab Co Ltd | Liquid crystal display device |
Also Published As
Publication number | Publication date |
---|---|
JPH0797639B2 (en) | 1995-10-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |