JPH0222554B2 - - Google Patents

Info

Publication number
JPH0222554B2
JPH0222554B2 JP60049816A JP4981685A JPH0222554B2 JP H0222554 B2 JPH0222554 B2 JP H0222554B2 JP 60049816 A JP60049816 A JP 60049816A JP 4981685 A JP4981685 A JP 4981685A JP H0222554 B2 JPH0222554 B2 JP H0222554B2
Authority
JP
Japan
Prior art keywords
conductor pattern
layer
glass
thick film
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60049816A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61208295A (ja
Inventor
Toshio Matsuzaki
Haruo Tanmachi
Kyoshi Sato
Takumi Suzuki
Takeshi Sugii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60049816A priority Critical patent/JPS61208295A/ja
Priority to CA000476831A priority patent/CA1237019A/fr
Priority to US06/712,713 priority patent/US4689638A/en
Priority to DE8585302032T priority patent/DE3586065D1/de
Priority to EP85302032A priority patent/EP0157563B1/fr
Priority to KR1019850001981A priority patent/KR900002807B1/ko
Publication of JPS61208295A publication Critical patent/JPS61208295A/ja
Publication of JPH0222554B2 publication Critical patent/JPH0222554B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
JP60049816A 1984-03-26 1985-03-13 回路基板における多層導体パタ−ンの形成方法 Granted JPS61208295A (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP60049816A JPS61208295A (ja) 1985-03-13 1985-03-13 回路基板における多層導体パタ−ンの形成方法
CA000476831A CA1237019A (fr) 1984-03-26 1985-03-18 Tete d'enregistrement thermique et methode de fabrication d'un substrat de cablage pour cette tete
US06/712,713 US4689638A (en) 1984-03-26 1985-03-18 Thermal recording head and process for manufacturing wiring substrate therefor
DE8585302032T DE3586065D1 (de) 1984-03-26 1985-03-25 Thermischer druckkopf und verfahren zum herstellen einer schaltungsplatte dafuer.
EP85302032A EP0157563B1 (fr) 1984-03-26 1985-03-25 Tête d'impression thermique et procédé de fabrication de son substrat de câblage
KR1019850001981A KR900002807B1 (ko) 1984-03-26 1985-03-26 열 레코팅 헤드와 그 배선기판을 제조하는 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60049816A JPS61208295A (ja) 1985-03-13 1985-03-13 回路基板における多層導体パタ−ンの形成方法

Publications (2)

Publication Number Publication Date
JPS61208295A JPS61208295A (ja) 1986-09-16
JPH0222554B2 true JPH0222554B2 (fr) 1990-05-18

Family

ID=12841640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60049816A Granted JPS61208295A (ja) 1984-03-26 1985-03-13 回路基板における多層導体パタ−ンの形成方法

Country Status (1)

Country Link
JP (1) JPS61208295A (fr)

Also Published As

Publication number Publication date
JPS61208295A (ja) 1986-09-16

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