JPH02224256A - Semiconductor element connection structure - Google Patents
Semiconductor element connection structureInfo
- Publication number
- JPH02224256A JPH02224256A JP1044256A JP4425689A JPH02224256A JP H02224256 A JPH02224256 A JP H02224256A JP 1044256 A JP1044256 A JP 1044256A JP 4425689 A JP4425689 A JP 4425689A JP H02224256 A JPH02224256 A JP H02224256A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- bump
- connection
- superelastic
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 239000000463 material Substances 0.000 claims abstract description 14
- 238000009713 electroplating Methods 0.000 claims abstract description 6
- 229910000679 solder Inorganic materials 0.000 abstract description 18
- 238000002844 melting Methods 0.000 abstract description 4
- 230000008018 melting Effects 0.000 abstract description 4
- 238000003825 pressing Methods 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000010276 construction Methods 0.000 abstract 1
- 238000001556 precipitation Methods 0.000 abstract 1
- 238000007747 plating Methods 0.000 description 30
- 238000000034 method Methods 0.000 description 16
- 229910052751 metal Inorganic materials 0.000 description 15
- 239000002184 metal Substances 0.000 description 15
- 239000010949 copper Substances 0.000 description 12
- 229910052802 copper Inorganic materials 0.000 description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 11
- 229910052737 gold Inorganic materials 0.000 description 11
- 239000010931 gold Substances 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 9
- XEEYBQQBJWHFJM-UHFFFAOYSA-N iron Substances [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 8
- 239000011347 resin Substances 0.000 description 8
- 229920005989 resin Polymers 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229910052742 iron Inorganic materials 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229910052697 platinum Inorganic materials 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 229910052725 zinc Inorganic materials 0.000 description 3
- 239000011701 zinc Substances 0.000 description 3
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 2
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910017518 Cu Zn Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910017752 Cu-Zn Inorganic materials 0.000 description 1
- 229910017943 Cu—Zn Inorganic materials 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005489 elastic deformation Effects 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000010791 quenching Methods 0.000 description 1
- 230000000171 quenching effect Effects 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Abstract
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体素子の接続構造に関するものである。[Detailed description of the invention] (Industrial application field) The present invention relates to a connection structure for semiconductor elements.
（従来の技術）
従来の半導体素子のフリップチップ接続の概略構造を第
８図に示す。図中の１は半導体素子、２は配線基板、３
ははんだバンプ、４は半導体素子１と配線基板２のそれ
ぞれに設けられた電極であり、Ａ−λは半導体素子の中
心を示している。(Prior Art) FIG. 8 shows a schematic structure of a conventional flip-chip connection of semiconductor elements. In the figure, 1 is a semiconductor element, 2 is a wiring board, and 3
4 is a solder bump, 4 is an electrode provided on each of the semiconductor element 1 and the wiring board 2, and A-λ indicates the center of the semiconductor element.
フリップチップ接続は、半導体素子１と配線基板２の電
極４の電気的接続を、はんだバンプ３を加熱溶融する一
括接続で行えるので、ワイヤボンディング法に比べて作
業性が優れている。又、ワイヤボンディング法及びＴ
Ａ Ｂ （Ｔａｐｅ ＡｕｔｏｍａｔｅｄＢｏｎｄｉｎ
ｇ ）法のように電極配置が半導体素子の周辺に限定さ
れないので、大幅に接続端子数を増大できるという特徴
をもっている。Flip-chip bonding is superior in workability to the wire bonding method because the electrical connection between the semiconductor element 1 and the electrodes 4 of the wiring board 2 can be made in one batch by heating and melting the solder bumps 3. Also, wire bonding method and T
A B (Tape Automated Bondin
g) Since the electrode arrangement is not limited to the periphery of the semiconductor element as in the method, it has the feature that the number of connection terminals can be greatly increased.
しかしながら、この接続構造では第９図に示すように、
・温度変化が生じた場合半導体素子１と配線基板２との
熱膨張係数の差による寸法ずれＢが発生し、はんだバン
プ３に剪断歪みを生じ接続信頼性が低下する。However, with this connection structure, as shown in Figure 9,
- When a temperature change occurs, a dimensional deviation B occurs due to the difference in thermal expansion coefficients between the semiconductor element 1 and the wiring board 2, causing shear strain in the solder bumps 3 and reducing connection reliability.
剪断歪みは、はんだバンプ３と半導体素子１との中心距
離の増加とともに増大するため、はんだバンプ３の許容
しうる剪断歪み量からはんだバンプ３を配置できる領域
が制限され、多端子化ならびに大面積の半導体素子への
適用が困難であった。Since shear strain increases as the distance between the centers of the solder bumps 3 and the semiconductor element 1 increases, the area in which the solder bumps 3 can be placed is limited due to the amount of shear strain that the solder bumps 3 can tolerate. It has been difficult to apply this method to semiconductor devices.
このはんだバンプの剪断歪みを低減させる手段として、
半導体素子と熱膨張係数の近い配線基板材料を用いる方
法が考えられるが、配線基板材料が制限されてしまうと
いう欠点がある。As a means to reduce the shear strain of solder bumps,
A possible method is to use a wiring board material with a coefficient of thermal expansion close to that of the semiconductor element, but this method has the disadvantage that the wiring board material is limited.
一方、ポリイミドフィルムで支持したはんだバンプを重
ねて多段バンプを形成し、剪断歪みを低減する方法（特
開昭６２−２９３７３０号公報）が提案されている。On the other hand, a method has been proposed (Japanese Unexamined Patent Publication No. 62-293730) in which shearing strain is reduced by stacking solder bumps supported by polyimide films to form multistage bumps.
しかしながら、はんだバンプを積み重ねるため、必要部
材の増加、接続工数の増加に伴う価格上昇という欠点が
ある。However, since the solder bumps are stacked, there is a drawback that the number of required members increases and the number of connection steps increases, resulting in an increase in price.
又、第１０図は金属バンプを圧力で当接させて電気的接
続を得る半導体素子接続構造である。第１０図において
、半導体素子１と配線基板２のそれぞれの電極４上には
金属バンプ３３が形成されている。この金属バンプ３３
には樹脂５の硬化時の収縮力により圧力が加わり、金属
バンブ３３同士が機械的に接触し電気的接続が得られる
。Further, FIG. 10 shows a semiconductor element connection structure in which electrical connection is obtained by bringing metal bumps into contact with each other under pressure. In FIG. 10, metal bumps 33 are formed on the electrodes 4 of the semiconductor element 1 and the wiring board 2, respectively. This metal bump 33
Pressure is applied to the metal bumps 33 by the shrinkage force of the resin 5 when it hardens, and the metal bumps 33 come into mechanical contact with each other to establish an electrical connection.
しかしながら、この接続構造では金属バンプ３３の高さ
がバラツクと電気的接続が得られない箇所が生ずる。又
、樹脂５の熱膨張係数は金属バンプ３３に比べて大きい
ため、温度変化が生じると圧力が弱まり、金属バンプ３
３の接触が不安定になるので、接続信頼性に欠けるとい
う問題点があつた。However, in this connection structure, the height of the metal bumps 33 varies and there are places where electrical connection cannot be obtained. Furthermore, since the coefficient of thermal expansion of the resin 5 is larger than that of the metal bumps 33, when a temperature change occurs, the pressure weakens and the metal bumps 3
There was a problem in that connection reliability was lacking because the contact at point 3 became unstable.
（発明が解決しようとする課題）
本発明では、上記に述べた半導体素子と配線基板の間に
発生する大きな剪断歪み、バンプ高さのバラツキ及び樹
脂との熱膨張係数の差による圧力変動に対して電気的接
続の信頼性が高く、しかも微細接続が可能な安価な半導
体素子接続構造を提供するものである。(Problems to be Solved by the Invention) The present invention solves the above-mentioned large shear strain occurring between the semiconductor element and the wiring board, variations in bump height, and pressure fluctuations due to the difference in thermal expansion coefficient with the resin. The object of the present invention is to provide an inexpensive semiconductor element connection structure that has high reliability in electrical connection and allows fine connections.
（課題を解決するための手段）
本発明では、上記課題を解決するために超弾性体材料を
介在させた半導体素子実装構造として、超弾性体材料を
半導体素子の接続部又は実装配線基板の接続部に選択的
に電解析出させ、バンプ構造とし、そのバンプを接続点
として加圧又は表面にコートしたはんだなどを溶融させ
ることにより接続を得る半導体素子接続構造である。(Means for Solving the Problems) In order to solve the above problems, in the present invention, as a semiconductor element mounting structure in which a superelastic material is interposed, the superelastic material is used at the connection part of the semiconductor element or the connection part of the mounted wiring board. This is a semiconductor element connection structure in which a bump structure is formed by selectively electrolytically depositing the bumps, and connections are obtained by applying pressure or melting solder coated on the surface using the bumps as connection points.
これは超弾性体材料を半導体素子における熱歪みを受け
る部分に使用することにより繰り返しの歪みに対しても
弾性範囲で変形を繰り返すことで破断を防止することを
狙ったものであり、外部歪みに柔軟に追従するバンプ構
造であるため信軌性の高い接続が得られる。This is aimed at preventing breakage by using a superelastic material in the parts of the semiconductor element that are subject to thermal strain so that it can repeatedly deform within the elastic range even when subjected to repeated strain. The flexible bump structure provides a highly reliable connection.
超弾性体材料としては、弾性歪みが０．５％以上の金属
、例えばＣｕ−Ｚｎ−５ｎ、 Ａｕ−Ｃｕ−Ｚｎ、 Ａ
ｇ−Ｃｄ。Examples of superelastic materials include metals with an elastic strain of 0.5% or more, such as Cu-Zn-5n, Au-Cu-Zn, A
g-Cd.
Ａｕ−Ｃｄ、 Ｐｅ−Ｐｔ、 Ｐｅ−Ｐｄなどが用いら
れ、これらの合金を合金めっき浴により接続点に選択析
出させるものである。Au-Cd, Pe-Pt, Pe-Pd, etc. are used, and these alloys are selectively deposited at the connection points using an alloy plating bath.
このように形成した超弾性合金は、超弾性特性を向上さ
せるため、必要に応じて、加熱急冷等の熱処理を施して
もよい。The thus formed superelastic alloy may be subjected to heat treatment such as heating and quenching, if necessary, in order to improve its superelastic properties.
本発明では、超弾性合金のバンプ材料を、フォトリソグ
ラフィ（フォトリソ）及びめっき工程で高精度にかつ極
めて安価に形成できるため信頼性の高い半導体接続を得
ることができる。In the present invention, a superelastic alloy bump material can be formed with high precision and at an extremely low cost through photolithography and plating processes, so that highly reliable semiconductor connections can be obtained.
（実施例） 実施例１ 次に本発明を図面に示す実施例に基づいて説明する。(Example) Example 1 Next, the present invention will be explained based on embodiments shown in the drawings.
第１図は本発明の接続部の断面構造を示すもので６は銅
層、７は超弾性バンプ、８は金を示している。FIG. 1 shows a cross-sectional structure of a connecting portion according to the present invention, in which 6 indicates a copper layer, 7 indicates a superelastic bump, and 8 indicates gold.
この実施例では７の超弾性バンプを２の配線基板側に形
成したものでこの超弾性バンプ７と半導体素子１の電極
４をアライメントし収縮性樹脂５で固定接続したもので
ある。In this embodiment, 7 superelastic bumps are formed on the 2nd wiring board side, and the superelastic bumps 7 and the electrodes 4 of the semiconductor element 1 are aligned and fixedly connected using a shrinkable resin 5.
第２図は本実施例の工程を示すもので以下順に説明する
。まず配線が施された配線基板２に全面に銅Ｎ６を無電
解銅めっきで形成する。次にバンプ部分となるところの
み露出するようにフォトリソでめっきレジストを形成す
る。次に超弾性バンプ材料としてＣｕ−Ｚｎ−５ｎ（組
成比Ｃｕ ３４．７ｗｔ％Ｚｎ−３，０ｗｔ％Ｓｎ）
を銅層の露出したバンプ部分に電気めっきにより析出さ
せる。ここで用いた、銅合金めっき液組成を第１表に示
した。FIG. 2 shows the steps of this embodiment, which will be explained in order below. First, copper N6 is formed on the entire surface of the wiring board 2 on which wiring is provided by electroless copper plating. Next, a plating resist is formed by photolithography so that only the bump portion is exposed. Next, Cu-Zn-5n (composition ratio Cu 34.7wt%Zn-3,0wt%Sn) was used as a superelastic bump material.
is deposited by electroplating on the exposed bump portions of the copper layer. Table 1 shows the composition of the copper alloy plating solution used here.
第 １ 表
この合金めっきではＣｕ、 Ｚｎ、 Ｓｎの酸化電位が
著しく異なるためめっき装置は第３図に示すような分離
陽極型の装置を用いた。Table 1 In this alloy plating, since the oxidation potentials of Cu, Zn, and Sn are significantly different, a separate anode type plating apparatus as shown in FIG. 3 was used as the plating apparatus.
第３図において、９は銅陽極板、１０は銅陽極板、１１
は亜鉛陽極板、１２はめっき槽、１７はめっき液、１３
は各陽極電流を調整するための可変抵抗器、１４はそれ
ぞれの陽極の電流計、１５はそれぞれの陽極対陰極の電
圧計、１６は直流電源を示している。In Figure 3, 9 is a copper anode plate, 10 is a copper anode plate, 11
is a zinc anode plate, 12 is a plating tank, 17 is a plating solution, 13
14 is a variable resistor for adjusting each anode current, 14 is an ammeter for each anode, 15 is a voltmeter for each anode to cathode, and 16 is a DC power supply.
図に示すように３種の陽極金属をそれぞれ個別の回路を
作って、それぞれについて陽極電流及び陽極と陰極（被
めっき物）との電位差を調整することにより、めっき液
内のそれぞれの金属イオン濃度を一定に保つことができ
、また析出金属の組成も一定に保つことができる。As shown in the figure, by creating individual circuits for each of the three types of anode metals and adjusting the anode current and the potential difference between the anode and cathode (object to be plated) for each, the concentration of each metal ion in the plating solution can be adjusted. can be kept constant, and the composition of the deposited metal can also be kept constant.
以上のめっき液及びめっき装置を用いて超弾性バンプ７
を形成した後接触抵抗を下げることとエツチングレジス
トのために超弾性バンプ７の上に金めつき層８を施す、
その後めっきレジストを剥離し、塩化第２鉄又は過硫酸
アンモニウム溶液などでバンブ部以外の銅層６を除去す
る。Superelastic bump 7 was produced using the above plating solution and plating equipment.
After forming the superelastic bump 7, a gold plating layer 8 is applied on the superelastic bump 7 to lower the contact resistance and to resist etching.
Thereafter, the plating resist is peeled off, and the copper layer 6 other than the bump portions is removed using ferric chloride or ammonium persulfate solution.
このようなエツチング工程を必要とすることから、配線
基板２の導体は、予め金などの耐エツチング金属のコー
トを施しておく必要がある。Since such an etching step is required, the conductors of the wiring board 2 must be coated with an etching-resistant metal such as gold in advance.
このようにして完成した配線基板２の半導体素子搭載部
に収縮樹脂を印刷などによりコートし、半導体素子をア
ライメントし硬化させることにより接続を得るものであ
る。The semiconductor element mounting portion of the wiring board 2 thus completed is coated with shrinkable resin by printing or the like, and connections are obtained by aligning and curing the semiconductor elements.
又、接続手段としては、収縮樹脂の代わりに仮バネなど
の加圧方法を用いても良い。Further, as the connection means, a pressurizing method such as a temporary spring may be used instead of the shrinkable resin.
一方溶融接続を得る場合には、金めつき層８の代わりに
はんだめっきを行い半導体素子をアライメントした後、
リフロー炉ではんだを溶融させ接続させることもできる
。On the other hand, when obtaining a fusion connection, after performing solder plating instead of the gold plating layer 8 and aligning the semiconductor element,
Connections can also be made by melting solder in a reflow oven.
このような接続構造とすることにより本弾性体バンプは
、２％の弾性歪みを示し、０〜１５０°Ｃの温度サイク
ルを１０００回繰返しても電気的接触は維持された。With such a connection structure, the present elastic bump exhibited an elastic strain of 2%, and electrical contact was maintained even after 1000 temperature cycles from 0 to 150°C were repeated.
実施例２
第１の実施例では、超弾性バンプを配線基板２に形成し
たものを示したが、本実施例では半導体素子側にバンプ
を形成した例を示す。Example 2 In the first example, a superelastic bump was formed on the wiring board 2, but in this example, an example is shown in which the bump is formed on the semiconductor element side.
第４図は本発明の第２の実施例における接続部の断面構
造を示すもので半導体素子１上の電極４の表面にアルミ
ニウム層１８を形成し、その後チタン、白金、金７１１
９を形成し、この上に超弾性金属バンプ２０としてＦｅ
−２６ａｔ％Ｐｄを電気めっきにより選択的に形成し、
バンプ表面に金層８を形成して配線基板２の電極４とコ
ンタクトするものである。FIG. 4 shows a cross-sectional structure of a connecting portion in a second embodiment of the present invention, in which an aluminum layer 18 is formed on the surface of an electrode 4 on a semiconductor element 1, and then titanium, platinum, gold 711
9 is formed, and Fe is formed thereon as a superelastic metal bump 20.
-26 at% Pd is selectively formed by electroplating,
A gold layer 8 is formed on the bump surface to contact the electrode 4 of the wiring board 2.
第５図は詳細な工程フローを示したものでる。FIG. 5 shows a detailed process flow.
まず半導体素子１のバンプ電極部４以外の部分は予めパ
ッシベーション膜で保護しておき、半導体素子全面にア
ルミニウム蒸着膜１８を形成する。First, portions of the semiconductor element 1 other than the bump electrode portions 4 are previously protected with a passivation film, and an aluminum vapor deposition film 18 is formed over the entire surface of the semiconductor element.
このアルミニウム蒸着膜１８はめっき用の通電フィルム
として作用する。その後、フォトリソによりバンプ部を
露出させるようにレジスト膜を形成し、チタン、白金、
金層１９を蒸着する。この時の断面を第６図に示した。This aluminum vapor-deposited film 18 acts as a conductive film for plating. After that, a resist film is formed by photolithography to expose the bump part, and titanium, platinum,
A gold layer 19 is deposited. A cross section at this time is shown in FIG.
第６図において２１はパッシベーション膜、２２はレジ
スト膜を示している。In FIG. 6, 21 indicates a passivation film, and 22 indicates a resist film.
この後、有機溶剤中に浸漬しレジスト膜２２を溶解剥離
することによりバンプ部以外のチタン。Thereafter, the resist film 22 is dissolved and peeled off by immersion in an organic solvent, thereby removing titanium from areas other than the bump portions.
白金、金層を除去できる。これは一般にリフトオフ法と
よばれるものである。Platinum and gold layers can be removed. This is generally called the lift-off method.
次に第７図に示すようにバンプ部が露出するようにめっ
きレジスト２３を形成し電気めっきで鉄系超弾性バンプ
２０を形成する。鉄系超弾性バンプ（Ｆｅ−Ｐｄ系）の
めっき液組成を第２表に示した。Next, as shown in FIG. 7, a plating resist 23 is formed so that the bump portions are exposed, and iron-based superelastic bumps 20 are formed by electroplating. Table 2 shows the composition of the plating solution for iron-based superelastic bumps (Fe-Pd-based).
第２表
Ｆｅ −Ｐｄめっき液組成
めっき装置は第３図に示したものと基本的に同じであり
この場合は２つの陽極板（Ｆｅ、 Ｐｄ）としてめっき
した。Table 2 Fe--Pd plating solution composition The plating apparatus was basically the same as that shown in FIG. 3, and in this case two anode plates (Fe, Pd) were plated.
次に金めつき８を施し、めっきレジスト２３を剥離して
、アルミニウムエツチング液を用いてバンプ部以外のア
ルミニウム層１８をエツチングして完成となる。Next, gold plating 8 is applied, the plating resist 23 is peeled off, and the aluminum layer 18 other than the bump portions is etched using an aluminum etching solution to complete the process.
以下実施例１と同様の接続構造とすることができる。Hereinafter, the same connection structure as in the first embodiment can be used.
なお、本実施例においてもバンプ表面にはんだめっきを
施すことによりはんだでの溶融接続とすることができる
。In this embodiment as well, by applying solder plating to the surface of the bump, it is possible to achieve a fusion connection using solder.
このような構造とすることにより本弾性体バンプは１％
の弾性歪みを示し、０〜１５０°Ｃの温度サイクルを１
０００回繰り返しても電気的接触は維持された。With this structure, the elastic bump is 1%
It exhibits an elastic strain of
Electrical contact was maintained even after 000 repetitions.
（発明の効果）
以上のように本発明は、半導体素子接続バンプとして、
それぞれを接触させてバンプ自身の弾性変形を利用して
配線基板及び半導体素子の歪みに追従するバンプ構造を
電気めっきとフォトリソにより高精度でかつ安価に得る
ことができ、信顛性の高いフリップチップ接合が可能と
なった。(Effects of the Invention) As described above, the present invention provides a bump for connecting a semiconductor element.
A bump structure that follows the distortion of the wiring board and semiconductor element by making contact with each other and utilizing the elastic deformation of the bumps themselves can be obtained with high precision and at low cost by electroplating and photolithography, making it a highly reliable flip chip. It is now possible to join.
第１図は本発明の実施例１の超弾性バンプを配線基板側
に形成した半導体素子接続構造を示す説明図、第２図は
第１図の半導体素子接続構造を実現するための工程フロ
ー図、第３図はめっき装置の説明図、第４図は実施例２
として半導体素子側に超弾性バンプを形成した接続構造
を示す説明図、第５図は第４図の半導体素子接続構造を
実現するための工程フロー図、第６図及び第７図は実施
例２の工程を詳細に説明するためのプロセス断面図、第
８図〜第１０図は従来のはんだバンプにより接続された
半導体素子と配線基板の断面図で、第９図は温度変化に
より配線基板が膨張しバンプ、剪断歪みが導入された様
子を示し、第１０図ははんだバンプを圧力で接触させて
樹脂で固めた場合の半導体素子接続構造の断面を示す。
１・・・半導体素子、２・・・配線基板、３・・・はん
だバンプ、４・・・金属電極、５・・・樹脂、６・・・
銅めっき層、７・・・銅系超弾性バンプ、８・・・金層
、９・・・銀陽極板、１０・・・銅陽極板、１１・・・
亜鉛陽極板、１２・・・めっき槽、１３・・・可変抵抗
器、１４・・・電流針、１５・・・電圧計、１６・・・
直流電源、１７・・・めっき液、１８・・・アルミニウ
ム蒸着層、１９・・・チタン、白金、金層、２０・・・
鉄系超弾性バンプ、２１・・・パッシベーション膜、２
２・・・レジスト膜、２３・・・めっきレジ７’、ｌ−
，３３・・・金属バンプ。
特許出願人 新日本製鐵株式會社他１名第２図
第３図FIG. 1 is an explanatory diagram showing a semiconductor element connection structure in which a superelastic bump according to Example 1 of the present invention is formed on the wiring board side, and FIG. 2 is a process flow diagram for realizing the semiconductor element connection structure of FIG. 1. , FIG. 3 is an explanatory diagram of the plating apparatus, and FIG. 4 is Example 2.
5 is an explanatory diagram showing a connection structure in which superelastic bumps are formed on the semiconductor element side, FIG. 5 is a process flow diagram for realizing the semiconductor element connection structure of FIG. 4, and FIGS. 6 and 7 are illustrations of Example 2. Figures 8 to 10 are cross-sectional views of a semiconductor element and wiring board connected by conventional solder bumps, and Figure 9 is a process cross-sectional view to explain the process in detail. FIG. 10 shows a cross section of a semiconductor element connection structure in which solder bumps are brought into contact with pressure and hardened with resin. DESCRIPTION OF SYMBOLS 1... Semiconductor element, 2... Wiring board, 3... Solder bump, 4... Metal electrode, 5... Resin, 6...
Copper plating layer, 7... Copper-based superelastic bump, 8... Gold layer, 9... Silver anode plate, 10... Copper anode plate, 11...
Zinc anode plate, 12... Plating bath, 13... Variable resistor, 14... Current needle, 15... Voltmeter, 16...
DC power supply, 17... Plating solution, 18... Aluminum vapor deposition layer, 19... Titanium, platinum, gold layer, 20...
Iron-based superelastic bump, 21...passivation film, 2
2... Resist film, 23... Plating resist 7', l-
, 33...metal bump. Patent applicant Nippon Steel Corporation and one other person Figure 2 Figure 3
Claims (1)
続構造であって、前記超弾性体材料を電気めっきにて形
成したことを特徴とする半導体素子接続構造。1. A semiconductor element connection structure that electrically connects semiconductor elements through a superelastic material, characterized in that the superelastic material is formed by electroplating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1044256A JP2709499B2 (en) | 1989-02-25 | 1989-02-25 | Semiconductor element connection structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1044256A JP2709499B2 (en) | 1989-02-25 | 1989-02-25 | Semiconductor element connection structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02224256A true JPH02224256A (en) | 1990-09-06 |
| JP2709499B2 JP2709499B2 (en) | 1998-02-04 |
Family
ID=12686443
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1044256A Expired - Fee Related JP2709499B2 (en) | 1989-02-25 | 1989-02-25 | Semiconductor element connection structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2709499B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5784779A (en) * | 1995-05-20 | 1998-07-28 | Robert Bosch Gmbh | Method for joining an electrical connection of a non-packaged IC component with a conductive strip on a substrate |
| JP2011060926A (en) * | 2009-09-09 | 2011-03-24 | Hitachi Ltd | Semiconductor apparatus |
-
1989
- 1989-02-25 JP JP1044256A patent/JP2709499B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5784779A (en) * | 1995-05-20 | 1998-07-28 | Robert Bosch Gmbh | Method for joining an electrical connection of a non-packaged IC component with a conductive strip on a substrate |
| JP2011060926A (en) * | 2009-09-09 | 2011-03-24 | Hitachi Ltd | Semiconductor apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2709499B2 (en) | 1998-02-04 |
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