JPH02229443A - Semiconductor element connection - Google Patents
Semiconductor element connectionInfo
- Publication number
- JPH02229443A JPH02229443A JP5065189A JP5065189A JPH02229443A JP H02229443 A JPH02229443 A JP H02229443A JP 5065189 A JP5065189 A JP 5065189A JP 5065189 A JP5065189 A JP 5065189A JP H02229443 A JPH02229443 A JP H02229443A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- superelastic
- insulating substrate
- solder
- connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 15
- 229910000679 solder Inorganic materials 0.000 abstract description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 4
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 abstract description 4
- 239000004020 conductor Substances 0.000 abstract description 4
- 229910052802 copper Inorganic materials 0.000 abstract description 4
- 239000010949 copper Substances 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 4
- 229910045601 alloy Inorganic materials 0.000 abstract description 3
- 239000000956 alloy Substances 0.000 abstract description 3
- 239000003984 copper intrauterine device Substances 0.000 abstract description 3
- 238000009713 electroplating Methods 0.000 abstract description 3
- 229910001870 ammonium persulfate Inorganic materials 0.000 abstract description 2
- 239000002184 metal Substances 0.000 description 14
- 229910052751 metal Inorganic materials 0.000 description 14
- 238000007747 plating Methods 0.000 description 7
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 2
- 229910017518 Cu Zn Inorganic materials 0.000 description 1
- 229910017755 Cu-Sn Inorganic materials 0.000 description 1
- 229910017752 Cu-Zn Inorganic materials 0.000 description 1
- 229910017927 Cu—Sn Inorganic materials 0.000 description 1
- 229910017943 Cu—Zn Inorganic materials 0.000 description 1
- 229910004337 Ti-Ni Inorganic materials 0.000 description 1
- 229910011209 Ti—Ni Inorganic materials 0.000 description 1
- 229910007609 Zn—S Inorganic materials 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- KHYBPSFKEHXSLX-UHFFFAOYSA-N iminotitanium Chemical compound [Ti]=N KHYBPSFKEHXSLX-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3473—Plating of solder
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体素子の接続方法に関するものである。[Detailed description of the invention] (Industrial application field) The present invention relates to a method for connecting semiconductor elements.
（従来の技術）
従来の半導体素子のフリップチップ接続の概略構造を第
３図に示す。図中の１は半導体素子，２は配線基板，３
ははんだバンプ，４は半導体素子ｌと配線基板２のそれ
ぞれに設けられた電極であり、Ａ−ｘは半導体素子の中
心を示している。(Prior Art) FIG. 3 shows a schematic structure of a conventional flip-chip connection of semiconductor elements. In the figure, 1 is a semiconductor element, 2 is a wiring board, and 3 is a semiconductor element.
1 is a solder bump, 4 is an electrode provided on each of the semiconductor element 1 and the wiring board 2, and A-x indicates the center of the semiconductor element.
フリップチップ接続は、半導体素子１と配線基板２の電
極４の電気的接続を、はんだバンプ３を加熱溶融する一
括接続で行えるので、ワイヤボンディング法に比べて作
業性が優れている。又、ワイヤボンディング法及びＴＡ
Ｂ （Ｔａｐｅ ＡｕｔｏｍａｔｅｄＢｏｎｄｉｎｇ）
法のように電極配置が半導体素子の周辺に限定されない
ので、大幅に接続端子数を増大できるという特徴をもっ
ている。Flip-chip bonding is superior in workability to the wire bonding method because the electrical connection between the semiconductor element 1 and the electrodes 4 of the wiring board 2 can be made in one batch by heating and melting the solder bumps 3. In addition, wire bonding method and TA
B (Tape Automated Bonding)
Since the electrode arrangement is not limited to the periphery of the semiconductor element as in the method, it has the feature that the number of connection terminals can be greatly increased.
しかしながら、この接続構造では第４図に示すように、
温度変化が生じた場合半導体素子１と配線基板２との熱
膨張係数の差による寸法ずれＢが発生し、はんだバンプ
３に剪断歪みを生じ接続信顧性が低下する。However, with this connection structure, as shown in Figure 4,
When a temperature change occurs, a dimensional deviation B occurs due to the difference in thermal expansion coefficients between the semiconductor element 1 and the wiring board 2, causing shear strain in the solder bumps 3 and reducing connection reliability.
剪断歪みは、はんだバンプ３と半導体素子１との中心距
離の増加とともに増大するため、はんだバンプ３の許容
しうる剪断歪み量からはんだバンプ３を配置できる領域
が制限され、多端子化ならびに大面積の半導体素子への
適用が困難であった。Since shear strain increases as the distance between the centers of the solder bumps 3 and the semiconductor element 1 increases, the area in which the solder bumps 3 can be placed is limited due to the amount of shear strain that the solder bumps 3 can tolerate. It has been difficult to apply this method to semiconductor devices.
このはんだバンプの剪断歪みを低減させる手段として、
半導体素子と熱膨張係数の近い配線基板材料を用いる方
法が考えられるが、配線基板材料が制限されてしまうと
いう欠点がある。As a means to reduce the shear strain of solder bumps,
A possible method is to use a wiring board material with a coefficient of thermal expansion close to that of the semiconductor element, but this method has the disadvantage that the wiring board material is limited.
一方、ポリイミドフィルムで支持したはんだバンプを重
ねて多段バンプを形成し、剪断歪みを低減する方法（特
開昭６２−２９３７３０号公報）が提案されている。On the other hand, a method has been proposed (Japanese Unexamined Patent Publication No. 62-293730) in which shearing strain is reduced by stacking solder bumps supported by polyimide films to form multistage bumps.
しかしながら、はんだバンプを積み重ねるため、必要部
材の増加、接続工数の増加に伴う価格上昇という欠点が
ある。However, since the solder bumps are stacked, there is a drawback that the number of required members increases and the number of connection steps increases, resulting in an increase in price.
又、第５図は金属バンプを圧力で当接させて電気的接続
を得る半導体素子接続構造である。第５図において、半
導体素子ｌと配線基板２のそれぞれの電極４上には金属
バンプ１３が形成されている。この金属バンプ１３には
収縮性樹脂５の硬化時の収縮力により圧力が加わり、金
属バンプ１３同士が機械的に接触し電気的接続が得られ
る。Further, FIG. 5 shows a semiconductor element connection structure in which electrical connection is obtained by bringing metal bumps into contact with each other under pressure. In FIG. 5, metal bumps 13 are formed on the electrodes 4 of the semiconductor element 1 and the wiring board 2, respectively. Pressure is applied to the metal bumps 13 by the shrinkage force of the shrinkable resin 5 during curing, and the metal bumps 13 come into mechanical contact with each other to establish electrical connection.
しかしながら、この接続構造では金属バンプ１３の高さ
がバラックと電気的接続が得られない箇所が往ずる。又
、収縮性樹脂５の熱膨張係数は金属バンプに比べて大き
いため、温度変化が生じると圧力が弱まり、金属バンブ
の接触が不安定になるので接続信転性に欠けるという問
題点があった。However, in this connection structure, the height of the metal bump 13 often makes it impossible to establish electrical connection with the barracks. Furthermore, since the coefficient of thermal expansion of the shrinkable resin 5 is larger than that of the metal bumps, when a temperature change occurs, the pressure weakens and the contact between the metal bumps becomes unstable, resulting in a lack of connection reliability. .
（発明が解決しようとする課題）
本発明では、上記に述べた半導体素子と配線基板の間に
発生する大きな剪断歪み，バンプ高さのバラツキ及び収
縮性樹脂との熱膨張係数の差による圧力変動に対して電
気的接続の信頬性が高く、しかも微細接続が可能な安価
な半導体素子接続方法を提供するものである。(Problems to be Solved by the Invention) In the present invention, pressure fluctuations due to the large shear strain that occurs between the semiconductor element and the wiring board, variations in bump height, and the difference in thermal expansion coefficient with the shrinkable resin are solved. The present invention provides an inexpensive semiconductor element connection method that provides high reliability of electrical connections and allows fine connections.
本発明は、半導体素子と配線基板とを電気的に接続する
方法であって、前記半導体素子と配線基板との間に超弾
性材料でスルーホールを形成した絶縁基板を介在させる
ことを特徴とする半導体素子接続方法を要旨とするもの
である。The present invention is a method for electrically connecting a semiconductor element and a wiring board, characterized in that an insulating substrate having through holes formed with a superelastic material is interposed between the semiconductor element and the wiring board. The gist of this article is a semiconductor element connection method.
本発明では、前述の課題を解決するために、超弾性材料
を介在させた半導体素子実装構造とし、絶縁基板に接続
ピッチと同間隔に穴をあけ超弾性金属でスルーホール構
造を形成し、半導体素子と配線基板の間にアライメント
し、はんだ又は外部からの加圧で接続を得る方法である
。In order to solve the above-mentioned problems, the present invention has a semiconductor element mounting structure with a superelastic material interposed therebetween, holes are made in an insulating substrate at the same intervals as the connection pitch, and a through-hole structure is formed with a superelastic metal. This method aligns the element and the wiring board and establishes a connection using solder or external pressure.
超弾性材料としては、弾性歪みが０． ５％以上の金属
が望ましい。As a superelastic material, the elastic strain is 0. A metal content of 5% or more is desirable.
この超弾性材料には、例えばＴｉ −Ｎｉ， Ｆｅ−Ｐ
ｔ，Ｐｅ Ｐｄ＋ Ｍｎ Ｃｕ， Ｉｎ Ｔｊ
ｌＮｓ Ｎ＋ Ａｕ ＣｄＩＡｇ−Ｃｄ， Ａｕ−
Ｃｕ−Ｚｎ＋ Ｃｕ−Ｚｎ−１’Ｊ， Ｃｕ−Ｚｎ−Ｓ
ｎ，Ｃｕ−Ａ７−Ｎｉ， Ｃｕ−Ｓｎなどが用いられ、
これらの金属をめっきによるか或いはスバッタなどによ
りスルーホールを形成する。This superelastic material includes, for example, Ti-Ni, Fe-P
t, Pe Pd+ Mn Cu, In Tj
lNs N+ Au CdIAg-Cd, Au-
Cu-Zn+ Cu-Zn-1'J, Cu-Zn-S
n, Cu-A7-Ni, Cu-Sn, etc. are used,
Through holes are formed using these metals by plating or sputtering.
このようにして形成した超弾性金属は、超弾性特性を向
上させるために、必要に応じて加熱冷却等の熱処理を施
してもよい。The superelastic metal thus formed may be subjected to heat treatment such as heating and cooling, if necessary, in order to improve its superelastic properties.
本発明に使用できる超弾性合金の種類と組成を第１表に
例示した。Table 1 shows examples of types and compositions of superelastic alloys that can be used in the present invention.
第 １ 表
本発明では、超弾性材料で形成したスルーホール付絶縁
基板を接続媒体として使用することにより、高精度、低
価格でかつ高信鎖性の半導体素子接続を得ることができ
る。Table 1 In the present invention, by using an insulating substrate with through holes made of a superelastic material as a connection medium, it is possible to obtain semiconductor element connections with high precision, low cost, and high reliability.
（実施例） 次に本発明を図面に示す実施例に基づいて説明する。(Example) Next, the present invention will be explained based on embodiments shown in the drawings.
第１図は本発明の接続部の断面構造を示すもので、６は
絶縁基板，例えばポリイミドフィルム，７は銅めっき層
，８は超弾性スルーホール．９ははんだを示している。FIG. 1 shows the cross-sectional structure of the connection part of the present invention, in which 6 is an insulating substrate, such as a polyimide film, 7 is a copper plating layer, and 8 is a superelastic through hole. 9 indicates solder.
第１図において半導体素子１の電極４及び配線基板２の
電極４と同じ位置になるように絶縁基板６に穴あけ加工
し、超弾性金属８でスルーホール加工し、半導体素子１
と配線基板２との間にアライメントし両電極が電気的接
合が得られるようにはんだ付けしたものである。In FIG. 1, holes are drilled in the insulating substrate 6 so as to be at the same positions as the electrodes 4 of the semiconductor element 1 and the electrodes 4 of the wiring board 2, and the through holes are processed with superelastic metal 8.
and the wiring board 2, and both electrodes are soldered to achieve electrical connection.
第２図（ａ）〜（ｅ）を用いて超弾性スルーホール付絶
縁基板の作成手順を説明する。The procedure for producing an insulating substrate with superelastic through holes will be explained using FIGS. 2(a) to 2(e).
まず、絶縁基板６に微少ドリル又はエッチングにより穴
あけを行う（第２図（ａ））。次に絶縁基仮６全面に無
電解銅めっき７を形成する（第２図ら））。First, holes are made in the insulating substrate 6 by micro-drilling or etching (FIG. 2(a)). Next, electroless copper plating 7 is formed on the entire surface of the temporary insulating base 6 (FIG. 2 et al.).
次に導体以外の部分にめっきレジスト１０をフォトリソ
で形成する（第２図（Ｃ））。無電解めっきが露出した
部分に超弾性合金８としてＣｕ−３４．７ｗｔχＺｎ−
３．ＯｗｔχＳｎを電気めっきにて形成する。次に接合
材料としてはんだ９を電気めっきする（第２図（ｄ））
。Next, a plating resist 10 is formed on the portion other than the conductor by photolithography (FIG. 2(C)). Cu-34.7wtχZn- was applied as superelastic alloy 8 to the exposed part of electroless plating.
3. OwtχSn is formed by electroplating. Next, electroplating solder 9 as a bonding material (Fig. 2(d))
.
次にめっきレジスト１０を除去し、はんだ９をエッチン
グレジストした後、過硫酸アンモニウム溶液などで導体
部以外の無電解めっき銅７をエッチングする（第６図（
ｅ））。Next, after removing the plating resist 10 and applying an etching resist to the solder 9, the electroless plated copper 7 other than the conductor part is etched using an ammonium persulfate solution (see Fig. 6).
e)).
以上の工程で完成した超弾性スルーホール付絶縁基板を
半導体素子１と配線基板２との間で接続電極４とアライ
メントしリフロー炉で加熱することにより両電極をはん
だ接合する。The insulating substrate with superelastic through holes completed in the above steps is aligned with the connecting electrode 4 between the semiconductor element 1 and the wiring board 2, and the two electrodes are soldered together by heating in a reflow oven.
このようにして得られた実装構造は温度変化による配線
基板一半導体素子の熱膨張の差による熱歪みに対しても
スルーホールを形成した超弾性金属が２％の弾性歪みを
有することにより十分追従するため極めて高い信顧性が
得られた。The mounting structure obtained in this way can sufficiently cope with thermal distortion caused by the difference in thermal expansion between the wiring board and the semiconductor element due to temperature changes, since the superelastic metal in which the through holes are formed has an elastic distortion of 2%. As a result, we have achieved extremely high credibility.
（発明の効果）
本発明に従い、超弾性材料を半導体素子における熱歪み
を受ける部分に使用することにより、繰り返しの歪みに
対しても弾性範囲で変形を繰り返すことで、破断を防止
することを狙ったものであり、外部歪みに柔軟に追従す
るバンプ構造とすることができるので、信頬性の高い半
導体素子接続構造が得られる。(Effects of the Invention) According to the present invention, by using a superelastic material in a part of a semiconductor element that is subject to thermal strain, it is possible to prevent breakage by repeatedly deforming within the elastic range even under repeated strain. Since it is possible to form a bump structure that flexibly follows external distortion, a highly reliable semiconductor element connection structure can be obtained.
第１図は本発明の実施例を示すもので、超弾性材料でス
ルーホールを形成した絶縁基板を接合媒体とした接続構
造を示している。
．．第２図は本発明の実施例においてスルーホールを形
成する工程を示したものである。
第３図〜第５図は従来のはんだバンプにより接続された
半導体素子と配線基板の断面図で、第４図は温度変化に
より配線基板が膨張しバンプに剪断歪みが導入された様
子を示し、第５図ははんだバンブを圧力で接触させて樹
脂で固定した場合の半導体素子接続構造を示す断面図で
ある。
１・・・半導体素子、２・・・配線基板、３・・・はん
だバンブ、４・・・金属電極、５・・・樹脂、６・・・
絶縁基板、７・・・無電解銅めっき層、８・・・超弾性
体材料によるスルーホール、９・・・はんだ、１０・・
・めっきレジスト。
第２図
第３ｍｌ
第５図FIG. 1 shows an embodiment of the present invention, and shows a connection structure using an insulating substrate with through holes formed with a superelastic material as a bonding medium. ．． ．． FIG. 2 shows the process of forming through holes in an embodiment of the present invention. Figures 3 to 5 are cross-sectional views of a semiconductor element and a wiring board connected by conventional solder bumps, and Figure 4 shows how the wiring board expands due to temperature changes and shear strain is introduced into the bumps. FIG. 5 is a sectional view showing a semiconductor element connection structure in which solder bumps are brought into contact with pressure and fixed with resin. DESCRIPTION OF SYMBOLS 1... Semiconductor element, 2... Wiring board, 3... Solder bump, 4... Metal electrode, 5... Resin, 6...
Insulating substrate, 7... Electroless copper plating layer, 8... Through hole made of superelastic material, 9... Solder, 10...
・Plating resist. Figure 2 3ml Figure 5
Claims (1)
て、前記半導体素子と配線基板との間に超弾性材料でス
ルーホールを形成した絶縁基板を介在させることを特徴
とする半導体素子接続方法。A method for electrically connecting a semiconductor element and a wiring board, the method comprising interposing an insulating substrate in which through holes are formed with a superelastic material between the semiconductor element and the wiring board. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1050651A JP2709501B2 (en) | 1989-03-02 | 1989-03-02 | Semiconductor element connection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1050651A JP2709501B2 (en) | 1989-03-02 | 1989-03-02 | Semiconductor element connection method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02229443A true JPH02229443A (en) | 1990-09-12 |
| JP2709501B2 JP2709501B2 (en) | 1998-02-04 |
Family
ID=12864844
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1050651A Expired - Fee Related JP2709501B2 (en) | 1989-03-02 | 1989-03-02 | Semiconductor element connection method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2709501B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5683942A (en) * | 1994-05-25 | 1997-11-04 | Nec Corporation | Method for manufacturing bump leaded film carrier type semiconductor device |
| US5952717A (en) * | 1994-12-29 | 1999-09-14 | Sony Corporation | Semiconductor device and method for producing the same |
-
1989
- 1989-03-02 JP JP1050651A patent/JP2709501B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5683942A (en) * | 1994-05-25 | 1997-11-04 | Nec Corporation | Method for manufacturing bump leaded film carrier type semiconductor device |
| US5905303A (en) * | 1994-05-25 | 1999-05-18 | Nec Corporation | Method for manufacturing bump leaded film carrier type semiconductor device |
| US5952717A (en) * | 1994-12-29 | 1999-09-14 | Sony Corporation | Semiconductor device and method for producing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2709501B2 (en) | 1998-02-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR910002454B1 (en) | Film carrier and bonding method using the film carrier | |
| US6224392B1 (en) | Compliant high-density land grid array (LGA) connector and method of manufacture | |
| US4842662A (en) | Process for bonding integrated circuit components | |
| CA2115553C (en) | Plated compliant lead | |
| JP2500996B2 (en) | How to make electronic interconnections | |
| JP2892505B2 (en) | Mounting electronic components on circuit boards | |
| EP0473929B1 (en) | Method of forming a thin film electronic device | |
| KR100201036B1 (en) | Bump, semiconductor chip and package having the bump, and mounting method and semiconductor apparatus | |
| CN85108637A (en) | Electronic circuit and manufacture method thereof | |
| JPH02229443A (en) | Semiconductor element connection | |
| JP3349166B2 (en) | Circuit board | |
| JPS61196546A (en) | Film carrier integrated circuit and manufacture thereof | |
| JP3049948B2 (en) | Package manufacturing method | |
| JP2737545B2 (en) | Film carrier tape for semiconductor device and method of manufacturing the same | |
| JPH02237129A (en) | Connection structure of semiconductor element | |
| US6153518A (en) | Method of making chip size package substrate | |
| JP2570626B2 (en) | Board connection structure and connection method | |
| JPS6366958A (en) | Lead frame for semiconductor and manufacture thereof | |
| JPH0572751B2 (en) | ||
| JP2770040B2 (en) | Bump forming method and semiconductor element connecting method | |
| JPH0685153A (en) | Surface mount type electronic component | |
| JPH02137240A (en) | Connection structure of semiconductor element | |
| JP2819321B2 (en) | Electronic component mounting substrate and method of manufacturing the electronic component mounting substrate | |
| JPH088352A (en) | Semiconductor device and manufacture of semiconductor mounting board | |
| JPH02224256A (en) | Semiconductor element connection structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081024 Year of fee payment: 11 |
|
| LAPS | Cancellation because of no payment of annual fees |