JPH02223928A - Defect relieving method - Google Patents
Defect relieving methodInfo
- Publication number
- JPH02223928A JPH02223928A JP1042992A JP4299289A JPH02223928A JP H02223928 A JPH02223928 A JP H02223928A JP 1042992 A JP1042992 A JP 1042992A JP 4299289 A JP4299289 A JP 4299289A JP H02223928 A JPH02223928 A JP H02223928A
- Authority
- JP
- Japan
- Prior art keywords
- conductive film
- film
- source
- contact
- oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007547 defect Effects 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 title description 8
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000010408 film Substances 0.000 claims description 46
- 238000009792 diffusion process Methods 0.000 claims description 18
- 239000010409 thin film Substances 0.000 claims description 11
- 239000011159 matrix material Substances 0.000 claims description 3
- 230000002950 deficient Effects 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 3
- 239000011229 interlayer Substances 0.000 abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 abstract description 3
- 239000001301 oxygen Substances 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 230000002159 abnormal effect Effects 0.000 abstract description 2
- 238000011109 contamination Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052593 corundum Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 230000000694 effects Effects 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910003437 indium oxide Inorganic materials 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- 229910001887 tin oxide Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 210000004209 hair Anatomy 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は液晶表示装置に用いられるアクティブマトリク
ス基板及び半導体素子の欠陥救済方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an active matrix substrate used in a liquid crystal display device and a method for relieving defects in semiconductor elements.
近年、絶縁基板」−に薄膜ｉ・ランジスタ（以下ＴＰＴ
と略す）を形成する研究が活発に行なわれている。この
技術はガラス等の安価な絶縁基板を用いて薄形デイスプ
レィを実現するアクティブマトリックスパネル等の応用
で重要な技術である。この応用において９表示パネルの
表示部電極として透明電極を用い、対向透明電極間に液
晶を封入することにより透過型表示パネル構成がとれる
。In recent years, thin film i-transistors (hereinafter referred to as TPT) have been developed on insulating substrates.
Research is being actively conducted to form the This technology is important for applications such as active matrix panels that realize thin displays using inexpensive insulating substrates such as glass. In this application, a transmissive display panel structure can be obtained by using a transparent electrode as the display electrode of the 9 display panel and sealing liquid crystal between the opposing transparent electrodes.
第２図（ａ）は透過型表示パネルを構成するＴＰＴの外
観図を示す。図面に於いて２０１はソースライン、２０
２はゲートライン、２０３はゲート電極、２０４は多結
晶シリコン薄膜、２ｏ５はソースコンタクト、２０６は
ドレインコンタクト。FIG. 2(a) shows an external view of a TPT constituting a transmissive display panel. In the drawing, 201 is the source line, 20
2 is a gate line, 203 is a gate electrode, 204 is a polycrystalline silicon thin film, 2o5 is a source contact, and 206 is a drain contact.
２０７は透明導電膜であるところの液晶駆動電極である
。ソースライン及びゲートラインには画素外に外部ドラ
イブ回路及び電機特性測定装置との電気的接線を取る為
の端子が形成されている。207 is a liquid crystal drive electrode which is a transparent conductive film. Terminals are formed on the source line and the gate line outside the pixel to connect them to an external drive circuit and an electrical property measuring device.
次に、第２図（ａ）の破線部分の断面図を第２図（ｂ）
に示す。図面に於いて２１１は絶縁性基板、２１２は多
結晶シリコン内に不純物をドープしたソース拡散領域、
２１３も２１２と同様に形成したドレイン拡散領域、２
１４はゲート酸化膜。Next, a cross-sectional view of the broken line part in FIG. 2(a) is shown in FIG. 2(b).
Shown below. In the drawing, 211 is an insulating substrate, 212 is a source diffusion region doped with impurities in polycrystalline silicon,
213 also has a drain diffusion region formed in the same manner as 212;
14 is a gate oxide film.
２１５はゲート電極、２１６は眉間絶縁膜、２１７はソ
ースティン、２１８は液晶駆動電極である。215 is a gate electrode, 216 is an insulating film between the eyebrows, 217 is a saucepan, and 218 is a liquid crystal drive electrode.
前記ＴＰＴのゲート電極とソースライン又はソース拡散
領域は膜厚が約１ミクロンメートルの眉間絶縁膜及び膜
厚が数１０から数１００ミクロンメートルのゲート酸化
膜によって絶縁されている為にゲート電極とソース拡散
領域間のリークが発生し易い。The gate electrode and source line or source diffusion region of the TPT are insulated by a glabella insulating film with a thickness of about 1 micron and a gate oxide film with a thickness of several tens to hundreds of microns. Leakage between diffusion regions is likely to occur.
例えばプロセスに於いて、異物（ゴミ、ケバ等）がＴＰ
Ｔとなる部分の基板上に更にＴＰＴの形成中に多結晶シ
リコン上、ゲート酸化膜上等に付着すると、多結晶シリ
コンドゲート電極間が短絡したリークが発生する。また
、こすり偏によっても同様である。特にゲート酸化膜上
に付いた場合はほとんどの場合大変尾おきなリークとな
る。また。For example, during the process, foreign matter (dust, fluff, etc.)
If TPT is further deposited on the polycrystalline silicon, gate oxide film, etc. on the substrate at the TPT portion, leakage occurs due to a short circuit between the polycrystalline silicon gate electrodes. The same applies to uneven rubbing. In particular, if it gets on the gate oxide film, it will almost always result in a very large leak. Also.
外観上判断しにくいような微少な異物や静電気によるゲ
ート酸化膜破壊によってもリークが発生することがある
。Leakage may also occur due to damage to the gate oxide film due to minute foreign matter or static electricity that is difficult to determine from the outside.
前記の原因等によりソース拡散領域と、ゲート電極との
間にリークが発生すると、それに電気的接続する。ソー
スライン及びゲートライン間のリークとなる。該ライン
間のリークによってゲートライン信号とソースライン信
号が混合し９表示パネルを点燈するとソース・ゲートラ
インの欠陥として外観で確認される。また、ソース拡散
領域とドレイン拡散領域との間にリークが発生するとリ
ークが発生した部分のＴＰＴに接続される画素は欠陥と
して外観で確認される。When leakage occurs between the source diffusion region and the gate electrode due to the above-mentioned causes, an electrical connection is made thereto. This results in leakage between the source line and gate line. Due to the leakage between the lines, the gate line signal and the source line signal are mixed, and when the display panel 9 is turned on, it is visually confirmed as a defect in the source/gate line. Further, when leakage occurs between the source diffusion region and the drain diffusion region, the pixel connected to the TPT in the portion where the leakage occurs is visually confirmed as a defect.
従来の前記の欠陥修正方法を第２図に従って説明する。The conventional defect repair method described above will be explained with reference to FIG.
第２図（ａ）はソース拡散領域、ゲート電極間にリーク
を有するＴＰＴであり修正前である。FIG. 2(a) shows a TPT with leakage between the source diffusion region and the gate electrode, and is before correction.
（ｃ）、（ｄ）が修正後である。（Ｃ）ではレーザリペ
ア装置等を用いることにより非接触でソース拡散領域と
ソースライン間を接続する多結晶シリコン層を切断（溶
断）する。（ｄ）では同様な方法によりゲート電極とゲ
ートライン間を接続する導電薄膜を切断する等の欠陥修
正方法が従来用いられていた。なお、この種の欠陥修正
方法として関連するものには例えば特開昭５８−１７１
８４５ 、号が挙げられる。(c) and (d) are after correction. In (C), the polycrystalline silicon layer connecting the source diffusion region and the source line is cut (fused) in a non-contact manner using a laser repair device or the like. In the case of (d), a defect repair method has conventionally been used in which a similar method is used to cut the conductive thin film connecting the gate electrode and the gate line. Note that related defect repair methods of this type include, for example, Japanese Patent Application Laid-Open No. 58-171.
845, No. 845.
上記従来技術は欠陥が発生した場合、レーザ等によりソ
ース拡散領域とソースライン間の多結晶シリコン層又は
ゲート電極とゲートライン電極間を接続する導電７ａ膜
を溶断した半導体膜や金属薄膜等が液晶を汚染する。新
たな部分に短絡状態を発生させる等の問題があった。In the above conventional technology, when a defect occurs, the polycrystalline silicon layer between the source diffusion region and the source line or the conductive 7a film connecting between the gate electrode and the gate line electrode is fused using a laser or the like, and the semiconductor film, metal thin film, etc. contaminate. There were problems such as short circuits occurring in new parts.
本発明はかかる問題を除去したもので、その目的は欠陥
部分以外の他の部分に影響を及ぼすに欠陥を修正するこ
とにある。The present invention eliminates this problem, and its purpose is to correct defects that affect other parts than the defective part.
上記目的を達成するために欠陥が発生した場合に、電気
的に切断したい部分は金属膜と酸化物系導電膜とのコン
タクト又は半導体膜と酸化物系導電膜とのコンタクト領
域を形成した構造とし。In order to achieve the above purpose, if a defect occurs, the part to be electrically disconnected should have a structure in which a contact area between a metal film and an oxide-based conductive film or a contact region between a semiconductor film and an oxide-based conductive film is formed. .
欠陥が発生した場合に、レーザ光等により部分的に熱を
加えられるようにした。If a defect occurs, heat can be applied locally using a laser beam or the like.
酸化物系導電膜はシリコン等の半導体膜やアルミニウム
等の金属膜と接触し、熱が加えられると接触界面にＳ
ｉ Ｏ，やＡＱ、０３等の酸化物系絶縁膜を形成する。Oxide-based conductive films come into contact with semiconductor films such as silicon or metal films such as aluminum, and when heat is applied, S is generated at the contact interface.
An oxide-based insulating film such as iO, AQ, 03, etc. is formed.
それによって、欠陥部分は電気的に絶縁されるようにな
るので、ｆ＃、気的短絡した欠陥は修正される。また１
本発明によれば、コンタクト領域に酸化物糸導、ｆｆ１
ｌｌｌの酸素が反応する程度の３００〜５００’Ｃ程の
熱を部分的に加えるだけなので、他の領域への汚染等の
影響を与えることがない。Thereby, the defective part becomes electrically insulated, so that the f#, electrically shorted defect is corrected. Also 1
According to the invention, an oxide thread conductor, ff1, is provided in the contact area.
Since heat of about 300 to 500'C, which is enough to react with 1000 ml of oxygen, is only partially applied, there is no effect of contamination on other areas.
以下２本発明の一実施例を第１図、第３図。 The following two embodiments of the present invention are shown in FIGS. 1 and 3.
第４図により説明する６
図１（ｂ）はソースコンタクト領域１１５．ドレインコ
ンタクト領域１１６間にリークを有する薄膜トランジス
タの平面図である。ソースコンタクトｌ［１１５とドレ
インコンタクト領域１１６が短絡により画素駆動用透明
導電１１．１１７に信号電圧が常時印加されるようにな
った場合９表示パネルとして欠陥が発生（）た画素は常
時白点対の欠陥として表示される。この場合画素駆動用
透明導電膜１１７をドレイン領域１１６より絶絶すれば
欠陥ＴＦＴ部の画素は常時異点対の欠陥となりパネルと
しては欠陥が目立たなくなる。この場合の透明導電膜１
１７の絶縁方法を図１ （ａ）により説明する。図１（
ａ）は図１ （ｂ）のドレインコンタクト領１１６の断
面拡散図である。絶縁性基板１にシリコン等の半導体膜
やアルミニウム等の金属導電膜２を形成し、この上に層
間絶縁膜６形成後、所定のパターンにコンタク１〜ホー
ルを開［］する。その後、酸化インジウム、酸化スズ、
インジウム、スズ酸化物等の酸化物系導電膜８を堆積す
ると、導電膜２と酸化物系導電膜８は電気的に導電状態
どなる。しかし、導電膜２ど酸化物系導電膜８の接触領
域９．１１６にレーザ光等により部分的に熱を加えると
、酸化物系導電膜８の酸素が導電膜２中に拡散し、接触
界面９にＳｉ、０２やＡＱ２０．等の酸化物系絶縁膜９
を形成し、導電膜２と酸化物系導電膜８を絶縁する。こ
こで、導電膜２はドレインコンタクｌ−領域１１６の多
結晶シリコン簿膜３１４に対応し、酸化物系導電膜８は
画素駆動用透明導電膜３．１７に対応する。This will be explained with reference to FIG. 4. FIG. 1(b) shows the source contact region 115. FIG. 3 is a plan view of a thin film transistor having leakage between drain contact regions 116; If a signal voltage is constantly applied to the pixel driving transparent conductor 11.117 due to a short circuit between the source contact l[115 and the drain contact region 116]9, the pixel with a defect in the display panel will always have a white spot. displayed as a defect. In this case, if the transparent conductive film 117 for pixel driving is removed from the drain region 116, the pixels in the defective TFT section will always be defective as a pair of abnormal points, and the defect will not be noticeable as a panel. Transparent conductive film 1 in this case
The insulation method of No. 17 will be explained with reference to FIG. 1(a). Figure 1 (
1(a) is a cross-sectional diffusion view of the drain contact region 116 of FIG. 1(b). A semiconductor film such as silicon or a metal conductive film 2 such as aluminum is formed on an insulating substrate 1, and after an interlayer insulating film 6 is formed thereon, contacts 1 to holes are opened in a predetermined pattern. After that, indium oxide, tin oxide,
When the oxide-based conductive film 8 such as indium or tin oxide is deposited, the conductive film 2 and the oxide-based conductive film 8 become electrically conductive. However, when heat is applied partially to the contact area 9.116 of the conductive film 2 and the oxide-based conductive film 8 using a laser beam or the like, oxygen in the oxide-based conductive film 8 diffuses into the conductive film 2, and the contact area 9 with Si, 02 and AQ20. Oxide-based insulating film 9 such as
is formed to insulate the conductive film 2 and the oxide-based conductive film 8. Here, the conductive film 2 corresponds to the polycrystalline silicon film 314 of the drain contact region 116, and the oxide conductive film 8 corresponds to the pixel driving transparent conductive film 3.17.
第２の実施例を以下に示す。第３図はソース拡散領域３
０５．ゲート電極領域３０３間にリークを有する薄膜ト
ランジスタの平面図である。ソース領域３０５にソース
配線３０１として配線物系導電膜を用いて、第１の実施
例用様コンタクト領域３０５にレーザ等により部分的に
熱を加えればソースコンタクト領域３０５に酸化物系の
絶縁膜が形成されソースライン３０１とゲートライン３
０２を絶縁することにＪ：す、ライン欠陥を修正するこ
とができる。A second example is shown below. Figure 3 shows the source diffusion region 3.
05. 3 is a plan view of a thin film transistor having leakage between gate electrode regions 303. FIG. If a wiring-based conductive film is used as the source wiring 301 in the source region 305 and heat is applied partially to the contact region 305 using a laser or the like as in the first embodiment, an oxide-based insulating film is formed in the source contact region 305. A source line 301 and a gate line 3 are formed.
By insulating 02, line defects can be corrected.
第３の実施例を以下に示す。第４図はソース拡散領域４
０９．ゲート電極領域４０３間にリークを有する薄膜ト
ランジスタの平面図である。この実施例はソース配線４
０１にアルミニウム等の低抵抗の導電膜を用いた場合で
ある。ソース配線４０〕及びＴＦＴのソース拡散領域４
０９にコンタク［・ホールを開口し、酸化物系導電膜４
０８で電気的に導通をとっである。ソース拡散領域４０
９゜ゲート電極領域４０３にリークを有する薄膜１、ラ
ンジスタにおいて、コンタクト領域３０５，３０６の片
側又は両側領域にレーザ等により部分的に熱を加えコン
タクト領域界面３０５，３０６に酸化物系絶縁膜を形成
し、ソースライン４０１とゲートライン４０２とを絶縁
することにより、ライン欠陥を修正することができる。A third example is shown below. Figure 4 shows the source diffusion region 4.
09. 3 is a plan view of a thin film transistor having leakage between gate electrode regions 403. FIG. In this embodiment, the source wiring 4
This is a case where a low-resistance conductive film such as aluminum is used for 01. Source wiring 40] and TFT source diffusion region 4
Contact hole is opened in 09, and oxide-based conductive film 4 is formed.
Electrical continuity is established at 08. Source diffusion region 40
9° In the thin film 1 and transistor having leakage in the gate electrode region 403, heat is applied partially to one or both sides of the contact regions 305 and 306 using a laser or the like to form an oxide-based insulating film at the contact region interfaces 305 and 306. However, line defects can be corrected by insulating the source line 401 and gate line 402.
本発明によれば、ＴＩ”Ｔに欠陥が発生した場合にＴＰ
Ｔとソース、ゲートラインとのコンタク１−部分に部分
的に熱を加えるだけで欠陥ＴＰＴを電気的に絶縁できる
ので、他の部分への汚染等の影響を与えないで欠陥を修
正できる効果がある。また、ソース、ゲートラインリー
クによるライン欠陥の画素欠陥にすることが可能となる
。よって表示パネルの歩留い向上及び修正時間の短縮な
どすぐれた効果がある。According to the present invention, when a defect occurs in TI"T, the TP
Since the defective TPT can be electrically isolated by simply applying heat to the contact area 1 between the T and the source and gate lines, the defect can be repaired without contaminating other parts. be. Furthermore, it becomes possible to convert line defects into pixel defects due to source and gate line leakage. Therefore, there are excellent effects such as improving the yield of display panels and shortening the repair time.
第１図（ａ） （ｂ）本発明の第１の実施例髪示す
。第２（ａ）は′ｇ１．股トランジスタの平面図、第２
図（ｂ）は第２図（ａ）の破線断面図。
第２図（Ｃ）、（ｄ）は従来方法による欠陥修正後の外
観図である。第３図は本発明による第２の実施例を示す
。第４図は本発明による第３の実施例を示す。
１．２１１・・・絶縁性基板、２，２１２，２１３・・
・ソース・ドレイン拡散領域、１１３，２０３゜２１５
．２３３，３０３，４０３−・・グー１−電極。
１１２．２０２，３０２，４０２・・・ゲートライン、
１．１４，２０４，３０４，４０４・・・多結晶シリコ
ン薄膜、１１５，２０５，３０５゜４０５．４０９・・
・ソースコンタクト、６゜２１６・・・層間絶縁膜、２
１５・・・ゲート電極。
１１６．２０６，３０６，４０６・・・ドレインコンタ
クト、８，１１７，２０７，２１８゜３０７．４０７，
４０８・・・透明導電膜、】】、］−２２０１，２１７
，３０１，４０１・・・ソースライン、９・・・酸化物
系絶縁膜。FIGS. 1(a) and 1(b) show hair of a first embodiment of the present invention. The second (a) is 'g1. Top view of the crotch transistor, 2nd
Figure (b) is a sectional view taken along the broken line in Figure 2 (a). FIGS. 2(C) and 2(d) are external views after defect correction by the conventional method. FIG. 3 shows a second embodiment according to the invention. FIG. 4 shows a third embodiment according to the invention. 1.211...Insulating substrate, 2,212,213...
・Source/drain diffusion region, 113, 203° 215
．． 233,303,403--Goo 1-electrode. 112.202,302,402...gate line,
1.14,204,304,404...polycrystalline silicon thin film, 115,205,305°405.409...
・Source contact, 6°216... interlayer insulating film, 2
15...Gate electrode. 116.206,306,406...Drain contact, 8,117,207,218°307.407,
408...Transparent conductive film, ], ]-2201, 217
, 301, 401... Source line, 9... Oxide-based insulating film.
Claims (1)
膜トランジスタのソース換算領域とゲート電極との間に
リーク電流が流れ、該ソース拡散量的及びゲート電極に
電気的接続するソースライン及びゲートライン間のリー
クが発生した薄膜トランジスタに於いて、該ソース拡散
領域に酸化物系導電膜とのコンタクト領域を形成し、コ
ンタクト領域を部分的に熱することによりソースライン
及びゲートライン間を絶縁することを特徴とする欠陥救
済方法。1. A leakage current flows between the source equivalent region and the gate electrode of each thin film transistor arranged in a matrix on an insulating substrate, and leakage current flows between the source line and the gate line electrically connected to the gate electrode in terms of the source diffusion amount and the gate electrode. In a thin film transistor in which leakage has occurred, a contact region with an oxide-based conductive film is formed in the source diffusion region, and the contact region is partially heated to insulate between the source line and the gate line. and how to remedy defects.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1042992A JPH02223928A (en) | 1989-02-27 | 1989-02-27 | Defect relieving method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1042992A JPH02223928A (en) | 1989-02-27 | 1989-02-27 | Defect relieving method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02223928A true JPH02223928A (en) | 1990-09-06 |
Family
ID=12651525
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1042992A Pending JPH02223928A (en) | 1989-02-27 | 1989-02-27 | Defect relieving method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02223928A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004006339A (en) * | 2002-04-26 | 2004-01-08 | Sanyo Electric Co Ltd | El panel dimming method and el panel |
| WO2012160609A1 (en) * | 2011-05-26 | 2012-11-29 | パナソニック株式会社 | Display panel and manufacturing method for same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4840022U (en) * | 1971-09-16 | 1973-05-19 | ||
| JPS6315637A (en) * | 1986-07-04 | 1988-01-22 | 三洋電機株式会社 | Battery |
| JPS63153738U (en) * | 1987-03-25 | 1988-10-07 |
-
1989
- 1989-02-27 JP JP1042992A patent/JPH02223928A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4840022U (en) * | 1971-09-16 | 1973-05-19 | ||
| JPS6315637A (en) * | 1986-07-04 | 1988-01-22 | 三洋電機株式会社 | Battery |
| JPS63153738U (en) * | 1987-03-25 | 1988-10-07 |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004006339A (en) * | 2002-04-26 | 2004-01-08 | Sanyo Electric Co Ltd | El panel dimming method and el panel |
| JP4508547B2 (en) * | 2002-04-26 | 2010-07-21 | 三洋電機株式会社 | EL panel dimming method and EL panel |
| WO2012160609A1 (en) * | 2011-05-26 | 2012-11-29 | パナソニック株式会社 | Display panel and manufacturing method for same |
| US8704309B2 (en) | 2011-05-26 | 2014-04-22 | Panasonic Corporation | Display panel and method of manufacturing the same |
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