JPH0221751U - - Google Patents

Info

Publication number
JPH0221751U
JPH0221751U JP10050288U JP10050288U JPH0221751U JP H0221751 U JPH0221751 U JP H0221751U JP 10050288 U JP10050288 U JP 10050288U JP 10050288 U JP10050288 U JP 10050288U JP H0221751 U JPH0221751 U JP H0221751U
Authority
JP
Japan
Prior art keywords
semiconductor element
mounting
terminal
lead
support frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10050288U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10050288U priority Critical patent/JPH0221751U/ja
Publication of JPH0221751U publication Critical patent/JPH0221751U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第1図は本考案の一実施例を示す平面図、第2
図、第3図は本考案の応用例を示す平面図である
。 1,2……半導体素子搭載用支持架、3……半
導体素子、4……金属細線、11,22……外部
端子、33……引出し用端子。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体素子搭載用支持架を有する端子及び前記
    半導体素子表面に形成された電極を金属細線で結
    合して外部に引き出す端子を有するリードフレー
    ムにおいて、前記引出し用端子の両側に半導体素
    子搭載用支持架を有する端子を対称形に配置した
    ことを特徴とする半導体素子搭載用リードフレー
    ム。
JP10050288U 1988-07-28 1988-07-28 Pending JPH0221751U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10050288U JPH0221751U (ja) 1988-07-28 1988-07-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10050288U JPH0221751U (ja) 1988-07-28 1988-07-28

Publications (1)

Publication Number Publication Date
JPH0221751U true JPH0221751U (ja) 1990-02-14

Family

ID=31328633

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10050288U Pending JPH0221751U (ja) 1988-07-28 1988-07-28

Country Status (1)

Country Link
JP (1) JPH0221751U (ja)

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