JPH0245651U - - Google Patents
Info
- Publication number
- JPH0245651U JPH0245651U JP1988124555U JP12455588U JPH0245651U JP H0245651 U JPH0245651 U JP H0245651U JP 1988124555 U JP1988124555 U JP 1988124555U JP 12455588 U JP12455588 U JP 12455588U JP H0245651 U JPH0245651 U JP H0245651U
- Authority
- JP
- Japan
- Prior art keywords
- plastic
- metal plate
- mold
- sealed
- element chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 5
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
第１図は本考案の第１実施例を示し、同図ａは
内部構造の平面図、同図ｂはその縦断面図、第２
図は本考案の第２実施例を示し、同図ａは内部構
造の平面図、同図ｂはその縦断面図、第３図は従
来のパツケージ構造を示し、同図ａは内部構造の
平面図、同図ｂはその縦断面図である。 １，１１……リードフレーム、２，１２……半
導体素子チツプ、３，１３……リード端子、４，
１４……金属細線、５，１５……プラスチツク、
６，１６……金属板、６ａ……リード片。
内部構造の平面図、同図ｂはその縦断面図、第２
図は本考案の第２実施例を示し、同図ａは内部構
造の平面図、同図ｂはその縦断面図、第３図は従
来のパツケージ構造を示し、同図ａは内部構造の
平面図、同図ｂはその縦断面図である。 １，１１……リードフレーム、２，１２……半
導体素子チツプ、３，１３……リード端子、４，
１４……金属細線、５，１５……プラスチツク、
６，１６……金属板、６ａ……リード片。
Claims (1)
- 半導体素子チツプをプラスチツクでモールド封
止してなる半導体装置において、前記半導体素子
チツプを覆うように金属板を設け、かつこの金属
板を前記プラスチツクでモールド封止すると共に
、該金属板と電気的に接続されるリードをプラス
チツク外に引出したことを特徴とする半導体装置
のパツケージ構造。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988124555U JPH0245651U (ja) | 1988-09-22 | 1988-09-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988124555U JPH0245651U (ja) | 1988-09-22 | 1988-09-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0245651U true JPH0245651U (ja) | 1990-03-29 |
Family
ID=31374392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988124555U Pending JPH0245651U (ja) | 1988-09-22 | 1988-09-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0245651U (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015133024A1 (ja) * | 2014-03-06 | 2015-09-11 | 三菱電機株式会社 | 電力用半導体装置 |
-
1988
- 1988-09-22 JP JP1988124555U patent/JPH0245651U/ja active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015133024A1 (ja) * | 2014-03-06 | 2015-09-11 | 三菱電機株式会社 | 電力用半導体装置 |
| JPWO2015133024A1 (ja) * | 2014-03-06 | 2017-04-06 | 三菱電機株式会社 | 電力用半導体装置 |
| EP3116023A4 (en) * | 2014-03-06 | 2017-12-06 | Mitsubishi Electric Corporation | Power semiconductor device |