JPH02216574A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To allow each processor to possess common high-speed accessible time by inputting a time signal generated by means of a time counter to a CPU on the processor, or switching the time signal and inputting it to the other CPU. CONSTITUTION:Processors 1A, 1B and 1C respectively are constituted of a clock generating circuit 2, a time counter 3, a switching circuit 4 to switch the time signal, and a CPU 6. For example, when the time counter 3 of the processor 1A generates a count-up output, the signal from the time counter 3 of the processor 1a is interrupted by the switching circuit 4. Contact points A and B of the switching circuit of the processor 1A are separated, only contact points B and C are connected, and a time updating signal sent from the other processors 1B and 1C through a time updating transmission signal line 7 is inputted to the NMI terminal of the CPU. Thus the common high-speed accessible time by means of the multiprocessor can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor system in which a plurality of processors share one common bus.

[Conventional technology]

FIG. 4 is a block connection diagram showing a conventional multiprocessor system. In the figure, ID, IE, and IF are processors, and these are connected to one common bus 8. Furthermore, as shown in FIG. 5, each of these processors ID to IF includes a clock generation circuit 2, a time counter 3 that counts the clock from this clock generation circuit 2 and outputs a time signal, and this time counter 3. Based on the count-up output of the central processing unit (hereinafter referred to as CP),
It consists of an interrupt controller 5 that issues an interrupt to a computer (referred to as U) 6.

Next, the operation will be explained. First, clock generation circuit 2
The clock generated in is input to the time counter 3. The time counter 3 outputs a signal to the 1-interrupt controller 5 when the CPU 6 counts the clock generation of a preset value using the control signal 9. Therefore, the interrupt controller 5 receives this count and the resulting signal. C.P.
This is input to the interrupt input line of U6, and upon receiving this input, the CPU 6 is driven to interrupt and updates the time stored in the main memory.

In this way, a time value that can be arbitrarily referenced by the CPU 6 at high speed is set in the main memory.

[Problem to be solved by the invention]

Since the conventional multiprocessor system is configured as described above, if the load of the program executed by each processor ID to IF is different, the program execution for the time counter 3 of the CPU 6 is different from each processor ID to IF.
This causes a time lag.

As a result, there were problems such as the time values held in the main memory of the CPU 6 being different for each processor ID to IF.

On the other hand, when only one processor manages time and other processors need time, it is possible to access the processor that manages time and obtain a common time. This method has problems, such as that it can only be accessed at low speeds, so it cannot be applied to applications that require fast time acquisition. The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a multiprocessor system in which each processor can have a common time that can be accessed at high speed through a common bus.

[Means to solve the problem]

A multiprocessor system according to the present invention uses a switching circuit to input a time signal generated by a time counter that counts clocks from a clock generation circuit on one processor to a CPU on that processor, and at the same time Output to a dedicated signal line provided on the bus or ignore the time signal generated from the time counter on your own processor, and input only the time signal on the dedicated signal line on the common bus from other processors to the CPU. The time is updated on all processors at the same time.

[Effect]

The switching circuit in this invention transmits a time signal generated by only one processor in a multiprocessor using a common bus to all processors through one signal line on the common bus. It operates to update the time at the same time.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, IA is a processor.

These are the clock generation circuit 2, the time counter 3, and the time signals output by the time counter 3 are simultaneously supplied to the CPU 6 and the common bus 8, and the time signals of other processors obtained from the common bus 8 are taken into the CPU 6. The switching circuit 4 and the CPU 6 that can be switched to
It consists of

In FIG. 2, in addition to the processor IA, a processor IB and an IC having a similar internal configuration are provided.

2 is a block connection diagram showing a multiprocessor system of the present invention in which these are connected to one common bus 8. FIG. In FIG. 2, the switching circuit 4 in each of the processors IA to IC is connected to three switch contacts A.

It is conceptually illustrated by B, C and a switch contact piece.

Next, the operation will be explained. First, when the contact piece of the switching circuit 4 is connected to all contacts A, B, and C, the count-up output of the time counter 3 is input to the non-maskable interconnected (hereinafter referred to as NMI) terminal of the CPU 6. For example, clock generation circuit 2 of processor IA
When the time counter 3 that counts the clock generated in
At the same time as being input to the NMI terminal of the PU 6, it is also transmitted to the common bus 8 via the time update transmission signal line 7. on the other hand,
Since the signal input to the CPU 6 is input to the NMI terminal of the CPU 6, no matter what operation the CPU 6 is performing, it is always detected by the CPU 6 and the time of the processor IA is updated.

On the other hand, when the signal from the time counter 3 of the processor IA is cut off by the switching circuit 4, this processor IA
Even if the time counter 3 of A generates a clock count-up output, contacts A and B of the switching circuit of this processor IA are disconnected, only contacts B and C are connected, and this signal is ignored. In this case, only the time update signal sent via the time update transmission signal line 7 from the other processors IB and IC via the common bus 8 is
It is input to the NMI terminal of the CPU 6.

As can be seen from the configuration in FIG. 2, when the time counter 3 of the processor IA counts up.

The time update signal is simultaneously transmitted to the CPU 6 of the processor IA as well as to each CPU 6 of the processors IB and IC. Then, by making all the processors IA to IC simultaneously receive the first time update signal, time synchronization among the multiprocessors can be achieved. FIG. 3 is a flowchart showing the procedure for time synchronization and system start processing, which will be explained as follows. First, by powering on the multiprocessor system or resetting all processors IA-IC, each processor IA-IC issues a control command to be executed by each processor IA-IC, and each processor IA-IC performs onboard initialization of its own processor ( Step 5TI), all processors IA~
The time until the initialization of the IC is completed is a loop. Next, each processor IA to IC initializes its own time counter 3 and causes the time counter 3 to start counting operation (step 5T2), and then, Wait for the first NMI interrupt to occur (step 5T3). In this way, when the time counter 3 counts up and contacts A and C of the switching circuit 4 are connected, or when the time of the common bus 8 When a 1-time update signal is input through the update transmission signal line 7.

The loop of step ST3 is exited, and normal system software operation is started (step 5T4).

As a result, all the processors IA to IC wait for the common start time for all boards.

〔Effect of the invention〕

As described above, according to the present invention, the count-up signal of the time counter is transmitted to the common bus and the on-board CPU.
A switching circuit is provided to switch between outputting the count-up signal to the 200 PU, or inputting the count-up signal to the 200 PU from the common bus, so that the count-up signal is simultaneously transmitted to other processors through the signal line on the common bus. Since I configured it,
As in the past, the time can be held in the main memory of the processor, and the advantage is that it is possible to have a common time that can be accessed quickly by multiple processors.

[Brief explanation of the drawing]

FIG. 1 is a block connection diagram showing a processor of a multiprocessor system according to an embodiment of the invention, FIG. 2 is a block connection diagram showing the entire multiprocessor system of the invention, and FIG. FIG. 4 is a flowchart showing the procedure of synchronization processing, FIG. 4 is a block connection diagram showing a conventional multiprocessor system, and FIG. 5 is a block connection diagram showing a conventional processor. LA, IB, and IC are processors, 2 is a clock generation circuit, 3 is a time counter, 4 is a switching circuit, and 6 is a central processing bag! (CPU), 8 is a common bus. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent Applicant: Mitsubishi Electric Corporation 1A Near 0 "Tsu" Figure Figure 1B. IC-7 t,,”i Fig.

Claims (1)

[Claims] A plurality of processors connected to one common bus, a clock generation circuit provided in each of these processors to generate a clock, and a time counter provided in each of the processors to count the clock from the clock generation circuit. and a central processing unit provided in each of the processors, which receives a time signal from the time counter and updates the time; and a central processing unit that inputs the time signal from the time counter to the central processing unit, and a It can be switched to output to the dedicated signal line provided on the common bus, or to input only the time signal output from the time counter of another processor to the dedicated signal line of the common bus to the central processing unit of the own processor. A multiprocessor system equipped with a switching circuit.