JPH0876822A - Drive control command device and synchronization control system and method for plural drive control command devices - Google Patents

Abstract

PURPOSE: To obtain a drive control command device which can construct a synchronization system that is capable of a synchronizing operation with no step-out, in a system constructed by plural drive control command devices. CONSTITUTION: The drive control command device consists of an operation clock generation part 9, an interruption generation part 11 which outputs interruption signal for each operation clock, an office number setting part 13 which sets office number to show whether the drive control command device is to be operated as a master or a slave, a synchronizing timing signal transmission part 15 which operates only when the drive control command device is used as a master and outputs a synchronizing timing signal based on the operation clock, a synchronization control part 18 which operates only when the drive control command device is used as a slave and outputs a synchronizing operation start signal based on the error state signal showing a preparatory state or a synchronous state of the synchronizing operation and also on the synchronizing tiling signal received from the drive control command device serving as a master, a synchronization checking part 22 which decides whether the operation of the drive control command device serving as a slave is in synchronism with that of the command device serving as a master or not, and an error signal generation part 24 which outputs error signal based on the error state signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a general industrial machine and the like, for example, an assembly line in which several various robots simultaneously perform different operations in synchronization with the movement of a conveyor. The present invention relates to a method of synchronously controlling a plurality of drive control command devices in synchronization with the movement of the drive control system, a synchronous control system of the plurality of drive control command devices, and a drive control command device used in the synchronous control system.

[0002]

2. Description of the Related Art FIG. 12 is a block diagram of a synchronization system using a conventional drive control command device. In the figure, 144 is a drive control command device, 8 is a microcomputer that controls the operation of the drive control command device 144, 9 is an operation clock generation unit that generates an operation clock 5, and 11 is a microcomputer 8 based on the operation clock 5. An interrupt generator that outputs an interrupt signal 12 for interrupting the
Reference numeral 4 is a drive control device that is motion-controlled by a drive control command device, 145 is a position detector that outputs a pulse 146 according to the rotation angle, and 147 is a pulse counter that counts the pulse 146.

Since the conventional drive control command device is constructed as described above, each drive control command device 144 is
When the power is turned on, the operation clock generator 9 starts operating and generates the operation clock 5. The interrupt generator 11 outputs an interrupt signal 12 to the microcomputer 8 in synchronization with the fall of the operation clock 5. The microcomputer 8 determines whether the interrupt by the interrupt signal 12 can be permitted based on the interrupt level, and when the interrupt can be permitted, executes the interrupt processing by the interrupt signal 12. This interrupt processing differs depending on each drive control command device.

Further, a case where a plurality of drive control command devices 144 are operated in synchronization with one position detecting section 145 will be described. First, the position detecting section 145 simultaneously generates a plurality of pulses 146 according to the rotation angle thereof. It is given to the drive control command device 144. Each drive control command device 144 counts pulses 146 with a pulse counter 147. Next, the microcomputer 8 sets the pulse counter 1
The data is read from 47, and a command is given to the drive control device 4 according to the data to perform control. Therefore, the plurality of drive control command devices 144 can be operated in synchronization with the rotation of the single position detection unit 145.

FIG. 13 shows a conventional example of synchronization between devices implemented by the positioning device disclosed in Japanese Patent Laid-Open No. 5-73147. 148a is a master positioning device, 1
48b is a slave positioning device, 149 is a CPU that controls the internal processing of the positioning controller, 150 is a communication interface that performs data communication between the master and slave, and the master and slave are data communication lines 151.
And a synchronous clock line 152.

Since the conventional example of FIG. 13 is configured as described above, position information is exchanged between the master positioning device 148a and the slave positioning device 148b via the data communication line 151. A master positioning device 148a and a slave positioning device 148b
The master and slave are synchronized by sharing in. Further, the position information transfer process and the drive device process are time-divided, and the master positioning device 1
In order to match the timing of starting the processing of each of the positioning device 48a and the slave positioning device 148b, the master positioning device 148a to the slave positioning device 1
A clock is supplied to 48b through a synchronous clock line 152.

FIG. 14 shows a conventional example of a synchronization system of a digital device disclosed in Japanese Patent Laid-Open No. 3-154450.
Reference numeral 153 is a reception circuit for receiving a reception signal 154 from an external device, 155 is a timing extraction circuit for extracting a reception timing 156 at the moment when the reception signal 154 is received, 157.
Is a timing disconnection detection circuit for detecting that the signal level of the reception signal 154 has not changed and the timing of the reception timing 156 cannot be extracted. 158 is an external clock supplied from an external device. 159 is an external clock 1.
An external clock loss detection circuit for detecting that the signal level of 58 does not change, 160 adjusts the output timing of the reference clock 163 to any timing of the reception timing 156, the external clock 158, and the internal clock. Mode control circuit for switching modes, 16
1 is a mode switch, 162 is a reference clock 1
It is a clock generator that produces 63.

Since the conventional example of FIG. 14 is configured as described above, the reception signal 154 received by the reception circuit 153 is output to the timing extraction circuit 155, and is received in synchronization with the timing received by the timing extraction circuit 155. The timing 156 is extracted. In addition, the mode control circuit 160
The timing signal output from the timing extraction circuit 155 or the external clock 1 supplied from the outside based on the detection result of whether the timing can be extracted by the timing disconnection detection circuit 157 and the external clock disconnection detection circuit 159.
58, or three modes of internal operation.
The output selected by the mode control circuit 160 is input to the clock generator 162, and the reference clock 163 is generated.

[0009]

When a synchronous system is constructed by using a plurality of conventional drive control command devices of FIGS. 12 and 13, the operation clocks of the respective drive control command devices operate completely asynchronously. For example, as shown in FIG. 15A, due to the difference in individual characteristics of the power supplies of the drive control command device, even if the power switches are turned on at the same time, there is a difference in the timing of the rise of the power supply voltage inside the drive control command device. Occurs, the operation clocks of the master and slave drive control command devices are displaced. In addition, FIG.
Even if the rising timings of the power supply voltages are the same as in (b), there is a difference in the synchronization of the operation clocks of the respective drive control command devices due to the differences in the individual characteristics of the crystal oscillators and counters that make up the clock generator. When the error occurs, the deviation between the respective operation clocks is accumulated. Therefore, since each drive control command device operates independently based on the operation clock issued at its own timing, even if synchronization is simply achieved with a synchronization clock supplied from the outside, In each operation of the drive control command device, a maximum timing error of one cycle of the operation clock occurs. Therefore, when the operation speed of the drive control device is high, the position shift of each drive control device due to the shift of synchronization becomes remarkable, and it becomes impossible to coordinate a plurality of machines.

Further, when a plurality of conventional drive control command devices and one position detecting means constitute a synchronizing system, each drive control command device receives the position data from the position detecting means at its own processing timing. To read out and control the drive controller independently based on the position data,
In addition to the timing error of one operation clock cycle, a timing error of one read cycle is generated.
Further, if an abnormality occurs in the position data received by one drive control command device, only the drive control command device is kept out of synchronization and the synchronous operation is continued.

Further, in the conventional example of the synchronous system shown in FIG. 14, the timing disconnection error can be detected only when the external clock or the received signal is not input from the external device. Therefore, even if the reception timing of the reception signal or the external clock is deviated and the synchronization timing between the master and the slave is deviated, it cannot be detected, the master and the slave operate at different timings, and the synchronous operation cannot be performed.

The present invention has been made in order to solve such a problem, and in a system including a plurality of drive control command devices, a drive system capable of forming a synchronous system capable of synchronous operation without synchronization deviation. In a system including a control command device and one position detection means and a plurality of drive control command devices, only when all the drive control command devices normally receive the position data from the position detection means. An object of the present invention is to obtain a drive control command device capable of configuring a synchronous system capable of synchronous operation without synchronization deviation.

[0013]

A drive control command device according to the present invention comprises an interrupt generating means for outputting an interrupt signal for each cycle of an operation clock generated by the operation clock generating means, and the first drive control command device. A synchronous timing signal transmitting unit that operates only when used as the above and outputs a synchronous timing signal based on the operating clock;
Synchronous operation based on an error status signal that operates only when used as the second drive control command device and indicates a preparation state or synchronous state of a synchronous operation and a synchronization timing signal received from the first drive control command device A synchronization control unit that outputs a start signal, a synchronization check unit that determines whether the operation of the second drive control command device is in synchronization with the operation of the first drive control command device, and based on an error state signal An error signal generating unit that outputs an error signal, and outputs a movement start signal when used as the first drive control command device and performs synchronous control, and moves when used as the second drive control command device. And a microcomputer that performs synchronous control by inputting a start signal.

Further, in the drive control command device according to the present invention, the value of the counting means for generating the operation clock by dividing the clock output from the crystal oscillator by 1 / N is the level of the synchronization timing signal. The latch means is provided for latching at the moment when is changed, and the synchronization check means for comparing the latch contents of the latch means with a preset value to check whether the synchronization is normal is provided.

A synchronous control system for a drive control command device according to the present invention includes a first drive control command device for outputting a synchronization timing signal and a movement start signal to the second drive control command device; The second drive for synchronizing the operation clock with the first drive control command device based on the synchronization timing signal received from the drive control command device and executing the synchronous operation based on the received movement start signal. And a control command device.

When the drive control command device according to the present invention is used as the second drive control command device, it outputs a movement start signal and performs synchronous control when used as the first drive control command device. A microcomputer for performing synchronous control by inputting a movement start signal, interrupt generating means for outputting an interrupt signal to the microcomputer in each cycle of the operation clock generated by the operation clock generating means, and a first drive control command device, And parallel / serial data conversion means for operating parallel data from the microcomputer to serial data, and operating for the second drive control command device and receiving from the first drive control command device. Serial that converts the serial data into parallel data so that it can be handled by a microcomputer / Parallel data conversion means, parallel / serial data conversion means or serial / parallel data conversion means, shift clock generation means for outputting a shift clock that takes timing for transmitting or receiving serial data, and second drive control command device If it is, the serial data received twice is compared to check if there is any abnormality, and at the same time the operation mode for switching the operation state from asynchronous operation to synchronous operation or from synchronous operation to asynchronous operation is recognized. And a code comparison means for doing so.

Further, the drive control command device according to the present invention includes an interrupt generating means for outputting an interrupt signal to the microcomputer at each cycle of the operation clock generated by the operation clock generating means, and a first drive control command device. And a synchronization timing signal transmitting means for operating only when used as a second drive control command device and a synchronization timing signal transmitting means for outputting a synchronization timing signal based on the operation clock. Synchronous control means for outputting a synchronous operation start signal based on an error status signal indicating a synchronous state and a synchronous timing signal received from the first drive control command device, and the operation of the second drive control command device is the first drive A synchronization check means for determining whether or not the operation of the drive control command device of the control command device is synchronized;
Error signal generating means for outputting an error signal based on an error state signal, and parallel / serial for outputting a request signal requesting the position detecting means to transmit position data in response to request data from the first drive control command device. Data conversion means, serial / parallel data conversion means for converting the serial position data received from the position detection means into parallel data, and communication check means for checking that the position data has been normally input. is there.

Further, the drive control command device according to the present invention, when the communication error occurs in the second drive control command device, in order to notify the first drive control command device of the occurrence of the communication error, a synchronization check is performed. The error signal is shared with the error signal generating means used for.

Further, the synchronous control system of the drive control command device according to the present invention outputs the synchronization timing signal and the movement start signal to the second drive control command device and also outputs the request signal to the position detecting means. A first drive control command device that executes a synchronous operation in synchronization with the position data from the position detection means, and a first drive control command based on the synchronization timing signal received from the first drive control command device. A second drive control command device that synchronizes an operation clock with the device and executes a synchronous operation in synchronization with the received movement start signal and the position data from the position detection means. .

[0020]

In the present invention, the synchronization timing signal transmitting means outputs the synchronization timing signal based on the operation clock only when it is used as the first drive control command device, and the synchronization control means is the second drive control command device. By outputting the synchronous operation start signal based on the synchronization status signal received from the first drive control command device and the error status signal indicating the synchronous operation preparation state or the synchronous status only when used as the second The operation clock of the drive control command device can be generated at the same timing as the operation clock of the first drive control command device.

A latch for latching the value of the counting means for dividing the clock output from the crystal oscillator by 1 / N to generate the operation clock at the moment when the level of the synchronization timing signal changes. Means, and a synchronization check means for comparing the latch content of the latch means with a preset value to check whether the synchronization is normal, the operation clock of the second drive control command device is It is possible to determine that the synchronization deviation has occurred from the operation clock of the drive control command device.

When used as the first drive control command device, a movement start signal is output and synchronous control is performed, and when used as the second drive control command device, synchronous control is performed by inputting the movement start signal. A microcomputer for performing, an interrupt generating means for outputting an interrupt signal to the microcomputer in each cycle of the operation clock generated by the operation clock generating means, and a microcomputer for operating when it becomes the first drive control command device. Parallel / serial data conversion means for converting the parallel data of the above into serial data, and so that the microcomputer can handle the serial data received from the first drive control command device when operating as the second drive control command device. Serial / parallel data conversion means for converting to parallel data Shift / serial data conversion means or serial / parallel data conversion means outputs a shift clock that takes a timing for transmitting or receiving serial data, and a second drive control command device. Code comparison means for recognizing an operation mode for switching the operating state from asynchronous operation to synchronous operation or from synchronous operation to asynchronous operation by checking the abnormalities by comparing the serial data received doubly. It is possible to change the operation state of the drive control command device during operation from asynchronous operation to synchronous operation, or from synchronous operation to asynchronous operation.

Further, the synchronous timing signal and the movement start signal are outputted to the second drive control command device, and the request signal is outputted to the position detecting means to synchronize with the position data from the position detecting means. The first drive control command device for executing the operation, and the operation clock of the first drive control command device is synchronized with the first drive control command device based on the synchronization timing signal received from the first drive control command device A second drive control command device that executes a synchronous operation in synchronization with the movement start signal and the position data from the position detection means, and is synchronized with the rotation of one position detection means that outputs the position data. Thus, it becomes possible to operate a plurality of drive control command devices in synchronization.

Further, the drive control command device according to the present invention, when the communication error occurs in the second drive control command device, in order to notify the first drive control command device of the occurrence of the communication error, a synchronization check is performed. The error signal is shared by the error signal generating means used for the above, and simplification of the circuit configuration and reduction of wiring can be realized.

Further, in a system consisting of one position detecting means and a plurality of drive control command devices, when a communication error occurs in the first drive control command device or the second drive control command device, the first drive A synchronous control method in which only a drive control command device in which a communication error has occurred from the position detection means by newly transmitting a request signal from the control command device to the position detection means receives new position data is a drive control in which a communication error has occurred. Since the command device can immediately receive normal position data, the synchronization deviation at the time of a communication error can be minimized, and the normal synchronous operation without synchronization deviation can be promptly recovered.

[0026]

【Example】

Example 1. FIG. 1 is a block diagram showing an embodiment of a synchronous control system between a plurality of drive control command devices. In this embodiment, the same drive control command device can be used for both the first drive control command device (hereinafter referred to as the master) and the second drive control command device (hereinafter referred to as the slave). In the figure, 1a is a master drive control command device, and 1b is a slave drive control command device. Reference numeral 2 denotes an external setting device for the operator to set a station number indicating whether the drive control command devices 1a and 1b operate as a master or which station of the slave operates. for,
The external setting signal 3 is output. 4 is a drive control command device 1
It is a drive control device that performs motion control of the drive unit 7 according to the operation clock 5 and the command value 6 given from a and 1b.

Reference numeral 8 is a microcomputer for controlling the operation of the drive control command devices 1a, 1b. An operation clock generator 9 generates an operation clock 5 for performing motion control. An interrupt generation unit 11 receives the operation clock 5 and outputs an interrupt signal 12 to the microcomputer 8. 13 is a station number setting indicating whether the drive control command devices 1a and 1b are operated as a master (hereinafter referred to as a master mode) or a slave (hereinafter referred to as a slave mode) in response to an external setting signal 3. A station number setting unit that outputs a signal 14.

Reference numeral 15 denotes a sync timing signal transmitter which operates only in the master mode and outputs a sync timing signal 17 based on the operation clock 5 and the sync timing output permission signal 16 provided from the microcomputer 8. .. 18 operates only in the slave mode, and operates synchronously based on the station number setting signal 14, the synchronization timing signal 17 received from the master drive control command device 1a, and the error status signal 19 output from the microcomputer 8. The synchronization control unit outputs a start signal 20 and a synchronization check trigger signal 21. Reference numeral 22 is a synchronization check unit for checking the synchronization state based on the operation clock 5 and the synchronization check trigger signal 21 and outputting the synchronization state signal 23.

In the master mode 24, the error signal 25 from the slave drive control command device 1b is inputted to inform the microcomputer 8 of the occurrence of an error in the slave by the slave error signal 26, and in the slave mode. In this case, it is an error signal generator that outputs an error signal 25 based on the station number setting signal 14 and the error status signal 19. Reference numeral 27 is a movement start signal for starting synchronous operation at the same time.

FIG. 2 shows an example of a circuit that realizes the constituent blocks of the drive control command device 1 (1a, 1b) that constitutes the synchronous control system of FIG. The operation clock generator 9 is composed of a crystal oscillator 28 and counters 29 and 30,
The counter 29 outputs the clock output from the crystal oscillator 28.
When the synchronous operation start signal 20 input to the reset terminal of the counter 30 is at the HIGH level, the counter 30 reduces the internal clock 10 to 1/2 ¹⁰ . Divide and operate clock 5
Generate

The interrupt generation unit 11 includes a flip-flop 3
1 and 32 and the NAND circuit 33, the interrupt signal 12 is set to the LOW level for one clock of the internal clock 10 in synchronization with the rising edge of the operation clock 5 to issue an interrupt request to the microcomputer 8. The synchronization timing signal transmitter 15 is composed of a NAND circuit 34 and a three-state gate 35, and outputs the synchronization timing signal 17a in the master mode.

The synchronization controller 18 has a 3-state gate 36,
It is composed of flip-flops 37, 38, an OR circuit 39 and an AND circuit 40. In the slave mode, the synchronous operation start signal 20 is set to the LOW level for one clock of the internal clock 10 in synchronization with the fall of the synchronous timing signal 17b. . The synchronization check unit 22 is composed of a NOT circuit 41 and a latch circuit 42, and latches the value of the counter 30 at the moment when the synchronization timing signal 17b falls. The error signal generator 24 includes AND circuits 43 and 44 and a NOT circuit 4
5, an OR circuit 46, a NOR circuit 47, and three-state gates 48 and 49, the synchronization timing permission signal 16 and the error state signal 19, and the slave drive control device 1 in the subsequent stage.
Based on the error signal 25b input from b, the error signal 25a is output to the drive control command device of the previous stage.

The movement start signal 27a is output from the microcomputer 8 in the master mode and passes through the three-state gate 50 to drive all the drive control command devices 1a and 1b.
Are entered at the same time. Reference numeral 51 is a three-state buffer that controls the output of the operation clock to the drive control device 4 by the operation clock output permission signal 52 from the microcomputer 8. Reference numeral 53 is a reset switch that resets each component by setting the reset signal 55 to the LOW level by turning on the power of the drive control command device or turning on the external reset switch.

Next, the operation when the drive control command device of FIG. 2 is applied to the first embodiment of FIG. 1 will be described with reference to FIGS. 3A and 3B are waveform diagrams for explaining the operation of the drive control command device according to the present invention. FIG. 3A is a master operation in synchronous operation, FIG. 3B is a slave operation in synchronous operation, and FIG. It shows the operation in the case of driving. FIG. 4 is a flow chart of a program for controlling the synchronous operation of the drive control command device according to the present invention.

First, the case of performing the synchronous operation will be described. When the power supply 54a of the drive control command device 1a for controlling the slave to operate as a master for performing the synchronous operation is turned on and the reset signal 55a becomes HIGH level, the microcomputer 8 controls the synchronous operation. Start execution. When the operator sets the external setter 2 to use as the master drive control command device or the slave drive control command device, the external setter 2 sets the external station number setting signal 3 indicating the station number.
Is output. The station number setting unit 13 determines the content of the external setting signal 3. When the master number is set as the master here, the station number setting section 13 outputs the station number setting signal 1 in the master mode.
4a is HIGH level, slave mode station number setting signal 14b is LOW level, terminal number setting signal 14c for the last end
To LOW level.

The microcomputer 8 executes step 100.
1 reads these station number setting signals 14a to 14c,
In step 1002, if either of the station number setting signals 14a-14b is at the HIGH level, it is determined that the operation is synchronous, and if both of the station number setting signals 14a-14b are at the LOW level, it is determined that the operation is asynchronous. . If the microcomputer 8 is in asynchronous operation, step 102
4 to 1027 are executed, and if it is a synchronous operation, step 100
Perform steps 3 to 1023. In step 1003, the microcomputer 8 determines which of the station number setting signals 14a and 14b is at the high level. If the master station number setting signal 14a is at the high level, the microcomputer 8 determines that it is the master, and the slave station number setting signal 14b. Is high, it is determined to be a slave. When it is used as a master, step 1004 is executed, and when it is used as a slave, step 1014 is executed.

First, the processing when used as a master will be described. When the slave drive control command device 1b is turned on and preparations for synchronous operation such as station number setting are completed, the error signal 2 input from the slave error signal generation unit 24b to the master error signal generation unit 24a.
5a becomes HIGH level. In step 1004, the microcomputer 8 determines the level of the error signal 25a, and while the error signal 25a is at the LOW level and the preparation is not completed, the preparation incomplete alarm is output inside the microcomputer 8 in step 1005. Then, the process returns to step 1004 and waits until the preparation is completed.

If the error signal 25a becomes HIGH level, in step 1006 the microcomputer 8
Sets the synchronization timing output permission signal 16 to the HIGH level to permit the output of the synchronization timing signal 17a. This enables the 3-state gate 35 to be output, so that the synchronization timing signal 17a is output from the 3-state gate 35 to the drive control command device 1b of the slave. In step 1007, by setting the operation clock output enable signal 52 to the LOW level, the 3-state gate 51 can be output.
Is output. At this time, the interrupt signal 12a is generated in synchronization with the rising edge of the operation clock 5a input to the interrupt generator 11. The interrupt signal 12a is input to the microcomputer 8, and the microcomputer 8 executes processing for controlling the position and speed of the drive control device 4.

In step 1008, the error signal 25a becomes H
By checking whether the IGH level remains, it is determined whether the slave drive control command device 1b is in a good synchronization state. The synchronization status is insufficient and the error signal 25a
Becomes a LOW level, the microcomputer 8 stops the synchronous operation in step 1009, and then outputs a synchronization deviation alarm indicating that the synchronization deviation has occurred in the slave in step 1010 inside the microcomputer 8. The process ends.

When the error signal 25a is at the HIGH level and it is determined that the synchronization state is good, the microcomputer 8 executes the synchronous operation control program at step 1011. When the control program for the synchronous operation ends and the synchronous operation ends, the microcomputer 8 determines in step 1012 that the synchronous operation has ended. Drive control command device 1b
To stop the synchronous operation by stopping the output of the synchronization timing signal 17a to the synchronous operation signal.

Next, the processing when used as a slave will be described. The power 54b of the slave drive control command device 1b is turned on, and the reset signal 55b is set to HIG.
When the H level is reached, the microcomputer 8 starts executing the program for controlling the synchronous operation. The station number setting unit 13 determines the content of the external setting signal 3, and if it is set as a slave here, it sets the master mode station number setting signal 14a to LOW level and the slave mode station number setting signal 14b to HIGH level. Furthermore, if there is no slave at the final stage, there is no slave at the subsequent stage, so no error signal is input, so it is necessary to invalidate the input of this error signal. Therefore, the station number setting signal 1 for the last end
By setting 4c to HIGH level, the error signal 2
The output of the OR circuit 47 in the error signal generator 24 is set to HIGH level regardless of the input of 5b. This makes 3
The input to the state gate 50 can be disabled. Steps 1002 and 1003 are the same as the case of using as a master, and the description is omitted.

In step 1014, the microcomputer 8 sets the synchronization timing output enable signal 16 to the LOW level until the slave drive control command device 1b is powered on and the preparation for the synchronous operation such as the station number is completed. Error signal 25b output from the section 24b
Is set to the LOW level to notify the master drive control command device 1a that the preparation for the synchronous operation is not completed.
When the preparation for the synchronous operation is completed, by setting the synchronization timing output permission signal 16 to the HIGH level, the error signal 25b is set to the HIGH level and the master drive control command device 1a is notified that the preparation for the synchronous operation is completed. Inform.

Next, in step 1015, the input of the synchronization timing signal 17b from the master drive control command device 1a is waited for. When the synchronization control unit 18 receives the synchronization timing signal 17b, the synchronization operation start signal 20 is set to the LOW level for one clock of the internal clock 10 in synchronization with the fall of the synchronization timing signal 17b inside the synchronization control unit 18. By resetting the count of the counter 30 of the operation clock generation unit 9 with this synchronization operation start signal 20, the operation clock 5b is delayed with respect to the falling edge of the master synchronization timing signal 17b within one clock of the internal clock 10. Start to generate.

By setting the operation clock output enable signal 52 to the LOW level, the 3-state gate 51 can be output.
b is output. At this time, the interrupt signal 12b is generated in synchronization with the rising edge of the operation clock 5b input to the interrupt generator 11. This interrupt signal 12b is input to the microcomputer 8 and step 1016 is executed.
Then, the microcomputer 8 starts the processing for controlling the position and speed of the drive control device 4.

In step 1017, the microcomputer 8 allows the count value latched by the latch circuit 42 of the synchronization check unit 22 immediately before the counter 30 is reset, to allow a preset synchronization deviation inside the microcomputer 8. By comparing with the minimum value and the maximum value of the error, it is determined whether the deviation of the synchronization is within the allowable error and the synchronization state is good. If the synchronization state is good, the error state signal 19 is held at the LOW level to set the error signal 25b for notifying the master drive control command device 1a of the occurrence of the error to the HIGH level, and step 1018 is executed. Execute to perform synchronous operation. In step 1019, it is determined whether to continue the synchronous operation or to end the synchronous operation. If the operation is to be ended, a process of stopping the synchronous operation is executed in step 1020 and the process ends.

In normal operation, the sync timing signal 17
Although the drive control command devices 1b of the respective slaves can be sufficiently synchronized based on b, the clock generated by the crystal oscillator 28 or the counters 29, 30 due to the contact failure of the cable or the change of the ambient temperature outside the specification range. The period may exceed the allowable range, the waveform in the cable may become dull, or the clock waveform may be disturbed by the influence of external noise, which may cause synchronization deviation outside the allowable range. If the synchronization status becomes insufficient, step 102
At 1, the microcomputer 8 sets the error status signal 19 to H.
By setting to IGH level, the error signal 25b becomes L
The OW level is set and the master drive control command device 1a is notified of the occurrence of an error. At this time, since the error state signal 19 becomes HIGH level, the synchronization control unit 18 sets the synchronous operation start signal 20 to HIGH level,
By keeping the reset of the counter 30 released, the detection of the timing by the synchronization timing signal 17b is stopped, and the operation clock 5 is output based on the internal clock 10 regardless of the synchronization timing signal 17b. As a result, the slave drive control command device 1b starts an operation asynchronous with the operation of the master drive control command device 1a. Further, in step 1022, the microcomputer 8 stops the synchronous operation, and in step 1023, outputs a synchronization deviation alarm indicating that the synchronization deviation has occurred inside the microcomputer 8, and ends the processing.

When the synchronization deviation occurs, the amount of the synchronization deviation can be estimated and corrected from the current speed and position by the processing of software, but this cannot completely resynchronize, and it is subtle. Since the vehicle will be operated while leaving a gap, in this embodiment, the synchronous operation is stopped when a synchronization deviation occurs. When the synchronization shift occurs, the synchronization processing is performed again by returning to the origin once to resynchronize.

Next, the case of performing asynchronous operation will be described. When the power supply 54 of the drive control command device 1 (1a, 1b) is turned on and the reset signal 55 becomes HIGH level, the microcomputer 8 starts executing the program for controlling the synchronous operation. When the operator sets the external setting device 2 to be used in asynchronous operation, the external setting device 2 outputs the external station number setting signal 3 indicating the station number.
The station number setting unit 13 determines the content of the external setting signal 3. If the asynchronous mode is set, the station number setting unit 13 sets the master mode station number setting signal 14a to LOW level, the slave mode station number setting signal 14b to LOW level, and the final end station number setting signal 14c to LOW level. To do. At step 1001, the microcomputer 8 reads these station number setting signals 14a and 14b, and at step 1002, both station number setting signals 14a and 14b are LOW.
If the level is reached, it is determined that the operation is asynchronous.

If it is the asynchronous operation, the microcomputer 8 sets the error status signal 19 to HIGH at step 1024.
By setting the level, the output of the OR circuit 39 in the synchronization control unit 18 becomes the HIGH level. This gives A
The synchronous operation start signal 20 output from the ND circuit 40 is HI.
It becomes the GH level, and the input of the synchronization timing signal 17b becomes invalid. The operation clock generator 9 outputs the operation clock 5 based on the internal clock 10 by setting the synchronous operation start signal 20 to the HIGH level. At this time,
The interrupt signal 12 is generated in synchronization with the rising edge of the operation clock 5 input to the interrupt generator 11. The interrupt signal 12 is input to the microcomputer 8, and in step 1025, the microcomputer 8 starts processing for controlling the position and speed of the drive control device 4. In step 1026, the asynchronous operation is executed, and in step 1027, it is determined whether the asynchronous operation is to be continued or to be ended. If it is ended, the processing is ended.

Example 2. FIG. 5 is a configuration diagram of a drive control command device having means for switching the operation mode according to an embodiment of the present invention. 6 is a flow chart showing a synchronous control method of the drive control command device according to one embodiment of the present invention, and FIG. 7 is a synchronous timing diagram of the drive control command device according to one embodiment of the present invention.

In the first embodiment, the error signal 19 output from the microcomputer 8 is input to the synchronization control means 18 only when the synchronization is deviated when the synchronous operation is executed, and the error signal 19 is set to the LOW level. To HIGH level, the synchronous operation is switched to the asynchronous operation. Further, although a synchronization timing signal having a clock waveform is used for synchronization, in the embodiment of the drive control command device shown in FIG. 5, instead of synchronizing with the synchronization timing signal, various information is mastered. Is synchronized with the reception timing of serial data to be transmitted from the slave to the slave. In order to synchronize the serial data reception timing in this manner, the first embodiment
The drive control command device shown in FIG.
Serial data converters 84a and 84b are added, and
Serial / parallel data conversion units 85a and 85b and shift clock generation unit 83 that operate when performing a slave operation
b, a code comparison unit 87 is additionally provided. As a result, the serial data 8 input from the master drive control command device 82a to the slave drive control command device 82b
8 is converted into parallel data by the serial / parallel data conversion units 85a and 85b, and the code comparison unit 87 determines what kind of operating state the contents of the parallel data indicate and at the same time synchronizes with the reception timing of the parallel data. The slave drive control command device 8 is generated by generating the timing signal 17 and switching the timing at which the operation clock is supplied by the synchronization control means 18 based on the operation mode signal 89 output from the code comparison means 87.
The operation state of 2b can be switched from the asynchronous drive to the synchronous drive or from the synchronous drive to the asynchronous drive from the master drive control command device 82a.

Next, the details of the operation will be described with reference to FIGS. 6 and 7. First, in FIG. 6, step 1 of FIG.
The processing of 001 to 1002 has already been executed, the setting of the master drive control command device or the slave drive control command device to be used is completed, and each drive control command device performs synchronous operation or asynchronous operation. Suppose In step 1101, it is determined whether it is a master or a slave, and when it is used as a master, steps 1102 to 1108 are executed, and when it is used as a slave, steps 1110 to 1117 are executed.

First, the processing when used as a master will be described. In step 1102, the microcomputer 8 outputs the parallel data having the checksum bit to the parallel / serial data conversion units 84a and 84b connected in cascade. As a result, the same parallel data is set in the parallel / serial data converters 84a and 84b. After setting the parallel data, the microcomputer 8 sets the serial data 8
The shift clock output permission signal 90 is output at the timing when 8 is desired to be transmitted. Shift clock output enable signal 90 and station number setting signal 1 output from station number setting unit 13
4 is input to the shift clock generator 83a. The shift clock generator 83a determines whether the station number setting signal 14 is in a setting state for selecting a master operation or a slave operation, and whether the shift clock output signal 90 is in a permitting state. Here, station number setting signal 1
4 is in a setting state for selecting the master operation, and the shift clock output signal 90 is in a permitting state, the period is synchronized with the internal clock 10 and is a cycle that is an integral multiple of the cycle of the internal clock 10. Generate an integer multiple clock with.

In normal operation, when various data is transmitted and received between the master and slave, the parallel / serial data converters 84a, 8a connected in cascade are used.
In order to output the data set to 4b as the serial data 88, an integer multiple clock is output as the shift clock 86a by the number of clocks that is twice the data length to be transmitted. By supplying the shift clock 86a to the parallel / serial data conversion units 84a and 84b, the data in the parallel / serial data conversion units 84a and 84b are sequentially shifted to the output side for each clock of the system clock, and serial data is output. Reference numeral 88 designates the master drive control command device 82a to the slave drive control command device 82
Send to b.

On the other hand, when the synchronization timing is set by the serial data 88, the operation clock 5a is set as shown in FIG.
Is output as the shift clock 86a from the time before the time when the operation clock 5a falls by the number of clocks twice the data length to be transmitted from the time when the operation clock 5a falls. As a result, the operation clock 5a
Can be synchronized with the timing of the fall of the shift clock 86a. By supplying this shift clock 86a to the parallel / serial data conversion units 84a and 84b,
The data in the serial data conversion units 84a and 84b is converted into serial data 88, and the master drive control command device 82 is used.
Send from a. At this time, the contents of the serial data 88a are that the data A sent first is the data of the parallel / serial data conversion unit 84b, and the data B sent later is the data of the parallel / serial data conversion unit 84a.
The serial data 88 to be transmitted is serial data carrying information for switching the operating state from asynchronous operation to synchronous operation or from synchronous operation to asynchronous operation.

Next, in step 1103, the station number setting signal 1
According to the contents of 4, it is judged whether the operation state is switched from synchronous operation to asynchronous operation or from asynchronous operation to synchronous operation, and if the former is selected, step 110
If steps 4 to 1106 are executed and the latter is selected, step 11
07 to 1109 are executed. When switching from the synchronous operation to the asynchronous operation, it is determined in step 1104 whether the synchronous operation is being performed, and if it is not the synchronous operation, the step 11 is performed.
After executing 06, the processing for switching the operation mode is terminated. If the synchronous operation is in progress, the synchronous operation is stopped in step 1105, then step 1106 is executed, and then the processing for the operation mode switching is terminated. . In this step 1106, the same processing as steps 1024 to 1027 of FIG. 4 is executed.

When switching from asynchronous operation to synchronous operation, it is determined in step 1107 whether asynchronous operation is in progress. If asynchronous operation is in progress, the asynchronous operation is stopped in step 1108 and then step 1109 is executed. The process for switching the operation mode is ended, and if the operation is not in asynchronous operation, step 1109 is executed and then the process for switching the operation mode is ended. In step 1109, the same processing as steps 1004 to 1013 in FIG. 4 is executed.

Next, the processing when used as a slave will be described. In the case of a slave, when the preparation for operation as a slave is completed, the serial / parallel data conversion unit 8 in which the shift clock 86b is cascade-connected
5a and 85b to prepare for receiving the serial data 88. In step 1110, the slave drive control command device 82b waits for reception of the serial data 88 from the master drive control command device 82a. When the slave drive control command device 82b receives the serial data 88, the serial data 88 is converted into serial / parallel data conversion units 85a and 85b at every shift clock.
Are input while being sequentially shifted to, then converted to parallel data and then input to the code comparison unit 87. When the serial data 88 is received, the previously received data C
Is input to the serial / parallel data conversion unit 85b,
The data D received later is input to the serial / parallel data conversion unit 85a.

This code comparison unit 87 uses two serial /
It is confirmed that the contents of the parallel data conversion units 85a and 85b match and that there is no communication error. When there is no error, the parallel data is input from the code comparison unit 87 to the microcomputer 8, and the microcomputer 8 determines the content of the parallel data and uses it for various processes. At the same time, the code comparison unit 87 determines whether the content of the parallel data is data for switching the operation state from asynchronous operation to synchronous operation or data for switching from synchronous operation to asynchronous operation, and depending on the determination status. Synchronization timing signal 17 and operation mode signal 89
Is output. When the content of the parallel data is data for synchronizing timing, the synchronizing timing signal 17 is set to LOW level for the time of one clock of the shift clock immediately after the data determination. Furthermore, the code comparison unit 87 sets the operation mode signal 89 to L if the content of the parallel data is data for switching from asynchronous operation to synchronous operation.
If the data is set to the OW level and the synchronous operation is switched to the asynchronous operation, the operation mode signal 89 is set to the HIGH level.

This operation mode signal 89 is sent to the synchronization controller 18
And controls the synchronous operation start signal 20. When the operation mode signal 89 becomes LOW level and the asynchronous operation is switched to the synchronous operation, the fall of the synchronization timing signal 17 output from the code comparison unit 87 is detected and the synchronous operation start signal 20 is synchronously controlled. Output from the unit 18. This synchronous operation start signal 20 is input to the operation clock generator 9, and the counter of the operation clock generator 9 is reset to synchronize the operation clock 5 with the timing of the end of reception of the serial data 88 received from the master. Controls the timing to start generation.

When the synchronous operation is switched to the asynchronous operation, the synchronous operation start signal 20 is set to the HIGH level regardless of the timing of ending the reception of the serial data 88. Since the synchronous operation start signal 20 is at the HIGH level, the counter of the operation clock generator 9 is not reset,
The output of the operation clock 5 is continued at the current timing.

Further, the microcomputer 8 monitors the operation mode signal 89 in step 1111 to determine whether the operation state is switched from synchronous operation to asynchronous operation or from asynchronous operation to synchronous operation. If the former is selected, steps 1112 to 111
4 is executed and the latter is selected, steps 1115 to 11
Execute 17. When switching from the synchronous operation to the asynchronous operation, it is determined in step 1112 whether the synchronous operation is being performed. If the synchronous operation is not being performed, step 1114 is executed, the operation mode switching process is terminated, and the synchronous operation is being performed. In this case, the synchronous operation is stopped in step 1113, step 1114 is executed, and then the operation mode switching process ends.

When switching from asynchronous operation to synchronous operation, it is determined in step 1115 whether asynchronous operation is in progress. If asynchronous operation is in progress, the asynchronous operation is stopped in step 1116 and then step 1117 is executed. The operation mode switching process is terminated, and if it is not during asynchronous operation, step 1117 is executed and then the operation mode switching process is terminated. In step 1117, the same processing as in steps 1014 to 1023 of FIG. 4 is executed. By performing the above-described processing, the operating state of the master drive control command device can be switched from the synchronous drive to the asynchronous drive, or from the synchronous drive to the asynchronous drive.

Example 3. FIG. 8 is a block diagram of a synchronization system of a plurality of drive control command devices for one position detection unit according to one embodiment of the present invention, and FIG. 9 is one position detection unit according to one embodiment of the present invention. FIG. 3 is a circuit diagram of a drive control command device that constitutes a synchronization system for. FIG. 10 is a flow chart showing a communication control method of the master drive control commanding device in communication with the position detecting unit which is an embodiment of the present invention. FIG. 11 is a flowchart showing a communication control method of the drive control command device of the slave in the communication with the position detecting unit according to the embodiment of the present invention.

In FIG. 8 and FIG. 9, 108 is a parallel which operates only when it is used as a master and converts parallel request data output from the microcomputer 8 into a serial request signal and sends it to the position detecting section. / A serial data conversion unit. A serial / parallel data conversion unit 109 receives the position data in the serial format transmitted from the position detection unit 114 and converts it into parallel data. Reference numeral 110 indicates whether or not the position data received from the position detection unit 114 can be normally received, a parity check, a framing error check,
It is a communication error check unit that checks by overrun error check or the like. Reference numerals 111 and 112 denote three-state gates that control the input / output of serial data.

Reference numerals 113a and 113b are parallel / serial data conversion unit 108, serial / parallel data conversion unit 109, communication error check unit 110, and three-state gate 111 in drive control command device 1 (1a, 1b) shown in FIG. , 112 are added, 113a is a master, and 113b is a slave. The position detector 114 receives a position detector 115 for detecting the position of an external device such as a conveyor, data from the position detector 115, and a request signal 117 from the master drive control command device 113a, and receives the request signal 117. The position data 118 is sent to all the drive control command devices 113a to 113b and the data sending unit 116 which sends position data, alarm information, operating state information, etc. individually or in combination as position data 118 according to the contents of the above. It is composed of a 3-state gate 119 for keeping the output in a high impedance state except when transmitting. In FIG. 8, a drive control command device 113a that operates as a master, a drive control command device 113b that operates as a plurality of slaves, and one position detection unit 11
4 constitutes a synchronization system.

Next, the operation will be described with reference to FIGS. As shown in FIG. 1, in a system in which a master drive control command device and a plurality of slave drive control command devices can perform synchronous operation, first, an operator instructs the external setting device 2 to drive the master drive control command. The external setter 2 outputs an external station number setting signal 3 indicating a station number when setting the device or the number of slaves to be used as the drive control command device. The station number setting unit 13 determines the content of the external setting signal 3. When the station number setting unit 13 is set as the master here, the station number setting signal 14a in the master mode is set to the HIGH level and the station number setting signal 14b in the slave mode is set to the LOW level. When the station number setting signal 14a in the master mode is set to the HIGH level after being set to be used as the master, the three-state gate 111 for transmission is opened so that the request signal 117 can be transmitted.

At step 1201, the microcomputer 8 of the master drive control command device 113a obtains the position data and alarm information necessary for the synchronous operation from the position detecting section 114.
Request data 120 for making a request to the parallel / serial data conversion unit 108. Next, in step 1202, the microcomputer 8 outputs the transmission request signal 121 for controlling the timing of transmitting the request signal 117 to the position detection unit 114. The parallel / serial data conversion unit 108 generates a request signal 117 at the timing when the transmission request signal 121 becomes active, and the request signal 117 is transmitted to the position detection unit 114 via the three-state gate 111. In step 1203, the microcomputer 8 of the master drive control command device 113a determines that the three-state gate 11 for reception is used.
2 is opened so that the position data 118 can be received. When the position detection unit 114 receives the request signal 117, the position detection unit 114 outputs the detected position data 118 to the data transmission unit 116.
Drive control command devices 113a to 113 connected to the
Send to b. The microcomputer 8 waits until it receives the position data 118 in step 1204. When the position data 118 received through the receiving three-state gate 112 is input to the serial / parallel conversion unit 109, the serial / parallel data conversion unit 109 converts the position data 118 into parallel data so that the microcomputer 8 can handle it. To do. The converted position data is input to the microcomputer 8 and used for controlling the position of the drive control device.

On the other hand, the slave drive control command device 113
The microcomputer 8 of b waits in that state until it receives the position data 118 from the position detector 114. When the position data 118 is transmitted from the position detector 114, it is received by the master drive control command device 113a, and at the same time, the position data 118 received via the receiving three-state gate 112 is transferred to the serial / parallel converter 109. Entered in. The serial / parallel data conversion unit 109 converts the position data 118 into parallel data so that the microcomputer 8 can handle it. The converted position data is input to the microcomputer 8 and used to control the position of the drive control device 4.

As a result, a plurality of drive control command devices 11
3a to 113b can receive the same data from one position detection unit 114 at the same timing in the same cycle. Further, a plurality of drive control command devices 113a-
Since the 113b operates in synchronization with each other as shown in the first embodiment, in synchronization with the position of the single position detection unit 114,
It is possible to operate a plurality of drive control command devices synchronously.

The drive control command device 113a of the master is
When the position data 118 is received in step 1204 of FIG. 10, the communication error check unit 110 causes the position data 118.
Is normally received, and the result is notified to the microcomputer 8 by a check signal 122. If it can be received normally, the received data 1
23 is output to the microcomputer 8. Step 1
At 205, the microcomputer 8 determines from the check result whether the communication is normally performed. If the communication is normal, the microcomputer 8 sets the reception gate control signal 124 to the HIGH level in step 1206 to close the reception three-state gate 112 so that the position data 118 cannot be received. The microcomputer 8 waits for a certain period of time, which is the processing cycle, in step 1207, and then returns to step 1201 to perform processing for reading the next position data.

When a communication error occurs in the master drive control command device 113a itself or the slave drive control command device 113b due to disturbance of the waveform of the communication signal due to the influence of external noise or the like, the master performs communication. The error check unit 110 notifies the microcomputer 8 that a communication error has occurred. On the other hand, in the slave, when the communication error check unit 110 notifies the microcomputer 8 of the occurrence of the communication error, the microcomputer 8 sets the error state signal 19 to the HIGH level. The output of the AND circuit 44 in the error signal generator 24 is set to L because the error state signal 19 has become HIGH level.
It goes to the OW level, and the error signal 25b goes to the LOW level. In this way, the slave sends the error signal 25b to L
By setting to the OW level, the master is notified of the occurrence of a communication error.

When a communication error occurs in the master or the slave, the microcomputer 8 checks the number of retries in step 1208. If the number of retries is less than the set number, the microcomputer 8 returns to step 1201.
A process for reading the next position data is performed. When the retries have been performed the set number of times or more, the microcomputer 8 executes the operation ending operation in steps 1209 to 1211. The microcomputer 8 executes step 1209
Then, the reception gate control signal 124 is set to the HIGH level to close the reception three-state gate 112 so that the position data cannot be received. At step 1210, an alarm indicating that a communication error has occurred inside the microcomputer 8 is output. After that, the synchronous operation is stopped in step 1211, and the process ends.

On the other hand, the slave drive control command device 113
In step 1221 of FIG. 11, the b opens the receiving three-state gate 112 so that the position data 118 can be received, and waits in that state until the position data 118 is received in step 1222. Upon receiving the position data 118, the communication error check unit 110 causes the position data 11
It is checked whether 8 is normally received, and the result is notified to the microcomputer 8. Step 122
At 3, the microcomputer 8 determines from the check result whether communication has been normally performed.

If the communication is normal, the microcomputer 8 sets the receiving gate control signal 124 to the HIGH level in step 1224, and the receiving three-state gate 112.
Is closed so that the position data 118 cannot be received.
Further, by setting the error state signal 19 output from the microcomputer 8 to the LOW level, the error signal generating means 24 sets the error signal 25b to the HIGH level, and the master drive control command device 113a does not have an error, and the error is normally generated. Notify that it is working. The microcomputer 8 waits until a certain period of time, which is the processing cycle, has passed in step 1225, then returns to step 1221 to enter the next reception waiting state. Further, when a communication error occurs due to the disturbance of the waveform of the communication signal due to the influence of external noise, the microcomputer 8 sets the error state signal 19 to the HIGH level,
The error signal generator 24 sets the error signal 25b to the LOW level to notify the master drive control command device 113a of the occurrence of the communication error.

Further, the microcomputer 8 checks the number of retries in step 1226, and if the number of retries is less than the set number, returns to step 1221 and
The next waiting state is reached. If the retries have been performed the set number of times or more, the operation end operation after step 1227 is executed. The microcomputer 8 executes step 1227.
Then, the reception gate control signal 124 is set to the HIGH level to close the reception gate 112 so that the position data 118 cannot be received, and in step 1228, an alarm indicating that a communication abnormality has occurred inside the microcomputer 8 is output. Above, in step 1229, the synchronous operation is stopped and the processing is ended.

In the third embodiment, all the drive control command devices 113a to 113b transmit the request signal 117 to the position detecting section 114 at a constant timing in accordance with the processing cycle for performing motion control of the drive control device, The process of reading the above data is repeatedly executed.

In the first embodiment, for example, the synchronization timing signal output from the synchronization check circuit of the master drive control command device is input to the synchronization check circuits of the plurality of slave drive control command devices. One circuit of the drive control command device and one corresponding circuit of the drive control command devices of a plurality of slaves are connected by a certain signal, and means for coding each signal into data capable of serial communication and its means By providing a means for decoding, the same operation can be performed even if each signal is transmitted / received by serial communication using a pair of transmission / reception cables.

In the first embodiment, the clock output from the crystal oscillator is divided into 1/2 ¹¹ to be the operation clock. Therefore, when the 1 MHz crystal oscillator is used, the operation clock becomes 488 Hz, which is the internal clock. The synchronization error due to the difference is 1 μsec. Depending on the required degree of synchronization accuracy, the cost can be reduced by lowering the frequency of the crystal oscillator or changing the division ratio of the internal clock.

In the first embodiment, the counter and the latch circuit are used to check the deviation of the synchronization. However, the same operation is performed by configuring the counter with software and stopping the count up of the counter. You can

In the third embodiment described above, when a communication error occurs, the master drive control command device transmits a request signal again to the position detection unit to cause a communication error from the position detection unit. Only the position data can be newly received, but it is configured so that the position data can be transmitted from the drive control command device that normally received the position data to the drive control command device in which the communication error occurred. Can be expected to operate in the same way.

[0082]

Since the present invention is constructed as described above, it has the following effects.

Synchronization check means for checking the synchronization state of a plurality of slave drive control command devices, a synchronization control circuit for outputting a synchronization operation start signal based on a synchronization timing signal received from the master, and preparation for synchronization operation By providing an error signal generating means for outputting an error signal based on an error status signal indicating a status or a synchronization status,
Since the operation clocks of the plurality of slave drive control command devices can be generated at the same timing as the operation clocks of the master drive control command device, it is possible to perform synchronous operation between the plurality of drive control command devices. I can.

A counter for dividing the clock output from the crystal oscillator into 1 / N to generate an operation clock, and a counter for latching the value of the counter at the moment when the synchronization timing signal falls. The operation clock of the slave drive control command device is set to the master drive control by providing a latch circuit and a microcomputer that checks whether synchronization is normal by comparing the preset value with the latch content of the latch circuit. Since it is configured to notify the master drive control command device that a synchronization deviation has occurred from the operation clock of the command device, operation is performed when an abnormality occurs in the synchronization state of any one slave drive control command device. Can be prevented.

In addition, parallel / serial data conversion means for converting parallel data carrying information for switching the operating state into serial data, and serial for converting serial data input from the master drive control command device into parallel data. / Parallel data conversion means, shift clock generation means for outputting a shift clock for timing transmission or reception of serial data by the parallel / serial data conversion means or the serial / parallel data conversion means, the serial data received twice By providing code comparison means for comparing and checking the operation mode and recognizing the operation mode and mode switching means for switching the timing of supplying the operation clock, the operation state of the drive control command device of the slave can be externally switched. Having urchin configuration, it is possible to switch the operating state of the plurality of slave drive control commanding unit during operation by a serial data from the master drive control commanding unit in the synchronous operation of the asynchronous operation, or from the synchronous operation to the asynchronous operation.

Further, the parallel / serial data converting means for outputting a request signal for requesting the position detecting means to transmit the position data based on the request data output from the microcomputer and the position detecting means are received. By providing a serial / parallel data conversion circuit that converts the position data into parallel data that can be handled by a microcomputer, and a communication check circuit that confirms that the position data was received correctly, requests from only the master drive control command device can be made. Since the position data is requested to the position detection means by the signal and the position data is received, it is possible to operate the plurality of drive control command devices synchronously in synchronization with the rotation of one position detection means.

Further, when a communication error occurs, the master drive control command device transmits a request signal to the position detecting means again, so that only the drive control command device having the communication error from the position detecting means is newly added. Since the position data can be received, the synchronization deviation of the drive control command device in which a communication error occurs can be minimized, and normal synchronous operation without synchronization deviation can be recovered immediately even if a communication error occurs. You can

Further, in order to notify the master of the occurrence of the communication error when the communication error occurs in the slave,
Since the error signal generating means used for the synchronization check can be shared with the error signal, the circuit configuration can be simplified and the wiring can be saved.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a synchronization system of a drive control command device according to the present invention.

FIG. 2 is a circuit diagram of a drive control command device according to the present invention.

FIG. 3 is a waveform diagram for explaining the operation of the drive control command device according to the present invention.

FIG. 4 is a flowchart showing a method for controlling a synchronous operation according to the present invention.

FIG. 5 is a configuration diagram of a drive control command device having means for switching operation modes according to the present invention.

FIG. 6 is a flowchart showing a synchronous control method of the drive control command device according to the present invention.

FIG. 7 is a synchronization timing chart of the drive control command device according to the present invention.

FIG. 8 is a configuration diagram of a synchronization system for one position detection means of the drive control command device according to the present invention.

FIG. 9 is a circuit diagram of a drive control command device that constitutes a synchronization system for one position detecting means according to the present invention.

FIG. 10 is a flowchart showing a communication control method of the master drive control command device in communication with the position detecting means according to the present invention.

FIG. 11 is a flowchart showing a communication control method of the slave drive control command device in communication with the position detecting means according to the present invention.

FIG. 12 is a configuration diagram of a synchronization system using a conventional drive control command device.

FIG. 13 is a configuration diagram of a synchronization system of a conventional positioning device.

FIG. 14 is a block diagram of a synchronization system of a conventional digital device.

FIG. 15 is an operation explanation waveform diagram of an operation clock of a conventional drive control command device.

[Explanation of symbols]

1, 1a, 1b drive control command device, 5 operation clock, 8 microcomputer, 9 operation clock generation unit, 11 interrupt generation unit, 12 interrupt signal, 13 station number setting unit, 15 synchronization timing signal transmission unit, 17 synchronization timing signal, 18 synchronization control unit, 19 error status signal, 20 synchronization operation start signal, 22 synchronization check unit, 25 error signal,
27 movement start signal, 28 crystal oscillator, 30 counter, 42 latch circuit, 82, 82a, 82b drive control command device, 83, 83a, 83b shift clock generator, 84, 84a, 84b parallel / serial data converter, 85, 85a, 85b serial /
Parallel data conversion unit, 86a, 86b shift clock, 87 code comparison unit, 88 serial data,
108 parallel / serial data converter, 109
Serial / parallel data conversion unit, 110 communication error check unit, 113, 113a, 113b drive control command device, 114 position detection unit, 117 request signal, 118 position data, 120 request data

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G05B 19/02 W 19/05 19/414 G05D 3/00 R Q 3/12 Q G05B 19/05 J 19/18 N W

Claims (10)

[Claims] 1. An operation clock generating means for generating an operation clock, an interrupt generating means for outputting an interrupt signal at each cycle of the operation clock, and an operation as a first drive control command device or a second drive control. Station number setting means for setting a station number indicating whether to operate as a command device, and synchronization timing signal transmission that operates only when used as the first drive control command device and outputs a synchronization timing signal based on the operation clock Means and an error status signal that operates only when used as the second drive control command device and indicates a preparation state or a synchronous condition for a synchronous operation, and a synchronization timing signal received from the first drive control command device. And a synchronization control means for outputting a synchronous operation start signal, and the operation of the second drive control command device is the first drive control command. A synchronization check means for determining whether or not it is synchronized with the operation of the device, an error signal generating means for outputting an error signal based on an error state signal, and a movement start signal when used as the first drive control command device. A drive control command device, comprising: a microcomputer that outputs and performs synchronous control, and performs synchronous control by inputting a movement start signal when used as the second drive control command device. 2. The clock output from the crystal oscillator is N
Counting means for dividing the frequency by 1 to generate an operation clock, latching means for latching the value of the counting means at the moment when the level of the synchronization timing signal changes, and a preset value 2. The drive control command device according to claim 1, further comprising: a synchronization check unit that compares the latch contents of the latch unit with each other to check whether synchronization is normal. 3. A system comprising a plurality of drive control command devices, wherein the first drive control command device outputs a synchronization timing signal and a movement start signal to the second drive control command device to drive the second drive control command device. The control command device synchronizes an operation clock with the first drive control command device based on the synchronization timing signal received from the first drive control command device, and performs synchronous operation based on the received movement start signal. A synchronous control system for a drive control command device, characterized by being executed. 4. A step of determining whether the drive control command device is set as the first drive control command device or the second drive control command device, and the step of determining whether the drive control command device is set as the first drive control command device. When the preparation is completed, the operation clock of the second drive control command device is synchronized with that of the first drive control command device. In order to output a synchronization timing signal, a step of performing a process for controlling the position and speed to the drive control device that controls the drive unit, a step of determining whether the synchronization state is good, Whether the synchronous operation is executed when the synchronous condition is good, the synchronous operation is stopped when the synchronous condition is insufficient, and a sync deviation alarm is output, and whether or not the synchronous operation ends during execution of the synchronous operation Judge And a step of terminating the synchronous operation by stopping the output of the synchronization timing signal to the second drive control command device to stop the synchronous operation when the synchronous operation ends, and as a second drive control command device. When set, the step of executing the operation preparation and outputting the completion of the operation preparation to the first drive control command device together with the completion, and the step of waiting for the reception of the synchronization timing signal from the first drive control command device, The step of performing processing for controlling the position and speed of the drive control device that controls the drive unit by receiving the synchronization timing signal, the step of determining whether the synchronization state is good, and the state of good synchronization In the case of executing the synchronous operation, and the step of outputting an error signal to the first drive control command device when the synchronous state is insufficient, stopping the synchronous operation, and outputting a synchronization deviation alarm. A synchronous control method for a drive control command device, comprising: a step of determining whether or not the synchronous operation ends during operation execution; and a step of stopping the synchronous operation and ending the synchronous operation when the synchronous operation ends. . 5. A microcomputer, an operating clock generating means for generating an operating clock, an interrupt generating means for outputting an interrupt signal to the microcomputer in each cycle of the operating clock, and a first drive control command device. Station number setting means for setting a station number indicating whether to operate or as a second drive control command device, and parallel data from the microcomputer that operates when it becomes the first drive control command device to serial data Parallel / serial data converting means for converting into serial data, and serial for converting the serial data received from the first drive control command device into parallel data so as to be operated by the microcomputer when operating as the second drive control command device. / Parallel data converter and parallel / serial data converter Shift clock generating means for outputting a shift clock that takes timing for transmitting or receiving serial data by the stage or the serial / parallel data converting means, and the second drive control commanding device which operates to receive dually. A microcomputer for comparing the serial data to check whether there is any abnormality, and at the same time, for recognizing an operation mode for switching the operation state from asynchronous operation to synchronous operation or from synchronous operation to asynchronous operation. In the case of the first drive control command device, synchronous control is performed while outputting a movement start signal, and in the case of the second drive control command device, synchronous control is performed by input of the movement start signal. Drive control command device. 6. A step of determining whether the drive control command device is set as the first drive control command device or the second drive control command device, and the step of setting the drive control command device as the first drive control command device. Output of serial data to the second drive control command device, the step of determining the preparation completion of the second drive control command device, and the position and speed of the drive control device controlling the drive unit. To execute the process for controlling, the step of determining whether or not the synchronization state is good, the step of performing the synchronous operation when the synchronization state is good, and the synchronous operation when the synchronization state is insufficient. To output a synchronization error alarm, a step of determining whether or not the synchronous operation ends during execution of the synchronous operation, and in the case of ending the synchronous operation, the serial data is sent to the second drive control command device. output To stop the synchronous operation and end the synchronous operation, and when set as the second drive control command device, wait for the reception of serial data from the first drive control command device, and the operation Execute the preparation and output the operation preparation completion to the first drive control command device upon completion, and execute the process for controlling the position and speed to the drive control device that controls the drive unit by receiving the serial data , A step of determining whether or not the synchronization state is good, a step of executing the synchronous operation when the synchronization state is good, and an error signal to the first drive control command device when the synchronization state is insufficient. Is output and the synchronous operation is stopped and a synchronization deviation alarm is output, a step of determining whether or not the synchronous operation is completed during execution of the synchronous operation, and a synchronous operation is stopped when the synchronous operation is completed. Synchronous control method for the drive control commanding unit having the steps of synchronizing the operation end. 7. A microcomputer, an operating clock generating means for generating an operating clock, an interrupt generating means for outputting an interrupt signal to the microcomputer in each cycle of the operating clock, and as a first drive control command device. Station number setting means for setting a station number indicating whether to operate or as the second drive control command device, and a synchronization timing based on the operation clock that operates only when used as the first drive control command device. Synchronous timing signal transmitting means for outputting a signal, and an error status signal which operates only when used as a second drive control command device and indicates a preparation state or a synchronous state of a synchronous operation and receives from the first drive control command device Synchronization control means for outputting a synchronization operation start signal based on the synchronized timing signal, and a second drive control finger. Synchronization check means for determining whether the operation of the command device is synchronized with the operation of the drive control command device of the first drive control command device, and an error signal generation means for outputting an error signal based on an error status signal, Parallel / serial data conversion means for outputting a request signal requesting position data transmission to the position detection means in response to request data from the microcomputer when the first drive control command device is received, received from the position detection means A drive control command device comprising serial / parallel data conversion means for converting the serial position data into parallel data and communication check means for checking that the previous position data has been normally input. 8. An error signal generating means and an error signal used for synchronization check in order to notify the first drive control command device of the occurrence of a communication error when a communication error occurs in the second drive control command device. 8. The drive control command device according to claim 7, wherein the drive control command device is shared. 9. In a system comprising one position detecting means and a plurality of drive control command devices, the first drive control command device sends a synchronization timing signal and a movement start signal to the second drive control command device. Along with outputting, a request signal is output to the position detecting means, synchronous operation is executed in synchronization with the position data from the position detecting means, and the second drive control command device is from the first drive control command device. The operation clock is synchronized with the first drive control command device based on the received synchronization timing signal, and synchronous operation is executed in synchronization with the received movement start signal and position data from the position detection means. A synchronous control system for a drive control command device, comprising: 10. A step of transmitting, to the position detecting means, a request signal requesting position data and alarm information required for synchronous operation to the position detecting means when set as the first drive control command device, A step of waiting for reception of position data in response to the request signal from the position detection means, a step of determining whether or not the reception of the position data including the second drive control command device is normally performed, When the reception is successful, the position data cannot be received, and a certain period of time is waited until the next position data is read. If the position data reception is abnormal, the retry count is further determined and the retry is performed. If the number of times is within the set number of times, return to the stage of transmitting the above request signal to the position detecting means, and if the number of retries is greater than or equal to the set number of times, output an alarm. A step of stopping the synchronous operation and ending the processing; a step of waiting for reception of position data in response to the request signal from the position detection means, when the second drive control command device is set; A step of determining whether or not the reception of the position data has been normally performed, a position data reception is disabled when the reception of the position data is normally performed, and a step of waiting for a certain period of time until the next position data is read, If the reception of the position data is abnormal, the number of retries is further determined, and if the number of retries is within a set number of times, return to the stage of waiting for the reception of the position data for the request signal from the position detection means, If the number of retries is greater than or equal to the set number, an alarm is output, synchronous operation is stopped, and processing is terminated. Synchronous control method for the drive control commanding unit only control command device is characterized in that to receive the new position data.