JPH0221486A - Dual port memory device - Google Patents

Abstract

PURPOSE:To efficiently perform a processing using a dual port memory device by providing a means to hold an arithmetic code for an arithmetic means or the value of mask data transiently. CONSTITUTION:At a logical operation circuit 4, the logical operation of external data and data in the device is executed based on the arithmetic code inputted from an address line 6 via an arithmetic code latch 11, and an executed result is outputted to a random access port 2. Here, the arithmetic code latch 11 and a mask clutch 10 function as the holding means for the arithmetic code and the mask data, and the arithmetic code latch 11 is formed in structure where, for example, it is constituted of four bits and it can set the arithmetic does of an AND, an OR, and an EOR, etc. Thereby, it is possible to hold the arithmetic code and the mask data at a specific time and to store the preceding state of the processing at the time of switching a task or a processor, therefore, the processing by a multitask or a multiprocessor can be performed, and the processing can be performed efficiently.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dual port memory device used as a display frame memory, and particularly to a technique suitable for multitasking processing or access by a multiprocessor.

[Conventional technology]

An example of this type of dual-port memory device described is Nikkei Electronics (NO, 391), published by Nikkei McGraw-Hill, March 24, 1986.
There is an image dual-port memory J (P243-264) in the 256 that incorporates a raster calculation function and also has a serial input function.

As described in the above-mentioned literature, recent dual-port memory devices tend to have higher functionality by adding logical operation functions and write mask functions.

[Problem to be solved by the invention]

The dual-port memory device described in the above document is considered to be optimal for use as a frame memory for display hardware, but when considering access from multiple processors or multitasking processing, The inventor has discovered that there are some points in which sufficient functionality cannot be exhibited.

For example, if we assume a multitasking environment in which the frame memory configured with the dual port memory elements described above is accessed in a time-sharing manner by multiple processors such as a main processor and a graphic processor, or by multiple tasks, the dual port memory elements configured once Not enough consideration has been given to how to manage logical operation codes or mask data when tasks are switched.

Although it is conceivable to realize the above management by software, this is not practical in a display system that requires high speed because the display speed decreases.

Therefore, the dual-port memory device has generally been used in such a way that no other display task is executed until the - group display task is completed.

The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a technology that can realize efficient processing using a dual-port memory element.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, it has a calculation means that performs a logical operation on data read through a random port and mask data from the outside, and a holding means that can temporarily hold the value of the operation code or mask data for the calculation means. However, it is possible to read and write the value of the logic code or mask data at a specific point in time in the holding means by access from a host device.

[Effect]

According to the above-mentioned means, since it becomes possible to store the operation code or mask data at the time of task switching under the control of the host device, it becomes possible to use multi-task processing or task switching using a multi-processor configuration. Efficient processing using dual port memory elements, such as image display processing, can be realized.

〔Example〕

FIG. 1 is a block diagram showing the configuration of a dual port memory device according to an embodiment of the present invention, FIG. 2 is a timing chart showing the control state of the dual port memory device, and FIG. 3 is a block diagram showing the configuration of the dual port memory device. FIG. 4 is a system configuration diagram showing a case where the device is used as a frame memory of a display device, and FIG. 4 is an explanatory diagram showing a task switching state.

As shown in FIG. 1, the dual port memory device 1 of this embodiment has a random access port 2 as a memory main body.
and a serial access port 3, and a logic operation circuit 4 as an operation means and an input/output control section 5 are provided for the random access port 2.

The random access port 2 side is equipped with a 64K×4 bit input/output port, and has eight address lines 6 and four data lines 7. On the other hand, the serial port side is equipped with a 4-bit input/output port and has four data lines 8.

The data line 7 on the random access port 2 side is connected to the random access port 2 via the input/output control section 5 and the logic operation circuit 4, and the data line 7 is further connected to the input/output control section 5 and the logic operation circuit. 4 and is manually supplied to the random access port 2 via the mask latch 10.

The logic operation circuit 4 executes a logic operation between external data and data within the element based on the operation code input from the address line 6 through the operation code latch 11, and sends the execution result to the random access port 2. The structure is such that it is output.

Here, the operation code latch 11 right and the mask latch function as means for holding the operation code and mask data, and the operation code latch 11 has, for example, 4
AND, OR with bit configuration.

It has a structure in which operation codes such as EOR can be set.

The random access port 2 has RΔ5SCAS and WE control lines as a control system, and these control procedures are similar to those of a normal DRAM.

The functions of the dual-port memory device 1 of this embodiment include a logical operation function that performs a logical operation between data originally stored in the device and externally written data, and a logical operation function that writes data bit by bit. It also has a possible light mask function.

Here, the operation code and mask data settings are
As shown in the figure, first, before activating RAS,
This is performed by activating AS and WE, externally placing an operation code on the lower four bits of address line 6, and placing mask data on data line 7. Through the above operating procedure, the operation code is set in the operation code latch 11, and the mask data is set in the mask latch 10.

Note that by setting the mask latch 10 to "0", the bit functions as a write mask.

In accordance with the arithmetic code and mask data set as described above, the arithmetic processing and write mask function will work in subsequent writing to the random access port 2.

Subsequently, the reading of the operational code and mask data, which is a characteristic feature of this embodiment, is performed as follows.

First, as shown in FIG. 2, by activating CAS and OE before RAS becomes active, the operation code set in the operation code latch 11 for the lower 4 bits of the address line 6 is activated. is output. Further, the mask data set in the mask ratchero is output to the data line 7.

As described above, it becomes possible to read out the operational code and mask data that have been previously set for the dual port memory element 1 from the outside.

Next, the dual port memory element 1 is transferred to the display device 15.
The case of using the frame memory 13 as the frame memory 13 will be explained with reference to FIGS. 3 and 4.

In FIG. 3, the dual port memory device 1 described above is connected as a frame memory 13 to a central processing unit 14 (CPU) on its random access port 2 side and to a display device 15 on its serial access port 3 side. There is. In other words, the frame memory 13 is the central processing unit 1
4 writes and reads display data, and outputs the display data to a display device 15 such as a CRT monitor.

Here, further explanation will be given assuming that a plurality of display tasks are executed in the display system as shown in FIG. 3 above.

FIG. 4 shows a state in which the processing of the management monitor and display tasks A and B for managing multitasks in the central processing unit 14 is sequentially switched over in chronological order.

In the figure, first, the occupied time of the display task A ends, and the time is switched to the management time of the task management monitor.

At this time, the task management monitor reads out the logical operation code and mask data in the frame memory 13 at the time of completion of execution of the display task A from the operation code latch 11 and mask latchero in the dual port memory element 1, and applies the same to the display task. Store it as information. The procedure for reading data from the operation code latch 11 and mask latch 10 is as described above.

Next, display task B from the management time on the task management monitor.
Then, the processing in the display task B is executed on the frame memory 13. When the time occupied by the display task ends, the time is switched to the management time of the task management monitor again. At this time, the task management monitor reads out the logical operation code and mask data in the frame memory 13 at the time of completion of execution of the display task B from the operation code latch 11 and mask latch 10 in the dual port memory element 1 in the same manner as described above. It is stored as display task B information. Next, within the same time, the task management monitor retrieves the logic code and mask data of the display task A stored in the previous cycle, and stores the logic code latch and mask latch lO in the dual port memory element l of the frame memory 13.
Set for. The setting procedure is as described above. Thereafter, the occupied time of display task A is reached again, and the display processing in display task 8 is restarted based on the logic code and mask data reset above.

As described above, according to this embodiment, the operation code latch 11
By providing a mask latch error and a mask latch error, it is possible to read and write data stored at a specific point in time from both latches, making it possible to retain the operation code and mask data at that specific point in time. Since the state of processing can be stored, multitasking or multiprocessor processing becomes possible, and efficient processing is realized.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, in the embodiment, dual port memory device 1 (
Although the case where the frame memory 13) is accessed by multitasking processing has been described, it may also be accessed by a multiprocessor system using a main processor and a graphic processor, for example.

In the above description, the invention made by the present inventor was mainly applied to a dual port memory element used as a frame memory in a so-called display system, which is the field of use thereof, but the invention is not limited to this. It may also be a dual port memory device used for other purposes.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, according to the present invention, since the operation code or mask data is retained even when switching tasks, it is possible to perform multi-task processing or use task switching using a multi-processor configuration, and efficient processing using dual-port memory devices is possible. It is possible to realize processing such as image display processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a dual-port memory device according to an embodiment of the present invention, FIG. 2 is a timing chart showing the control state of the dual-port memory device according to the embodiment, and FIG. Figure 314 is an explanatory diagram showing the task switching state in the embodiment. 1... Dual port memory element, 2... Random access port, 3... Serial access port, 4
...Logic operation circuit, 5...Input/output control section, 6...
Address line, 7.8...Data line, 10...Mask latch, 11...Operation code latch, 13...Frame memory, 14...Central processing unit (CPU), 1
5...Display device. Mask data chart

Claims (1)

[Claims] 1. Equipped with a random port that can write in bits and a serial port that inputs and outputs time-series data, and performs logical operations on the data read through the random port and external mask data. It has an arithmetic means and a holding means that can temporarily hold the value of the operation code or mask data for the arithmetic means, and the value of the logic code or mask data at a specific time in the holding means is accessed from a host device. A dual port memory device characterized by being readable and writable.