JPH022133A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To allow a shallow junction to be formed at a base area with improved controllability without increasing junction capacity even if contact resistance is reduced by providing a base contact area to be connected to the base area on the collector area onto an insulation separated area provided at the periphery of the collector area. CONSTITUTION:A collector area is formed on an N-type epitaxial layer (N epitaxial layer) on an N+Si substrate 1 and an SiO2 film 3 is accumulated. The upper surface of the N epitaxial layer 2 is exposed, an Si layer containing B is allowed to grow over the entire surface, and then a P epitaxial layer 4 and a P-type polycrystal Si layer 5 are formed. The P polycrystal Si layer 5 is selectively oxidized to form an SiO2 film 6. After performing ion impregnation of a polycrystal Si layer 7, a nitriding Si film 8 is accumulated. The nitriding Si film 8 and the polycrystal Si layer 7 at areas other than the P-type epitaxial layer 4 are removed and an SiO2 film 9 are accumulated. Then, the upper surface of the nitriding Si film 8 is exposed, a contact hole 10 is provided on the P polycrystal Si layer 5, B ion is impregnated, and annealing is performed. And then, the nitriding Si film 8 is eliminated and a bipolar transistor is formed where the N epitaxial layer 2 forms collector area, the P epitaxial layer forms base area, the P polycrystal Si layer 5 forms base contact are, and the N polycrystal Si layer 7 forms emitter.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device having an ultra high speed/ultra high frequency transistor.

[Conventional technology]

Techniques for manufacturing ultra-high-speed transistors include forming a shallow base region, reducing base resistance, and reducing junction capacitance. Conventionally, methods for forming a shallow base region include:
There are methods such as introducing impurities by lowering the accelerating voltage through an oxide film or the like during ion implantation, or performing short-time diffusion at low temperatures.

Further, as a means for reducing the base resistance, there is a method of increasing the impurity concentration in the base contact region. Further, as a means for reducing the junction capacitance, there is miniaturization, and one of the methods is self-alignment.

[Problem to be solved by the invention]

In the conventional semiconductor device manufacturing method described above, when using ion implantation to form a shallow base region, shallow junctions can be made by lowering the impurity concentration, but the drawback is that the base resistance increases. Although the low-temperature, long-duration diffusion method can form shallow junctions, it has the disadvantage of poor controllability. In addition, the reduction in junction capacitance is addressed by reducing the junction area through miniaturization, but even in the self-aligning process, the base contact region is formed in the semiconductor substrate and has a low resistance. If the concentration is high, it will be diffused deeper into the semiconductor substrate than in the intrinsic base portion, resulting in an increase in junction capacitance.

[Means to solve the problem]

A method for manufacturing a semiconductor device according to the present invention includes the steps of providing a region of one conductivity type on a semiconductor substrate, and a step of selectively providing an insulating isolation region in the region of one conductivity type to define a collector region.
forming a first semiconductor layer of an opposite conductivity type on a surface including the collector region; and selectively insulating and separating the first semiconductor layer to connect it to a base region on the collector region and the base region. A step of defining a base contact region, and sequentially stacking a second semiconductor layer of one conductivity type and an insulating film on the surface including the base region, and selectively and sequentially etching them to form an emitter region on the base region. forming a contact hole for the base contact region by opening the insulation isolation region on the base contact region; and diffusing an opposite conductivity type impurity into the base contact region of the contact hole. It consists of:

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1A to 1F are cross-sectional views of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1(a), an N-type epitaxial layer 2 is formed on an N+-type silicon substrate 1, and the N-type epitaxial layer 2 is selectively anisotropically etched to form an element isolation region. N-type epitaxial layer 2 is removed to form a collector region. Next, after thermal annealing is performed to recover the surface damage caused by etching, a silicon oxide film 3 is deposited on the entire surface by low pressure CVD, and a photoresist film is applied on the silicon oxide film 3 to flatten the surface. . next,
The entire surface is etched flat by an etch-back method to expose just the uppermost surface of the N-type epitaxial layer 2, so that the silicon oxide film 3 is buried in the element isolation region.

Next, as shown in FIG. 1(b), a silicon layer containing boron at a concentration of I x 101 g to l x 1019 cm -3 is grown to a thickness of 0.1 μm on the entire surface by MBE method, and an N-type epitaxial layer is grown. P-type epitaxial M4 on layer 2 and P-type polycrystalline silicon 5 on silicon oxide film 3
form.

Next, as shown in FIG. 1C, the P-type polycrystalline silicon layer 5 is selectively oxidized to form a silicon oxide film 6 to define a base region. Next, a polycrystalline silicon layer 7 is formed on the entire surface.
Acceleration energy 50-70keV, dose 1xlO
Ion implantation is performed at 2×10”Ω−2. Next, silicon nitride M8 is deposited on the polycrystalline silicon layer 7 by low pressure CVD.

Next, as shown in FIG. 1(d), the silicon nitride film 8 and the polycrystalline silicon layer 7 are selectively and sequentially etched to remove P.
The silicon nitride film 8 and the polycrystalline silicon layer 7 other than the upper part of the mold epitaxial layer 4 are removed.

Next, as shown in FIG. 1(e), a silicon oxide film 9 is deposited by low pressure CVD.

Next, as shown in FIG. 1(f), after coating the entire surface with a resist film to flatten the surface, the entire surface is etched back, leaving just the top surface of the silicon nitride film 8 exposed. Flatten the surface. Next, the silicon oxide film 9 on the P-type polycrystalline silicon layer 5 is selectively etched using photolithography technology to form a contact hole 1o.
In order to reduce the contact resistance, ions of boron, for example, are implanted into the P-type polycrystalline silicon N5 in the 1° contact hole, and then thermal annealing is performed to remove arsenic in the N-type polycrystalline 9932 layer 7 and the P-type polycrystalline silicon layer 5. Activates boron. Next, the silicon nitride M8 is removed, and the N-type epitaxial layer 2 is used as the collector region, the P-type epitaxial layer 4 is used as the base region, and the P-type polycrystalline silicon layer 5 is used as the base contact region. A bipolar transistor is constructed using the polycrystalline 9932 layer 7 as an emitter.

Here, the P-type polycrystalline silicon layer 5 is SOI (Sem
l-conductor on In5ulator)
Alternatively, the polycrystalline silicon layer 7 may be an epitaxial layer. Further, the silicon oxide film 3 may be formed by selectively oxidizing the N-type epitaxial layer M2.

FIGS. 2(a) to 2(h) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a second embodiment of the present invention.

First, as shown in FIG. 2(a), a P-type semiconductor substrate 11
An N1 type buried layer 12 is selectively formed on the surface of the substrate, and an N type epitaxial layer 2 is grown on the surface including the N+ type buried layer 12.

Next, as shown in FIG. 2(b), a silicon oxide film 3 for element isolation is selectively buried in the N-type epitaxial layer 2 by the same method as in the first embodiment, and a collector region is formed. 13 and a collector contact region 14 are formed. Next, a silicon nitride film 15 is formed on the entire surface by low pressure CVD, and this is selectively etched to open the silicon nitride film 15 above the collector contact region 14. next,
Using the silicon nitride film 15 as a mask, phosphorus is diffused into the collector contact region 14.
to a high concentration.

Next, as shown in FIG. 2(c), the silicon nitride film 15
is removed, and P is applied to the surface including the collector region 13 and collector contact region 14 by the same method as in the first embodiment.
A mold silicon layer 16 is formed.

Next, as shown in FIG. 2(d), the P-type silicon layer 16
A silicon oxide film 6 is selectively provided on the P-type silicon layer 1.
6 to form a base region on the collector region 13.

Next, as shown in FIG. 2(e), an N-type polycrystalline silicon film 7 and a silicon nitride film 8 are sequentially deposited on the surface including the P-type silicon layer 16.

Next, as shown in FIG. 2(f), the silicon nitride film 8 and the N-type polycrystalline silicon [7] are selectively and sequentially etched to form an emitter region on the base region of the P-type silicon layer 16.

Next, as shown in FIG. 2(g), a silicon oxide film 9 is deposited on the surface including the emitter region.

Next, as shown in FIG. 2(h), a resist film is applied on the silicon oxide film 9 to flatten the surface, and the entire surface is etched back to expose just the top surface of the silicon nitride film 8. Flatten the surface. Next, a contact hole 10 is formed in the silicon oxide film 9 on the P-type silicon layer 16 in the base region, and then boron ions are implanted into the silicon oxide film 9 in the contact hole 10 and activated by thermal annealing. Next, the silicon oxide film 9 on the collector contact region 14 is selectively etched to form a contact hole 17 for a collector contact, thereby forming a bipolar transistor suitable for an integrated circuit.

〔Effect of the invention〕

As explained above, the present invention lowers the contact resistance in the base contact region by providing the base contact region connected to the base region provided on the collector region on the insulation isolation region provided around the collector region. The junction capacitance does not increase even when a high concentration of impurities is introduced into the base region, and a shallow junction with a steep impurity concentration distribution can be formed in the base region with good control. It has the effect of being able to be manufactured.

[Brief explanation of the drawing]

FIGS. 1(a) to (f) and FIGS. 2(a) to (h) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first and second embodiments of the present invention. DESCRIPTION OF SYMBOLS 1...N+ type silicon substrate, 2...N type epitaxial layer, 3...Silicon oxide j model, 4...P type epitaxial layer, 5...P type polycrystalline silicon layer, 6・・・
・Silicon oxide film, 7... N-type polycrystalline silicon layer, 8
...Silicon nitride film, 9...Silicon oxide film, 10
... contact hole, 11 ... P type silicon substrate, 12 ... N + type buried layer, 13 ... collector region,
14... Collector contact region, 15... Silicon nitride film, 16... P-type silicon layer, 17... Contact hole. Figure 2 N-D = ° Storage Sole 7 Le Counterfeit AP Type Works ° 7〒Sial Tatami

Claims (1)

[Claims] a step of providing a region of one conductivity type on a semiconductor substrate; a step of selectively providing an insulating isolation region in the one conductivity type region to define a collector region; and a step of providing a first conductivity type region on a surface including the collector region. a step of forming a semiconductor layer; a step of selectively insulating and isolating the first semiconductor layer to define a base region on the collector region and a base contact region connected to the base region; a step of sequentially stacking a second semiconductor layer of one conductivity type and an insulating film on the surface and selectively and sequentially etching them to provide an emitter region on the base region; and a step of forming the insulating film on the base contact region. A semiconductor device comprising the steps of: opening a body isolation region to form a contact hole in the base contact region; and selectively diffusing an opposite conductivity type impurity into the base contact region of the contact hole. manufacturing method.