JPH02213139A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable the thickness of an N<->-type epitaxial layer to be thinned further than that in the conventional constitution while securing the breakdown strength of base-collector junction by forming an N<+>-type buried diffusing region in a subcollector formation planned region, and thereon forming an N<->-type epitaxial layer through a P-type epitaxial layer. CONSTITUTION:An N<+>-type buried diffusing region 3 is formed in the subcollector formation planned region of an NPN transistor on a P-type semiconductor substrate 1, and a P-type epitaxial layer 4 is formed on said P-type semiconductor substrate 1, and an N<->-type epitaxial layer 5 is formed on the P-type epitaxial layer 4, whereby the upward diffusion length within the N<->-type epitaxial layer 5 ln the N<+>-type buried diffusing region 3 is restrained, and without lowering the breakdown voltage at reverse bias application to the base-collector junction of said NPN transistor, the thickness of the N<->-type epitaxial layer 5 is thinned and the diffusion length in depth direction of a P-type isolating region 6 is shortened so as to decrease lateral diffusion length, whereby said NPN transistor is made high-speed and the element area is reduced.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention is directed to the manufacture of bipolar semiconductor integrated circuits that can increase the speed of NPN transistors and reduce the device area by using an epitaxial layer with a 2M structure. It is about the method.

(Prior Art) Bipolar integrated circuits are characterized by high speed compared to MO3 integrated circuits, and there is a wide demand for the production of bipolar integrated circuits equipped with faster NPN transistors.

NPN transistors in bipolar integrated circuits are N+ type (sheet resistance approximately 20Ω10) on a P-type semiconductor substrate in order to form a low-resistance subcollector region with high base-collector junction breakdown voltage and excellent high frequency response. The buried diffusion region is formed as a low-resistance subcollector, and an N-type (specific resistance of about 1 Ω-1) high-resistance epitaxial layer is further formed on a P-type semiconductor substrate.

One of the methods used to improve the high-speed performance of NPN transistors is to reduce the thickness of the N-type epitaxial layer to reduce the parasitic resistance of the collector and the parasitic capacitance between the collector and isolation. Ta. Furthermore, by reducing the thickness of the N'' type epitaxial layer, the diffusion length in the depth direction of the P type isolation region can be shortened by the amount that the N'' type epitaxial layer is thinned. Therefore, it is possible to reduce the lateral diffusion length of the P-type isolation region by the same amount as this, reducing the device area and reducing the parasitic capacitance between the collector of the NPN transistor and the P-type semiconductor substrate and the aluminum wiring capacitance. In addition, by reducing the chip area of the integrated circuit, it is possible to reduce the cost per chip and improve the yield.

(Problems to be Solved by the Invention) Due to the autodoping and reverse diffusion during the formation of the N-type epitaxial layer, and the thermal history caused by the semiconductor manufacturing process after the formation of the N-type epitaxial layer, the so-called "N
Due to this rise, the N-type impurity concentration profile of the collector directly under the active base of the NPN transistor becomes 5N0.
The height increases gradually toward the mold-embedded diffusion region. In such a profile, if the thickness of the N-type epitaxial layer is reduced in order to increase the speed of the NPN transistor, the impurity concentration in the collector of the base-collector junction will increase, causing breakdown of the base-collector junction. The voltage gradually decreases. Therefore, the thickness of the N-type epitaxial layer can only be reduced within a range that can ensure the withstand voltage required for the base-collector junction.

An object of the present invention is to provide a method of manufacturing a semiconductor device that allows the thickness of an N-type epitaxial layer to be made thinner than that of a conventional structure while ensuring the above-mentioned breakdown voltage.

C': Means for Solving Problem a) The method for manufacturing a semiconductor device of the present invention includes forming an N0-type buried diffusion region in a region where a sub-collector of a P-type semiconductor Qls board is to be formed, an NPN transistor transistor; P on a P-type semiconductor substrate
By forming a type epitaxial layer and forming an N-type epitaxial layer on this P-type epitaxial layer,
By suppressing the upward diffusion length of the N9 type buried diffusion region in the N- type epitaxial layer, the NPN transistor can be
The thickness of the − type epitaxial layer is reduced, and the P type portion is 11
By shortening the diffusion length in the depth direction in the 1 m region and reducing the lateral diffusion length, the speed of the NPN transistor is increased, and
This is to reduce the element area.

(Function) Compared to the conventional configuration of the bipolar integrated circuit manufacturing method, 1
As in the present invention, by forming a P-type epitaxial layer between a P-type semiconductor substrate and an N-type epitaxial layer, the thickness of the formed P-type epitaxial layer increases the thickness of the N0-type buried layer, which is the sub-collector of the NPN transistor. This means that the rise of the embedded diffusion region is suppressed, and while the breakdown voltage between the base and collector of the NPN transistor is kept the same as that of the conventional method, the thickness of the epitaxial layer can be reduced compared to that of the P-type epitaxial layer formed by the conventional method. It is possible to reduce the thickness of the layer.

(Example) An example of the present invention will be described based on FIGS. 1 and 2.

FIG. 1 is a sectional view of the NPN transistor portion of a bipolar semiconductor integrated circuit obtained by the manufacturing method of the present invention, and FIG. 2 is a process flowchart of an embodiment of the present invention.

As shown in FIG. 2(a), N on the P-type silicon substrate 1
An oxide film pattern 2 is formed in the region where the sub-collector of the PN transistor is planned to be formed using normal photolithography technology, and an N0 type buried diffusion region 3 with a sheet resistance of about 20Ω/hole is formed using the oxide film 1 and the cover pattern 2 as a mask. After forming the N1 type buried diffusion region 3, the oxide film pattern 2 is completely removed.

Next, as shown in FIG. 2(b), a P-type epitaxial layer 4 is formed on the P-type silicon substrate 1 in which the N1-type buried diffusion region 3 has already been formed. The specific resistance of the P-type epitaxial M4 is about the same as the specific resistance of the P-type silicon substrate 1, which is 5 to 15Ω.
1, and when forming the P-type epitaxial layer 4, the N″′-type buried diffusion region 3 is formed by lateral autodoping.
An N-type layer is not formed at the interface where the P-type silicon substrate 1 and the P-type epitaxial layer 4 are in direct contact without intervening. Furthermore, the thickness of the P-type epitaxial layer 4 is determined such that the tip of the raised portion of the N1-type buried diffusion region 3 is determined at the time when all heat treatments of 900"C or higher are completed during the manufacturing process of the semiconductor integrated circuit. Plf:!The thickness should be less than or equal to the thickness that can penetrate the epitaxial layer 4.

Next, as shown in FIG. 2(e), a normal N-type epitaxial layer M5 having a specific resistance of about 1 Ω-1 is formed on the top of the L]-type epitaxial layer 4.

Next, as shown in FIG. 2(d), a P-type isolation diffusion region 6, a P-type isolation diffusion region 6, a P-type isolation diffusion region 6, a P-type isolation diffusion region 6, a P-type
Mold base area7. An N0 type emitter region 8 and an N9 type collector contact region 9 are formed by a conventional method, and after i&, oxidation [10] is processed using photolithography to form a contact window. Furthermore, by forming aluminum wiring 11, an NPN transistor as shown in FIG. 1 is completed.

(Effects of the Invention) According to the method of manufacturing a semiconductor device of the present invention, the withstand voltage determined by the breakdown voltage of the base-collector junction of the N I''N transistor is the same as that of the conventional structure.

In addition, it is possible to manufacture an NPN transistor in which the N-type epitaxial layer and the thickness of the axial layer are thinner than those of the conventional structure, and therefore, the withstand voltage between the base and collector of the NPN transistor is the same as that of the conventional structure, and It is possible to manufacture bipolar integrated circuits in which the speed of the NPN transistor is faster than that of the conventional structure and the element area is smaller than that of the conventional structure, and the practical effects thereof are extremely large.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of an NPN transistor portion of a semiconductor device according to an embodiment of the present invention, and FIGS. 2(a) to 2(d) are flowcharts of the steps of the present invention. 1... P-type silicon substrate, 2... Oxide film. 3... N" type buried diffusion region, 4... P type epitaxial layer, 5... N- type epitaxial layer,
6...P-type isolation diffusion region, 7...P-type base region, 8...N0-type emitter region, 9...N1-type collector contact region, 10...oxide film, 11...
・Aluminum wiring. Figure 1 Patent Applicant: Matsushita Electronics Co., Ltd. i-, -p-type silicon base layer 3-...N1 vertical layer 4-, P-type epitaxial layer 5, -N-type epitaxial layer Layer 6-P type combination 11it broad length length 7...-P type hez 4 suffix 8-N+ type emitter 9 now negative 9-N medium size/79 conductor 4 member i 10-・・Oxide film 11−・・Aluminum stripe

Claims (1)

[Claims] An N^+ type buried diffusion region is formed in the region where the sub-collector of the NPN transistor is to be formed on the P-type semiconductor substrate, and
By forming a P type epitaxial layer on a type semiconductor substrate and forming an N^- type epitaxial layer on the P type epitaxial layer, the N^- type epitaxial layer in the N^+ type buried diffusion region is formed. The thickness of the N^- type epitaxial layer can be reduced without reducing the breakdown voltage of the base-collector junction of the NPN transistor when reverse bias is applied, and the thickness of the P-type isolation region can be reduced. By shortening the diffusion length in the depth direction and decreasing the diffusion length in the lateral direction,
A method of manufacturing a semiconductor device, characterized in that the speed of the NPN transistor is increased and the element area is reduced.