JPH0220906A - Emitter follower circuit - Google Patents

Emitter follower circuit

Info

Publication number
JPH0220906A
JPH0220906A JP63171278A JP17127888A JPH0220906A JP H0220906 A JPH0220906 A JP H0220906A JP 63171278 A JP63171278 A JP 63171278A JP 17127888 A JP17127888 A JP 17127888A JP H0220906 A JPH0220906 A JP H0220906A
Authority
JP
Japan
Prior art keywords
input
output
transistor
input side
side transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63171278A
Other languages
Japanese (ja)
Inventor
Hirokatsu Mizuki
水木 啓勝
Akifumi Ide
井手 章文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63171278A priority Critical patent/JPH0220906A/en
Publication of JPH0220906A publication Critical patent/JPH0220906A/en
Pending legal-status Critical Current

Links

Landscapes

  • Amplifiers (AREA)

Abstract

PURPOSE:To equalize base-emitter voltages of input and output side transistors and to reduce a distortion between input and output voltages by supplying a current having the same magnitude as that of a current flowing to the input side transistor, to the output side transistor by a current mirror circuit. CONSTITUTION:An input voltage, an output voltage, a base-emitter voltage of an input side transistor 3, a base-emitter voltage of an output side transistor 4, a current flowing to the input side transistor 3, and a current flowing to the output side transistor 4 are denoted as VIN, VOUT, VBEIN, VBEOUT, IIN and IOUT, respectively. In this case, when an input side resistance 5 is denoted as RIN, IIN=(VIN-VBEIN)/RIN is derived, and depends on the input side resistance 5. When a current amplification factor hFE is the infinite, since each base-emitter voltage of the input side and the output side transistors 3, 4 in a current mirror circuit is equal, IOUT becomes equal to IIN. Accordingly, VBEIN and VBEOUT also become equal, and VOUT becomes equal to VIN. In such a way, a distortion between input and output voltages can be reduced.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体回路技術分野のエミッタフォロア回路
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to emitter follower circuits in the field of semiconductor circuit technology.

従来の技術 従来のエミッタフォロア回路では、入出力の直流電圧レ
ベルを揃える為に、NPN型、PNP型のトランジスタ
各1個を、入力側、出力側の2段に接続する構成となっ
ていた。以下では、従来のエミッタフォロア回路につい
て、その構成と動作を説明する。
BACKGROUND OF THE INVENTION Conventional emitter follower circuits have a configuration in which one NPN type transistor and one PNP type transistor are connected to two stages, one on the input side and one on the output side, in order to equalize the input and output DC voltage levels. The configuration and operation of a conventional emitter follower circuit will be described below.

第2図は従来のエミッタフォロア回路を示す回路図であ
る。第2図A、Bにおいて、17 、25は入力端子、
18.26は出力端子、19 、27は入力側トランジ
スタ、20.28は出力側トランジスタ、21.29は
入力側抵抗、22.30は出力側抵抗、23は入力側ト
ランジスタを流れる電流、24は出力側トランジスタを
流れる電流である。又、第2図Aと第2図Bの回路構成
は、NPN型とPNP型のトランジスタの極性を逆にし
だもので、基本的には動作原理が同じものである為、以
下第2図Aについての説明を行なう。
FIG. 2 is a circuit diagram showing a conventional emitter follower circuit. In Fig. 2A and B, 17 and 25 are input terminals;
18.26 is the output terminal, 19 and 27 are the input side transistors, 20.28 is the output side transistor, 21.29 is the input side resistance, 22.30 is the output side resistance, 23 is the current flowing through the input side transistor, 24 is the This is the current flowing through the output transistor. In addition, the circuit configurations shown in Figure 2A and Figure 2B are based on the NPN type and PNP type transistors having opposite polarities, and the operating principles are basically the same, so the circuit configurations shown in Figure 2A are as follows. I will explain about this.

以上のように構成されたエミッタフォロア回路において
、入力電圧をVIN −出力電圧を又刃T、入力側トラ
ンジスタのベースエミッタ間電圧をvBEINI”力側
トランジスタのペースエミッタ間電圧をvBEOUT 
とすれば、vOUTは以下のようになる。
In the emitter follower circuit configured as described above, the input voltage is VIN - the output voltage is T, the base-emitter voltage of the input transistor is vBEINI, the base-emitter voltage of the output transistor is vBEOUT
Then, vOUT becomes as follows.

vOUT=vIN−vBEIN+vBEOUTコノ時、
vBEIN ’!:vBEOUT 7”、ホホ等シイ事
より、vOUTは”INにほぼ等しくなυ、エミッタフ
ォロア回路の出力が得られる。
When vOUT=vIN−vBEIN+vBEOUT,
vBEIN'! : vBEOUT 7'', hoho, etc. Therefore, vOUT is approximately equal to IN, and the output of the emitter follower circuit is obtained.

但し、ここで云う入出力トランジスタの特性は等しいも
のとする。
However, it is assumed here that the characteristics of the input and output transistors are the same.

発明が解決しようとする課題 しかしながら上記のような構成では、入力側トランジス
タを流れる電流23が入力側抵抗21に、又出力側トラ
ンジスタを流れる電流24が出力側抵抗22に依存する
為、電流23.24の大きさが必ずしも等しくない。そ
の為、vBEIN とvBEOUTが異なシ、出力電圧
voUTと入力電圧vINの間に歪が生じるという課題
を有していた。
Problems to be Solved by the Invention However, in the above configuration, the current 23 flowing through the input side transistor depends on the input side resistor 21, and the current 24 flowing through the output side transistor depends on the output side resistor 22, so that the current 23. 24 are not necessarily equal in size. Therefore, when vBEIN and vBEOUT are different, there is a problem that distortion occurs between the output voltage voUT and the input voltage vIN.

本発明はかかる点に鑑み、入出力間の歪の小さいエミッ
タフォロア回路を提供する事を目的とする。
In view of this, an object of the present invention is to provide an emitter follower circuit with low distortion between input and output.

課題を解決するだめの手段 本発明は、上記目的を達成するため、出力側トランジス
タに流れる電流量を、入力側トランジスタに流れる電流
量に等しくするカレントミラー回路を備えたことを特徴
とする。
Means for Solving the Problems In order to achieve the above object, the present invention is characterized in that it includes a current mirror circuit that makes the amount of current flowing through the output side transistor equal to the amount of current flowing through the input side transistor.

作  用 本発明は前記した構成によシ、入力側トランジスタに流
れる電流と同じ大きさの電流を、カレントミラー回路に
よって、出力側トランジスタに供給する事により、入出
力側トランジスタのベースエミッタ間電圧を等しくし、
入出力電圧間の歪を小さくする事ができる。
According to the above-described structure, the present invention supplies a current having the same magnitude as the current flowing through the input transistor to the output transistor using a current mirror circuit, thereby reducing the voltage between the base and emitter of the input and output transistor. be equal,
Distortion between input and output voltages can be reduced.

実施例 第1図A、Bは、本発明の実施例におけるエミッタフォ
ロア回路を示す回路図である。第1図A。
Embodiment FIGS. 1A and 1B are circuit diagrams showing an emitter follower circuit in an embodiment of the present invention. Figure 1A.

Bにおいて、1,1oは入力端子、2,11は出力端子
、3,12は入力側トランジスタ、4,13は出力側ト
ランジスタ、5,14は入力側抵抗、6.16はカレン
トミラー回路の入力側トランジスタ、7.16はカレン
トミラー回路の出力側トランジスタ、8は入力側トラン
ジスタを流れる電流、9は出力側トランジスタを流れる
電流である。
In B, 1 and 1o are input terminals, 2 and 11 are output terminals, 3 and 12 are input side transistors, 4 and 13 are output side transistors, 5 and 14 are input side resistors, and 6.16 is the input of the current mirror circuit. 7.16 is the output side transistor of the current mirror circuit, 8 is the current flowing through the input side transistor, and 9 is the current flowing through the output side transistor.

又、第1図Aと第1図Bの回路構成は、NPN型とPN
P型のトランジスタの極性を逆にしだもので、基本的に
は動作原理が同じものである為、以下第1図Aについて
の説明を行なう。
Also, the circuit configurations in Figures 1A and 1B are of NPN type and PN type.
Since this is a P-type transistor with the polarity reversed, and the principle of operation is basically the same, FIG. 1A will be explained below.

以上のように構成されたエミッタフォロア回路において
、入力電圧をvIN、出力電圧をvoUT入力側トラン
ジスタのベースエミッタ間電圧をvBEIN、出力側ト
ランジスタのベースエミッタ間電圧をVBEOUT 、
入力側トランジスタに流れる電流をエエN、出力側トラ
ンジスタに流れる電流をl0UTとする。又、各トラン
ジスタの電流増幅率hFE を無限大とし、入力側、出
力側のトランジスタの特性が同じものとし、カレントミ
ラー回路内の入力側、出力側のトランジスタの特性が同
じものとする。
In the emitter follower circuit configured as above, the input voltage is vIN, the output voltage is voOUT, the base-emitter voltage of the input transistor is vBEIN, the base-emitter voltage of the output transistor is VBEOUT,
Assume that the current flowing through the input side transistor is EN, and the current flowing through the output side transistor is 10UT. Further, it is assumed that the current amplification factor hFE of each transistor is infinite, that the characteristics of the transistors on the input side and the output side are the same, and that the characteristics of the transistors on the input side and the output side in the current mirror circuit are the same.

この時、”INは、入力側抵抗をRIN とすれば、 ”IN:(vIN−VBEIN)/RINとなシ、入力
側抵抗に依存している。電流増幅率hFEが無限大であ
れば、カレントミラー回路内の入力側、出力側トランジ
スタのペースエミッタ間電圧が各々等しい為、l0UT
はIINに等しくなる。従ってvBEINとvBEOU
T も等しくなり、vOUTはvIN と等しくなる・ 以上のように本実施例によれば、カレントミラー回路を
設ける事によシ、入出力電圧間の歪を小さくできる。
At this time, if the input resistance is RIN, then IN: (vIN-VBEIN)/RIN, which depends on the input resistance. If the current amplification factor hFE is infinite, the voltage between the pace emitters of the input side and output side transistors in the current mirror circuit is equal, so l0UT
becomes equal to IIN. Therefore vBEIN and vBEOU
T also becomes equal, and vOUT becomes equal to vIN. As described above, according to this embodiment, the distortion between the input and output voltages can be reduced by providing the current mirror circuit.

発明の詳細 な説明したように本発明によれば、入出力間の歪の小さ
いエミッタフォロア回路が実現でき、その実用的効果は
大きい。
As described in detail, according to the present invention, an emitter follower circuit with low distortion between input and output can be realized, and its practical effects are significant.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図A、Bは本発明における実施例のエミッタフォロ
ア回路を示す回路図、第2図A、Bは従来のエミッタフ
ォロア回路を示す回路図である。 1.1o・・・・・・入力端子、2,11・・・・・・
出力端子、3.12・・・・・・入力側トランジスタ、
4.13・・・・・・出力側トランジスタ、5,14・
・・・・・入力側抵抗、6.16・・・・・・カレント
ミラー回路の入力側トランジスタ、7.16・・・・・
・カレントミラー回路の出力側トランジスタ。
1A and 1B are circuit diagrams showing an emitter follower circuit according to an embodiment of the present invention, and FIGS. 2A and 2B are circuit diagrams showing a conventional emitter follower circuit. 1.1o...Input terminal, 2,11...
Output terminal, 3.12...Input side transistor,
4.13...Output side transistor, 5,14...
...Input side resistance, 6.16...Input side transistor of current mirror circuit, 7.16...
・Output side transistor of current mirror circuit.

Claims (1)

【特許請求の範囲】[Claims] NPN型、PNP型のトランジスタ各1個を、入力側、
出力側の2段に接続する事によって構成されるエミッタ
フォロア回路において、出力側トランジスタに流れる電
流量を入力側トランジスタに流れる電流量に等しくする
カレントミラー回路を備えた事を特徴とするエミッタフ
ォロア回路。
One NPN type and one PNP type transistor on the input side,
An emitter follower circuit configured by connecting two stages on the output side, the emitter follower circuit comprising a current mirror circuit that makes the amount of current flowing through the output side transistor equal to the amount of current flowing through the input side transistor. .
JP63171278A 1988-07-08 1988-07-08 Emitter follower circuit Pending JPH0220906A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63171278A JPH0220906A (en) 1988-07-08 1988-07-08 Emitter follower circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63171278A JPH0220906A (en) 1988-07-08 1988-07-08 Emitter follower circuit

Publications (1)

Publication Number Publication Date
JPH0220906A true JPH0220906A (en) 1990-01-24

Family

ID=15920363

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63171278A Pending JPH0220906A (en) 1988-07-08 1988-07-08 Emitter follower circuit

Country Status (1)

Country Link
JP (1) JPH0220906A (en)

Similar Documents

Publication Publication Date Title
US5057792A (en) Current mirror
KR100239619B1 (en) Voltage-current conversion circuit
US4779059A (en) Current mirror circuit
JPH0770935B2 (en) Differential current amplifier circuit
JPS6057248B2 (en) Amplifier input bias adjustment circuit
JPH0220906A (en) Emitter follower circuit
JPH027715A (en) Circuit device for low distortion switching of signal
JP2647725B2 (en) Voltage comparator
JPH03196279A (en) Operational amplifier
JP2996551B2 (en) Current mirror circuit device
JPS6126848B2 (en)
JP2645403B2 (en) Voltage follower circuit
JPH04132091A (en) Peak hold circuit
JPH05129852A (en) Differential amplifier circuit
JPH0487407A (en) Buffer circuit
JPS586321B2 (en) transistor circuit
JPS62208702A (en) Voltage-current conversion circuit
JPH01278108A (en) Differential amplifier circuit
JPH08237044A (en) Push-pull circuit
JPH04183007A (en) Buffer circuit
JPH0585131U (en) Emitter-coupled logic circuit
JPH0233207A (en) Buffer circuit
JPH05308276A (en) Ecl gate
JPH03129414A (en) Reference voltage circuit
JPS6282805A (en) Input circuit