JPH03129414A - Reference voltage circuit - Google Patents

Abstract

PURPOSE:To prevent a noise added on a substrate from being superimposed on an output terminal by separating the substrate electrically from a PNP transistor and an N-channel FET composed in the substrate. CONSTITUTION:A current on the PNP transistor 10 is decided by a voltage applied to a resistor 6 i.e. the difference of voltages between the bases and emitters of the PNP transistors 10, 20 and a current value is constant. The voltage between the output terminal 3 and the low potential terminal 9 of a power source 1 goes to the sum of the voltages of the PNP transistor 20 and the terminal of a resistor 8, which goes to the constant value. At such a case, the emitters of the PNP transistors 10, 20 are conformed to a P-type area 400 formed in an N-type area 700 being formed in the substrate 100, and the bases to N-type areas 700, 300, and the collector to P-type areas 200, 400, respectively, and the substrate 100 is separated electrically from the PNP transistor. Also, an N-chanel FET 30 is formed in the P-type area 200, and is separated electrically similarly. Thereby, it is possible to prevent the noise from being superimposed on the output terminal.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a reference voltage circuit formed on an integrated circuit, and in particular to a reference voltage circuit formed on the same substrate to prevent noise from entering the logic circuit. Regarding reference voltage circuits.

Note that in the following figures, the same reference numerals indicate the same or corresponding parts.

[Conventional technology]

Conventionally, as this type of reference voltage circuit, the circuits shown in FIGS. 3 and 4 are known. (Tokuko Sho 58-963
(See Publication No. 17) In the third flash, 1 is a power supply, 2 is a differential amplifier, 3 is an output terminal, 4 and 5 are N P N transistors, and 6 to 8 are resistors.

Briefly explaining the operation of FIG. 3, the voltage generated across the resistors 7 and 8 by the emitter currents of NPN transistors 4 and 5 having different emitter areas is detected by the differential amplifier 2, and is output to the output terminal 3. resistance 7
, 8 is negative feedback to the bases of the NPN transistors 4 and 5 to control the emitter current and keep the voltage at the output terminal 3 constant.

FIG. 4 shows the structure of NPN transistors 4 and 5. In the figure, 100 is an N-type substrate, 800 is a P-type region, 9 (10 is an N-type region, 1000 is a P-type region, 500 is a P-type region,
600 is an insulating film, and 600 is a conductive film. The collectors of NPN transistors 4 and 5 in FIG. 3 correspond to the substrate 100 in FIG. 4, the bases to the P-type region 800, and the emitters to the N-type region 900, respectively.

Further, the P type region 1000 is provided to connect the potential of the P type region 800 to the conductive film 600, and the insulating film 500 is provided to separate each region from the conductive N film 6 (10).

[Problem to be solved by the invention]

In the conventional circuit described above, the collectors of NPN transistors 4 and 5 are constructed using substrate 100. When this circuit is fabricated on the same substrate as the logic circuit, the noise generated in the logic circuit is applied to the collector of the NPN transistor through the substrate, so there is a problem that noise is superimposed on the output terminal 3.

Therefore, it is an object of the present invention to provide a reference voltage circuit in which noise is not superimposed on such an output terminal.

[Means to solve the problem]

In order to solve the above problems, the first circuit of the present invention
The first PNP whose collector and base are connected
A second PNP whose collector and base are connected to the emitter of a transistor (such as 10)
Connect the emitter of a transistor (such as 20), and connect the source of an N-channel FET (such as 30) to the connection point between these two emitters, such as output terminal 3 (hereinafter referred to as the first connection point), and One end of a series circuit of first and second resistors (6 and 7, etc.) is connected in series to the collector of the P N P transistor, such that the first resistor (6, etc.) is on the transistor side, and Second PNP
A third resistor (e.g. 8) in series with the collector of the transistor
The other end of this third resistor is connected to the other end of the series circuit of the resistors, and this connection point (such as 9, hereinafter referred to as the second connection point) and the drain of the N-channel FET are connected. A DC voltage (
power source 1, etc.) is applied, and the power source 1. The gate of the N-channel FET is driven via a differential amplifier (such as 2) so that the potential difference between the connection point between the second resistors and the collector of the second PNP transistor becomes 0. ,
Said 1st. A reference voltage circuit that generates a reference voltage between a second connection point, the two PNP transistors comprising:
A P-wall region (such as 200) formed on an N-type substrate (such as 100), an N-type region (such as 700) formed within this P-type region, and a P-wall region formed within this N-type region, respectively. (400 etc.).

In order to solve the above problems, the second circuit of the present invention is as follows:
The emitter of the first PNP transistor (e.g. 10) and the emitter of the second PNP transistor (e.g. 20) are connected, and the connection point of these two emitters (output terminal 3
(hereinafter referred to as the first connection point) is connected to an N-channel FET.
(30, etc.), and connect the first and second resistors (6
and 7, etc.) is connected to one end of the series circuit of the first resistor (6, etc.).
) is connected to the transistor side, one end of a third resistor (such as 8) is connected in series to the base of the second PNP transistor, and the other end of this third resistor and the and the other end of the series circuit, and connect this connection point (such as 9, hereinafter referred to as the second connection point) to the N-channel FE.
A DC voltage (power supply 1, etc.) is applied between the drain of the T and the drain side of the T so that the drain side becomes the positive electrode, and
The collector of the PNP transistor is connected to a second connection point, and the potential difference between the connection point between the first and second resistors and the base of the second PNP transistor is O. A reference voltage circuit that drives the gate of the N-channel FET via a differential amplifier (such as 2) and generates a reference voltage between the first and second connection points, the two PNP transistors comprising: Each N-type substrate (
A P-wall region (e.g., 200) formed on top of (e.g., 100), an N-type region (e.g., 700) formed within this P-type region, and a P-wall region (e.g., 400) formed within this N-type region. shall be made by

[Effect]

The present invention prevents noise added to the base 100 from being superimposed on the output terminal by electrically isolating the substrate 100 and the PNP transistors 10, 20 and the N-channel FET 30 formed within the substrate.

〔Example〕

FIG. 1 shows a configuration circuit as a first embodiment of the present invention, which corresponds to FIG. 3 of the conventional example, and FIG. 2 shows the structure of the P N P transistor side O and 20, and is similar to FIG. It corresponds to this.

In FIG. 1, 10 and 20 are diode-connected PNP transistors, and 30 is an N-channel FET. Further, in FIG. 2, 700 is an N type region.

In this example, the emitter area of the PNP transistor IO is made larger than the emitter area of the same transistor 20.

To explain the invention in detail with reference to FIG. 1, a 74 source voltage is supplied between the N-channel F E T0n and resistors 7 and 8 by a voltage Ill. Due to the negative feedback of the differential amplifier 2, the voltage between the resistors 7 and 8 is kept at the same potential. This means that the current ratio of diode-connected PNP transistors 10 and 20 is equal to the inverse ratio of the resistances of resistors 7 and 8. The current in PNP l-transistor 10 is equal to the voltage across resistor 6, i.e. PNP
This current value is determined by the difference in voltage between the base and emitter of transistors 10 and 20, and is constant. The voltage between the output terminal 3 and the low potential terminal 9 of the power source 1 is the sum of the voltages between the terminals of the PNP transistor 20 and the resistor 8, and has a constant value.

Next, the structure of the PNP transistor will be explained using FIG. An N-type region 700 is formed within a P-type region 200 formed on a substrate 100. Further, a P wall region 400 and an N type region 300 are formed within the N type region 700. Conductive film 6
00 is used to electrically connect the N-type region 300 and the P-wall region 400. Here, the emitters of the PNP transistors 10 and 20 are formed in the P wall region 400 formed in the N type region 700, the bases are formed in the N type regions 700 and 300, and the collectors are formed in the P type region 200 and the P type region 200. These correspond to the P wall regions 400 respectively.

Therefore, the substrate 100 and the PNP disk are electrically isolated. Furthermore, the N channel 30 is generally connected to the P type region 2.
00, so they are electrically isolated.

FIG. 5 shows a configuration circuit as a second embodiment of the present invention, and corresponds to FIG. 3 of the conventional example.

In FIG. 5, lO and 20 are PNP transistors,
30 is an N-channel FET. In this example, PN
The emitter area of the P transistor IO is made larger than that of the transistor 20.

To explain the invention in detail with reference to FIG. 5, a voltage 111 is supplied between the N-channel F E T2O and the resistors 7 and 8 by a power supply l. Due to the negative feedback of the differential amplifier 2, the voltage between the resistors 7 and 8 is kept at the same potential. This means that the base current ratio of PNP transistors 10 and 20 is equal to the inverse ratio of the resistances of resistors 7 and 8. The base current of the PNP transistor 10 is determined by the voltage applied to the resistor 6, that is, the difference between the base-emitter voltages of the PNP transistors IO and 20, and this current value is constant. The voltage between the output terminal 3 and the low potential terminal 9 of the power supply 1 is the sum of the voltages between the terminals of the PNP transistor 20 and the resistor 8, and has a constant value.

〔Effect of the invention〕

According to the first invention, the emitter of the PNP transistor 10 whose collector and base are connected, and the PNP whose collector and base are also connected.
The emitter of the transistor 20 is connected to the output terminal 3, which is the connection point between these two emitters.
Connect the source of E T2O in series with the collector of the PNP transistor 10, and connect one end of the series circuit of resistors 6 and 7 so that the resistor 6 is on the transistor IO side, and connect the resistor 6 in series with the collector of the PNP transistor 20. One end of the resistor 8 is connected to the resistor 6, and the other end of the resistor 8 is connected to the resistor 6.
, 7, and apply a DC power supply l between this connection point 9 and the drain of the N-channel FET2O so that the drain side becomes the positive terminal, and The gate of the N-channel FET2O is driven via the differential amplifier 2 so that the potential difference between the connection point between them and the collector of the PNP transistor 20 is O, and the output terminal In the reference voltage circuit that generates a reference voltage between the connection point 9 and the connection point 9, the two
NP transistors 10 and 20 are connected to an N-type substrate 1, respectively.
P type region 200 formed on 00 and this P type region 20
The N-type region 700 formed within 0 and this N-type region 700
Since the P-type region 400 is formed in the PNP transistor lO which determines the reference voltage.
and 20. N-channel F E T2O is the substrate 100
Since it is electrically isolated from the circuit board, it is possible to prevent the influence of noise from logic circuits fabricated on the same substrate.

According to the second invention, the emitter of the PNP transistor 10 and the emitter of the PNP transistor 20 are connected, and the output terminal 3 serving as the connection point between these two emitters is connected to the N
Connect the source of channel F E T2O and the PN
One end of a series circuit of resistors 6 and 7 is connected in series to the base of the P-type transistor 10 so that the resistor 6 becomes the same as the transistor 10, and one end of a resistor 8 is connected in series to the base of the PNP transistor 20. The other end of this resistor 8 is connected to the other end of the series circuit of the resistors 6.7, and a DC power source is connected between this connection point 9 and the drain of the N-channel FET2O so that the drain side is the positive terminal. l is applied, the collectors of the first and second PNP transistors are connected to the second connection point, and the voltage between the mutual connection point of the resistors 6.7 and the collector of the PNP transistor 20 is In the reference circuit that drives the gate of the N-channel FET2O via the differential amplifier 2 so that the potential difference is 0, and generates a reference voltage between the output terminal 3 and the connection point 9, the two PNP transistors 10 and 20 are respectively formed on the NQ substrate 100.
The PNP transistor 10 that determines the reference voltage is manufactured by forming a type region 200, an N-type region 700 formed within this P-type region 200, and a P-type region 400 formed within this N-type region 700. and 20. Since the N-channel FET2O is electrically isolated from the substrate 100, the influence of noise from logic circuits fabricated on the same substrate can be prevented 11-. can.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of the present invention, FIG. 2 is a structural diagram of the PNP transistor in FIGS. 1 and 5, and FIG. 3 is a conventional circuit diagram corresponding to FIG. 1. The circuit diagram of FIG. 4 is similar to that of FIG. 1 Power supply, 2 Differential amplifier, 3 Output terminal, 6°7.8
Resistance, 10.2 (1-PNP transistor, 3
ON channel FET, 100 substrate, 200.
800P type region, 300.90111. ,-,, N-type region, 400.1000,,,-P-type region, 500
Insulating film, 600 Conductive film, 7θON, etc. (100 ＼ 800

Claims (1)

[Claims] 1) A first P whose collector and base are connected
The source of the N-channel FET is connected to the first connection point between the emitter of the NP transistor and the emitter of a second PNP transistor whose collector and base are also connected, and the source of the N-channel FET is connected to the collector of the first PNP transistor. first in series
and one end of a series circuit of a second resistor is connected such that the first resistor is on the transistor side, and a third resistor is connected in series to the collector of the second PNP transistor.
a second connection point formed by connecting one end of the resistor of the third resistor to the other end of the series circuit of the first and second resistors, and a drain of the N-channel FET; During this time, a DC voltage is applied so that the drain side becomes the positive electrode, and the potential difference between the connection point between the first and second resistors and the collector of the second PNP transistor is set to zero. A reference voltage circuit that drives the gate of the N-channel FET via a differential amplifier and generates a reference voltage between the first and second connection points, the two PNP transistors each having an N-channel FET. A reference voltage circuit characterized in that it is manufactured by a P-type region formed on a type substrate, an N-type region formed within this P-type region, and a P-type region formed within this N-type region. . 2) The emitter of the first PNP transistor and the second PNP transistor
The source of the N-channel FET is connected to a first connection point with the emitter of the NP transistor, and one end of a series circuit of first and second resistors is connected to the first resistor in series with the base of the first PNP transistor. is connected to the transistor side, one end of a third resistor is connected in series to the base of the second PNP transistor, and the other end of the third resistor is connected to the first and second resistors. A DC voltage is applied between a second connection point formed by connecting the other end of the series circuit and the drain of the N-channel FET so that the drain side becomes a positive electrode, and the first and second PNP transistors the collector of the differential amplifier is connected to a second connection point, and the voltage difference between the connection point between the first and second resistors and the base of the second PNP transistor is zero. a reference voltage circuit that drives the gate of the N-channel FET through the gate and generates a reference voltage between the first and second connection points, the two PNP transistors each being formed on an N-type substrate; 1. A reference voltage circuit characterized in that the reference voltage circuit is manufactured by a P-type region formed within the P-type region, an N-type region formed within the P-type region, and a P-type region formed within the N-type region.