JPS62208702A - Voltage-current conversion circuit - Google Patents

Voltage-current conversion circuit

Info

Publication number
JPS62208702A
JPS62208702A JP61051793A JP5179386A JPS62208702A JP S62208702 A JPS62208702 A JP S62208702A JP 61051793 A JP61051793 A JP 61051793A JP 5179386 A JP5179386 A JP 5179386A JP S62208702 A JPS62208702 A JP S62208702A
Authority
JP
Japan
Prior art keywords
current
input
voltage
operational amplifier
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61051793A
Other languages
Japanese (ja)
Inventor
Hideo Kameda
亀田 英夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP61051793A priority Critical patent/JPS62208702A/en
Publication of JPS62208702A publication Critical patent/JPS62208702A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To output the sum of input voltages as a current with a simple circuit and to improve the characteristic in reducing the power supply voltage by using a current mirror as a feedback circuit of an operational amplifier and connecting a resistor between an input terminal and an inverting input of the operational amplifier. CONSTITUTION:Denoting the area ratio of transistors (TR) 3,2 as 1:m when the hFE of TRs constituting a current mirror circuit 15 is sufficiently high, the output current I0 is expressed as I0=m.Iia=(m/R).Via, which indicates that an output current proportional to the input voltage Via is obtained. When n-set of input terminals 8a-8n are provided, the resistance value of corresponding resistors 4a-4n is R and input voltages Via-Vin are impressed respectively, then the total sum of the input currents is Ii=(Via+... +Vin)/R. The sum current flows to the current mirror circuit 15, the output current I0=m.(Via+... +Vin)/R is obtained, which is an output current proportional to the sum of the input voltages.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、演算増幅器を用いた電圧電流変換回路の構
成に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the configuration of a voltage-current conversion circuit using an operational amplifier.

〔従来の技術〕[Conventional technology]

第2図は従来の電圧電流変換回路を示す0図において、
1は演算増幅器、2はNPN)ランジスタ(以下NPN
  Trと略す)、4は電圧電流変換用抵抗、6は電源
(電圧値Vcc)端子、7はグランド端子、8は演算増
幅器1の非反転入力端子でもある入力端子、9は基準電
圧端子、10は出力端子、11は演算増幅器1の出力端
子、12は演算増幅器1の反転入力端子であり、NPN
  Tr2のエミッタに接続されるとともに抵抗4を介
して基準電圧端子に接続されている。また13は基準電
圧端子に流れ込む電流(1流値■。”)、14は出力電
流(電流値■。)を示す。
Figure 2 shows a conventional voltage-current conversion circuit.
1 is an operational amplifier, 2 is an NPN) transistor (hereinafter referred to as NPN)
Tr), 4 is a voltage-current conversion resistor, 6 is a power supply (voltage value Vcc) terminal, 7 is a ground terminal, 8 is an input terminal which is also a non-inverting input terminal of the operational amplifier 1, 9 is a reference voltage terminal, 10 is an output terminal, 11 is an output terminal of operational amplifier 1, 12 is an inverting input terminal of operational amplifier 1, and NPN
It is connected to the emitter of Tr2 and also to the reference voltage terminal via resistor 4. Further, 13 indicates a current flowing into the reference voltage terminal (1 current value ■.''), and 14 indicates an output current (current value ■.).

次に動作について説明する。入力端子8に基準電圧端子
9から見て入力電圧Viが入力された場合を考える。こ
こで演算増幅器1の反転入力端子と非反転入力端子とは
イマジナリ−ショートとなるように帰還がかかるため、
反転入力端子12の電位は基準電圧端子9からみてVi
となり、抵抗4値をRとすると、これ電流れる電流13
値H01は■。’=(Vi)/Rとなる。ここで電流1
3値101はNPN  Tr2のベース電流値と、出力
電流14値■。との和であるが、NPN  Tr2のh
F、が十分高いと考えると、IO#I0°となり、To
 #(V i)/Rとなって電圧電流変換がなされる。
Next, the operation will be explained. Consider a case where an input voltage Vi is input to the input terminal 8 as seen from the reference voltage terminal 9. Here, feedback is applied to the inverting input terminal and non-inverting input terminal of the operational amplifier 1 so that an imaginary short circuit occurs.
The potential of the inverting input terminal 12 is Vi when viewed from the reference voltage terminal 9.
So, if the resistance 4 value is R, this current will be 13
The value H01 is ■. '=(Vi)/R. Here the current is 1
The three values 101 are the base current value of NPN Tr2 and the output current 14 value ■. h of NPN Tr2
Considering that F is sufficiently high, IO#I0° and To
#(V i)/R, and voltage-current conversion is performed.

なお、この回路で演算増幅器の出力端子11の電圧Vl
lは端子9の基準電圧をVsとすると、V、、=V s
 +V i +V、、2で表わされる。
Note that in this circuit, the voltage Vl of the output terminal 11 of the operational amplifier
When the reference voltage of terminal 9 is Vs, l is V,,=V s
+V i +V,,2.

また、複数の入力電圧を加算して電圧電流変換する場合
は、第2図に示した電圧電流変換回路の前に電圧の加算
回路を設けるか、もしくは第2図の回路を複数個並列に
並べ、それぞれ電圧電流変換した後に出力10を接続し
、それぞれの電流を加算するという方法がとられる。
In addition, when converting voltage to current by adding multiple input voltages, a voltage adding circuit should be provided before the voltage/current conversion circuit shown in Figure 2, or multiple circuits in Figure 2 should be arranged in parallel. , the output 10 is connected after each voltage-current conversion, and the respective currents are added.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の電圧電流変換回路は、以上のように構成されてい
るので、演算増幅器の出力電圧■、1としては、基準電
圧Vsに入力電圧Viと■、とが加算されるため、電a
lX電圧Vcc低下時の出力特性が悪いという欠点があ
った。
Since the conventional voltage-current conversion circuit is configured as described above, the output voltage (1) of the operational amplifier is determined by adding the input voltages Vi and (2) to the reference voltage Vs.
There was a drawback that the output characteristics were poor when the lX voltage Vcc decreased.

また複数の入力電圧の和を電流に変換して出力する場合
は電圧電流変換回路の前に加算器を追加するか、もしく
は複数の電圧電流変換回路を並列に並べ、それぞれの入
力電圧を電流に変換した後に電流を加算するなど、回路
が大規模になるという問題点があった。
Also, if you want to convert the sum of multiple input voltages into a current and output it, add an adder before the voltage-current conversion circuit, or arrange multiple voltage-current conversion circuits in parallel and convert each input voltage into a current. There was a problem in that the circuit became large-scale because the current was added after conversion.

この発明は上記のような問題点を解消するためになされ
たもので、電源電圧の減電圧時の特性を改善できるとと
もに、簡易な回路で入力電圧の和を電流として出力する
ことのできる電圧電流変換回路を得ることを目的とする
This invention was made in order to solve the above-mentioned problems, and it is possible to improve the characteristics when the power supply voltage decreases, and also to create a voltage and current system that can output the sum of input voltages as a current using a simple circuit. The purpose is to obtain a conversion circuit.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る電圧電流変換回路は、演算増幅器の帰還
回路としてカレントミラー回路を用いるとともに、入力
端子と演算増幅器の反転端子間に抵抗を接続したもので
ある。
The voltage-current conversion circuit according to the present invention uses a current mirror circuit as a feedback circuit of an operational amplifier, and connects a resistor between an input terminal and an inverting terminal of the operational amplifier.

〔作用〕[Effect]

この発明においては、演算増幅器の帰還回路としてカレ
ントミラー回路が使用されているから、該帰還回路は入
力端子と非反転又は反転入力端子間に印加された電圧を
、入力抵抗で割った値の出力電流に安定に変換するとと
もに、演算増幅器の出力が基準電位に対し■、たけ負に
なるように機能する。
In this invention, since a current mirror circuit is used as the feedback circuit of the operational amplifier, the feedback circuit outputs a value obtained by dividing the voltage applied between the input terminal and the non-inverting or inverting input terminal by the input resistance. It stably converts into current, and functions so that the output of the operational amplifier becomes significantly negative with respect to the reference potential.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第1
図は本発明の一実施例による電圧電流変換回路を示し、
図において、1は演算増幅器、2゜3はカレントミラー
回路を構成するNPN  Tr。
An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a voltage-current conversion circuit according to an embodiment of the present invention,
In the figure, 1 is an operational amplifier, and 2 and 3 are NPN transistors forming a current mirror circuit.

4a〜4nは入力抵抗、5は基準電圧端子9に接続され
た演算増幅器の入力電流によるオフセット補正用の抵抗
、6は電源端子(電圧値Vcc) 、7はグランド端子
、8a〜8nは入力端子、9は基準電圧端子、10は出
力端子、11は演算増幅器の出力端子、12は反転端子
、13a〜13nは入力電流(電流値Ia−In)、1
4は出力電流(電流値■。)、15はベアリングのとれ
たカレントミラー回路である。
4a to 4n are input resistors, 5 is a resistor for offset correction due to the input current of the operational amplifier connected to the reference voltage terminal 9, 6 is a power supply terminal (voltage value Vcc), 7 is a ground terminal, and 8a to 8n are input terminals , 9 is a reference voltage terminal, 10 is an output terminal, 11 is an output terminal of an operational amplifier, 12 is an inverting terminal, 13a to 13n are input currents (current value Ia-In), 1
4 is an output current (current value ■.), and 15 is a current mirror circuit with a bearing.

次に動作について説明する。Next, the operation will be explained.

第1図において、入力端子と入力抵抗が1つの場合、つ
まり入力端子が8a、入力抵抗が4aのみの場合を考え
る。入力電圧Viaが基準電圧端子9の電圧Vsを基準
として入力端子8aに印加されると、演算増幅器1の反
転入力端子12の電位は非反転入力端子とイマジナリ−
ショートになりほぼv3であるから、入力抵抗4aをR
とすると、これ電流れる電流13aはIiam(Via
)/Rで表わされる。この電流はカレントミラー回路1
5のトランジスタ3に流れ込む、ここでカレントミラー
回路を構成するトランジスタのhrEが十分高いとし、
トランジスタ3と2の一面積比を1:mとすると、出力
電流I0はlo−m−lLa−(m/R)  ・Via
となって、入力電圧に比例した出力電流が得られる。こ
の時、演算増幅器の出力端子11の電圧vllはVll
−V 3  Vmt3となって、電源電圧Vccの減電
圧に対し、十分広いダイナミックレンジをもっている。
In FIG. 1, consider the case where there is only one input terminal and one input resistor, that is, the case where the input terminal is 8a and the input resistor is only 4a. When the input voltage Via is applied to the input terminal 8a with reference to the voltage Vs of the reference voltage terminal 9, the potential of the inverting input terminal 12 of the operational amplifier 1 is imaginary equal to that of the non-inverting input terminal.
Since it is short-circuited and the voltage is almost v3, the input resistor 4a is set to R.
Then, the current 13a that flows is Iiam(Via
)/R. This current is current mirror circuit 1
Assuming that the hrE of the transistor forming the current mirror circuit flowing into the transistor 3 of No. 5 is sufficiently high,
If the area ratio of transistors 3 and 2 is 1:m, the output current I0 is lo-m-lLa-(m/R) ・Via
As a result, an output current proportional to the input voltage is obtained. At this time, the voltage vll of the output terminal 11 of the operational amplifier is Vll
-V 3 Vmt3, which has a sufficiently wide dynamic range with respect to the voltage reduction of the power supply voltage Vcc.

次に入力端子が8a〜8nまでn個あり、それに対応し
た抵抗4a〜4nの抵抗値がすべてRで、それぞれVi
a〜Vinの入力電圧が印加されている場合を考える。
Next, there are n input terminals 8a to 8n, and the resistance values of the corresponding resistors 4a to 4n are all R, and each Vi
Consider the case where input voltages a to Vin are applied.

入力電流の総和はll−1ia+・・・・・・+l1n
=(Via+・・・・・・+Vin)/Rで表わされ、
これがカレントミラー回路15に流れ込むため1.xm
・ (Via+・・・・・・+Vin)/Rと表わされ
入力電圧を加算して電圧に比例した出力電流が得られる
ことが分かる。
The total input current is ll-1ia+...+l1n
= (Via+...+Vin)/R,
Since this flows into the current mirror circuit 15, 1. xm
- It is expressed as (Via+...+Vin)/R, and it can be seen that by adding the input voltages, an output current proportional to the voltage can be obtained.

なお、上記実施例ではカレントミラー回路のトランジス
タとしてNPN型のものを用い出力電流吸い込み型とし
たものについて述べたが、PNP型のカレントミラー回
路を用い流し出し型としてもよく、上記実施例と同様の
効果を奏する。
In the above embodiment, an NPN type transistor is used as the transistor of the current mirror circuit, and an output current sinking type is described. However, a PNP type current mirror circuit may be used as a sinking type, and the same as in the above embodiment. It has the effect of

また、上記実施例では演算増幅器の非反転端子9を基準
電圧として説明を行なったが、入力端子8を基準電圧と
して、非反転端子9を入力端子として高入力インピーダ
ンスとして使用してもよく、上記実施例と同様の効果を
奏する。
Further, in the above embodiment, the non-inverting terminal 9 of the operational amplifier is used as a reference voltage, but the input terminal 8 may be used as a reference voltage and the non-inverting terminal 9 may be used as an input terminal with high input impedance. The same effects as in the embodiment are achieved.

さらに上記実施例では、n個の入力抵抗を同一の抵抗値
としたが、それぞれの入力端子毎に抵抗値が異なり、そ
れぞれゲインを変化させる場合や、カレントミラートラ
ンジスタのエミッタに抵抗を挿入してゲインを変化させ
てもよく、上記実施例と同様の減電圧特性改善効果を実
現することができる。
Furthermore, in the above embodiment, the n input resistors have the same resistance value, but each input terminal has a different resistance value, and the gain may be changed for each, or a resistor may be inserted into the emitter of the current mirror transistor. The gain may be changed, and the same effect of improving voltage reduction characteristics as in the above embodiment can be achieved.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明に係る電圧電流変換回路によれ
ば、演算増幅器の帰還回路としてカレントミラー回路を
使用し、入力端子と演算増幅器の反転または非反転入力
端子間に抵抗を接続するという構成にしたので、電源電
圧の減電圧特性が良くなるとともに、複数の入力電圧の
和に比例した出力電流を簡単に得ることができるという
効果がある。
As described above, according to the voltage-current conversion circuit according to the present invention, a current mirror circuit is used as a feedback circuit of an operational amplifier, and a resistor is connected between the input terminal and the inverting or non-inverting input terminal of the operational amplifier. This has the effect that the voltage reduction characteristics of the power supply voltage are improved and that an output current proportional to the sum of a plurality of input voltages can be easily obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例を示す回路図、第2図は従
来の電圧電流変換回路を示す回路図である。 図において、1は演算増幅器、15はカレントミラー回
路、12は反転端子、4a〜4nは抵抗、83〜8nは
入力端子である。 なお図中同一符号は同−又は相当部分を示す。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional voltage-current conversion circuit. In the figure, 1 is an operational amplifier, 15 is a current mirror circuit, 12 is an inverting terminal, 4a to 4n are resistors, and 83 to 8n are input terminals. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] (1)演算増幅器を用いた電圧電流変換回路において、 演算増幅器の出力端子と反転入力端子間に接続されたカ
レントミラー回路と、 演算増幅器の反転または非反転入力端子と単数または複
数の本電圧電流変換回路の入力端子間を接続する該入力
端子と同数かつ同一抵抗値の入力抵抗とを備え、 上記入力端子と上記非反転または反転入力端子間の電圧
またはその総和の電圧を上記入力抵抗値で割った値に比
例した電流が上記カレントミラー回路より外部に取出さ
れることを特徴とする電圧電流変換回路。
(1) In a voltage-current conversion circuit using an operational amplifier, there is a current mirror circuit connected between the output terminal and the inverting input terminal of the operational amplifier, and a current mirror circuit connected between the inverting or non-inverting input terminal of the operational amplifier and one or more main voltage currents. It is equipped with input resistors of the same number and the same resistance value as the input terminals that connect the input terminals of the conversion circuit, and the voltage between the input terminal and the non-inverting or inverting input terminal or the sum of the voltages is set at the input resistance value. A voltage-current conversion circuit characterized in that a current proportional to the divided value is taken out from the current mirror circuit.
JP61051793A 1986-03-10 1986-03-10 Voltage-current conversion circuit Pending JPS62208702A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61051793A JPS62208702A (en) 1986-03-10 1986-03-10 Voltage-current conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61051793A JPS62208702A (en) 1986-03-10 1986-03-10 Voltage-current conversion circuit

Publications (1)

Publication Number Publication Date
JPS62208702A true JPS62208702A (en) 1987-09-14

Family

ID=12896818

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61051793A Pending JPS62208702A (en) 1986-03-10 1986-03-10 Voltage-current conversion circuit

Country Status (1)

Country Link
JP (1) JPS62208702A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04117019A (en) * 1990-09-03 1992-04-17 Nec Ic Microcomput Syst Ltd Oscillation circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04117019A (en) * 1990-09-03 1992-04-17 Nec Ic Microcomput Syst Ltd Oscillation circuit

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