JPH08237044A - Push-pull circuit - Google Patents

Abstract

PURPOSE: To realize a push-pull circuit provided with an output suppression function whose operation is made stable by using a high speed transistor(TR) with low dielectric strength. CONSTITUTION: A couple of feed back circuits connected in parallel are provided, which are made up of a buffer amplifier 11, DC power supplies 12, 13, TRs 3, 4 connecting to an emitter common connecting point of TRs 1, 2 in complementary connection in a push-pull circuit. The buffer amplifier 11 is of a high input impedance. The negative pole of the DC power supply 12 is connected to the buffer amplifier 11 and the positive pole of the DC power supply 13 is connected to the buffer amplifier 13. The TR 3 is of the same conduction type as that of the TR 1 and its base connects to the positive pole of the DC power supply 12 and its emitter connects to a collector of the TR 1 in series. The TR 4 is of the same conduction type as that of the TR 2 and its base connects to the negative pole of the DC power supply 13 and its emitter connects to a collector of the TR 2 in series.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a push-pull circuit, and more particularly to a push-pull circuit with an output suppressing function for suppressing the output of a buffer amplifier.

[0002]

2. Description of the Related Art Next, an example of a conventional push-pull circuit with an output suppressing function is shown in FIG. Bias circuit 100 of FIG.
Includes, for example, transistors 101 and 104 that drive a complementary symmetrical push-pull circuit, and transistors 102 and 103, a resistor 105, and a resistor 106 that form an output suppression circuit. The complementary symmetrical push-pull circuit includes an input terminal 21, a power supply terminal 22 for the voltage V _CC , and a voltage V _EE.
The power supply terminal 23 of is introduced. The output suppression circuit includes output suppression signal input terminals 24 and 25, a power supply terminal 22 for the voltage V _CC ,
A power supply terminal 23 of voltage V _EE is introduced. The push-pull circuit has an output terminal 31, a load 41, and a terminal power supply 4 for the voltage V _TT.
2 are connected in series. The base-emitter voltage V _BE in the active state of the transistor is regarded as approximately constant, and will be handled below.

In this circuit, when the output is not suppressed, the voltage V _BE lower than the voltage V _CC of the power supply input terminal 22 by the voltage V _BE is applied to the output suppression signal input terminal 24 so as not to turn off the transistor 103. V _CC −V _BE ). Similarly, in order not to turn off the transistor 102, the power supply input terminal 23 is also connected to the output suppression signal input terminal 25.
Voltage V _BE higher than the voltage V _{EE of} V (= V _EE +
V _BE ) is given. Then, the voltage applied to the input terminal 21 is applied with a DC offset by the bias circuit 100, and is transmitted to the output terminal 31 via the push-pull circuit composed of the transistors 1 and 2.

On the other hand, in this circuit, when the output is suppressed, the voltage V _{CC of the} power supply input terminal 22 is applied to the output suppression signal input terminal 24 in order to turn off the transistor 103.
Gives a voltage equal to. Similarly, in order to turn off the transistor 102, a voltage equal to that of the power supply input terminal 23 is applied to the output suppression signal input terminal 25. When the transistors 102 and 103 are turned off, the transistor 101
Since the base current of 104 does not flow, the transistors 101 and 104 are also turned off. At this time, the voltage V _EE is applied to the base of the transistor 1 via the resistor 106, and the voltage V _CC is applied to the base of the transistor 2 via the resistor 105. As a result, the transistor 1
・ 2 The base-emitter is reverse biased and the output is suppressed. In order to suppress the output in this way, the relationship between the voltage V _TT of the termination power supply 42, the power supply voltage V _CC · V _EE, and the base-emitter voltage V _BE is V _EE −V _BE <V _TT <.
It is necessary to satisfy V _CC + V _BE . When this relationship is not satisfied, the transistor 1 or the transistor 2 is turned on and the output cannot be suppressed.

[0005]

By the way, in the conventional circuit, when the voltage V _TT of the termination power supply 42 is wider than the range of the output voltage of the circuit, the power supply voltages V _CC and V _EE are set according to V _TT . Must be set large. At this time, a maximum voltage of V _CC -V _EE may be applied between the collector and emitter of the transistors 1 and 2. Therefore, in order to prevent the circuit from being destroyed, it is necessary to use a transistor having a large withstand voltage of the collector-emitter voltage V _CE .

However, in general, the operating speed of a transistor and the withstand voltage are contradictory, so that a transistor with a high withstand voltage does not operate at high speed. Therefore, when the voltage V _TT of the terminal power supply 42 can be in a wide range, there is a problem that the operation of the push-pull circuit with the output suppressing function cannot be performed at high speed.

According to the present invention, even when the termination power supply voltage is wider than the range of the output voltage, the push-pull circuit with the output suppressing function enables high-speed operation by the high-speed transistor having a low breakdown voltage and stable operation. The purpose is to provide.

[0008]

In order to achieve this object, according to the present invention, a signal is input via a bias circuit having an output suppressing function and complementary connection is made to the first NPN.
In a push-pull circuit in which an output terminal is derived from a common emitter connection point of a transistor and a first PNP transistor, a buffer amplifier of high input impedance to which a voltage of the output terminal is input, and a buffer amplifier connected to an output side of the buffer amplifier A pair of parallel DC power supplies, a base connected to one DC power supply, a second NPN transistor serially connected to the first NPN transistor, and a base connected to the other DC power supply, a first PNP transistor And a second PNP transistor serially connected to.

[0009]

In the push-pull circuit of the present invention, the voltage at the circuit output terminal is fed back from the buffer amplifier to the emitter of the second NPN transistor via one power supply 12 and from the buffer amplifier to another DC power supply 13. It is fed back to the emitter of the second PNP transistor. here,
The collector-emitter voltage of the first NPN transistor is the difference between the voltage of the one power supply 12 and the base-emitter voltage, and is maintained at a constant value. The collector-emitter voltage of the first PNP transistor is the difference between the base-emitter voltage and the voltage of the other power supply 13, and is maintained at a constant value. Therefore, no excessive voltage is applied between the collector and the emitter of the first NPN transistor and the first PNP transistor.

Therefore, even when the output voltage of the terminal power supply voltage is wider than the range, the high speed transistor having a small withstand voltage enables high speed operation and stable operation.

[0011]

FIG. 1 shows the configuration of an embodiment of a push-pull circuit with an output suppressing function according to the present invention. FIG.
In FIG. 2, the same components as those in FIG. 2 are denoted by the same reference numerals for convenience, and the description thereof is omitted.

In FIG. 1, 12 is a DC power supply whose voltage is V _OFF1 and 13 is a DC power supply _whose voltage is V _OFF2 . NPN
A buffer amplifier 11 having a high input impedance and a low output impedance is connected to a common emitter connection point between the transistor 1 and the PNP transistor 2. The voltage of the output terminal 31 is input to the buffer amplifier 11. To the output line of the buffer amplifier 11, a pair of DC power supplies 12 and 13 which are parallel to each other are connected. That is, the negative side of the DC power supply 12 is on the buffer amplifier 11 side,
The positive side of the DC power supply 13 is connected to the buffer amplifier 11 side. An NPN transistor 3 is connected in series to the NPN transistor 1. That is, the collector of this NPN transistor 3 is the power supply terminal 22, and the emitter is NP.
The collector of the N-transistor 1 has a DC power source 12 at the base.
Is connected to the positive side of. On the other hand, PNP transistor 2
Is connected in series with the PNP transistor 4. That is, the emitter of this PNP transistor 4 is PNP.
The collector of the transistor 2 has a power supply terminal 23.
The base is connected to the negative side of the DC power supply 13.

In FIG. 1, when the output is not suppressed, the power supply input terminal 2 is connected to the output suppression signal input terminal 24 so as not to turn off the transistor 103, as in the conventional circuit.
The voltage V _BE lower than the second voltage V _CC by the voltage V _BE (= V _CC
-V _BE ). Similarly, in order not to turn off the transistor 102, a voltage V (= V _EE + V _BE ) higher than the voltage V _EE of the power supply input terminal 23 by the voltage V _BE is also applied to the output suppression signal input terminal 25. Then, the input voltage applied to the input terminal 21 is applied with a DC offset by the bias circuit 100 and transmitted to the output terminal 31 via the bases of the transistors 1 and 2. here,
The voltage at the output terminal 31 is fed back from the buffer amplifier 11 to the transistor 3 via the DC power supply 12, and to the transistor 4 from the buffer amplifier 11 via the DC power supply 13. However, these feedback circuits only serve to keep the collector-emitter voltage V _CE of the transistors 1 and 2 constant, and do not affect the voltage of the output terminal 31.

On the other hand, in the push-pull circuit of the embodiment, when the output is suppressed, the voltage of the power supply input terminal 22 is applied to the output suppression signal input terminal 24 in order to turn off the transistor 103 as in the conventional circuit. Apply a voltage equal to V _CC . Similarly, in order to turn off the transistor 102, a voltage equal to that of the power supply input terminal 23 is applied to the output suppression signal input terminal 25. And transistor 1
When 02.103 turns off, the transistors 101.10
Since the base current of 4 stops flowing, the transistor 10
1.104 is also turned off. When the transistors 101 to 104 are turned off, the base-emitter junctions of the transistors 1 and 2 are reverse-biased and the output is suppressed.

At this time, the voltage of the output terminal 31 determined by the terminal power supply 42 is fed back from the buffer amplifier 11 to the emitter of the transistor 3 via the power supply 12, and from the buffer amplifier 11 to the emitter of the transistor 4 via the power supply 13. Be returned to. Where transistor 1
The collector-emitter voltage V _CE of the
_It is the difference between _OFF1 and the base-emitter voltage V _BE, and is maintained at a constant value (V _OFF1 −V _BE ). Also, the transistor 2
The collector-emitter voltage V _CE becomes a difference between the base-emitter voltage V _BE and the voltage V _{OFF2 of the} power supply 13, and is maintained at a constant value (V _BE −V _OFF2 ). These feedback circuits work so as to keep the voltage V _CE between the collector and the emitter of the transistors 1 and 2 constant, so that no excessive voltage is applied during this period. Further, since the input impedance of the buffer amplifier 11 is high, it does not affect the voltage of the output terminal 31.

In FIG. 1, the resistors 105 and 106 are connected to the power sources of the voltages V _CC and V _EE , respectively, but they may be connected to the positive side of the power source 12 and the negative side of the power source 13, respectively. 12 and 13 may be configured by Zener diodes or the like. Furthermore, the bias circuit 100 can apply another known configuration.

[0017]

According to the present invention, even when the voltage of the terminal power supply is in a wide range, the speed of the circuit is increased by using the high-speed transistor having a low breakdown voltage, and the stable operation is ensured. You can

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a push-pull circuit according to the present invention.

FIG. 2 is a circuit diagram showing an example of a push-pull circuit according to a conventional technique.

[Explanation of symbols]

 1 ・ 3 ・ 101 ・ 102 NPN transistor 2 ・ 4 ・ 103 ・ 104 PNP transistor 11 Buffer amplifier 12 ・ 13 Power supply 21 Input terminal 22 ・ 23 Power supply terminal 24 ・ 25 Output suppression signal input terminal 31 Output terminal 41 Load 42 Termination power supply 100 Bias circuit

Claims (1)

[Claims] 1. A bias circuit (10) having an output suppressing function.
Signal is input through the first N
PN transistor (1) and first PNP transistor (2)
In the push-pull circuit in which the output terminal (31) is derived from the common emitter connection point with, the output of the buffer amplifier (11) with high input impedance and the voltage of the output terminal (31) are input. A pair of parallel DC power supplies (12, 13) connected to the side, and a second NPN transistor whose base is connected to one DC power supply (12) and which is connected in series to the first NPN transistor (1).
(3) and the other DC power supply (13), the base is connected,
Second PN connected in series with the PNP transistor (2) of
A push-pull circuit comprising a P-transistor (4).