JPH02196466A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH02196466A
JPH02196466A JP1670789A JP1670789A JPH02196466A JP H02196466 A JPH02196466 A JP H02196466A JP 1670789 A JP1670789 A JP 1670789A JP 1670789 A JP1670789 A JP 1670789A JP H02196466 A JPH02196466 A JP H02196466A
Authority
JP
Japan
Prior art keywords
wiring
steps
integrated circuit
stepped parts
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1670789A
Other languages
Japanese (ja)
Inventor
Hajime Ono
肇 小野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1670789A priority Critical patent/JPH02196466A/en
Publication of JPH02196466A publication Critical patent/JPH02196466A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent disconnection of wiring which is formed on stepped parts of a semiconductor substrate by metallic vapor deposition even through there are steps on the above substrate by providing multilateral stepped parts which protrude after intersecting at right angles to the wiring's extending direction from side faces of the steps that are formed below wiring or become hollow at inner sides and further, taking likewise other measures. CONSTITUTION:In a semiconductor integrated circuit device having a wiring 2 which is formed intersecting at right angles steps 6a and 6b extending in one direction on a semiconductor substrate 1, multilateral stepped parts 7a and 7b which protrude intersecting at right angles to the extending direction of the wiring 2 from side faces of the steps 6a and 6b that are formed below the above wiring 2 or become hollow on inner sides are formed; besides, the stepped parts 7a and 7b are formed so that each of them may have three sides or more which intersect at right angles or are parallel to the extending direction of the wiring 2. For example, rectangular stepped parts 7a and 7b are provided so that they become hollower than the steps 6a and 6b of conductive layers 3. Even thorough, for example, vapor deposition is performed from the upper side of the substrate 1 in the slanting direction of the arrow 9, thick metallic layers are vapor-deposited in the sides of the stepped parts 7a and 7b which are not shaded with respect to the vapor deposition direction and connecting parts 10 are formed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路装置に関し、特に凹凸のある半
導体基板上に配線が形成された半導体集積回路装置に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device in which wiring is formed on an uneven semiconductor substrate.

〔従来の技術〕[Conventional technology]

従来、この種の半導体集積回路装置は、配線の多層化に
伴い、半導体基板上に幾重にも眉間絶縁膜と配線とが重
ね形成された構造になっている。
Conventionally, this type of semiconductor integrated circuit device has a structure in which glabella insulating films and wiring are stacked on a semiconductor substrate in multiple layers due to multilayer wiring.

第2図(a)及び(b)は従来の一例を示す半導体基板
の部分平面図及びAA断面図である。この半導体集積回
路装置は、半導体基板1の上にのゲート層5を跨がって
一方向に形成された導電層3の上に、金属蒸着法により
、矢印4の方向から蒸着し、導電層3を横切る配線3a
が形成されている。
FIGS. 2(a) and 2(b) are a partial plan view and an AA cross-sectional view of a semiconductor substrate showing an example of the conventional method. This semiconductor integrated circuit device is manufactured by depositing a conductive layer 3 on a conductive layer 3 formed in one direction across a gate layer 5 on a semiconductor substrate 1 by a metal vapor deposition method from the direction of an arrow 4. Wiring 3a that crosses 3
is formed.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の半導体集積回路装置の構造では、配線を
、金属蒸着法によって形成するため、蒸着の方向に指向
性がある。従って、第2図(b)に示すように、段差6
aは完全に金属蒸着され、配線2と導電層3は接続され
るが、段差6bのところは、蒸着方向に対して影になる
ため、段差6bは、蒸着されなく、導電層3と配線2と
は断線状態になるという問題がある。
In the structure of the conventional semiconductor integrated circuit device described above, since the wiring is formed by a metal vapor deposition method, there is directivity in the direction of vapor deposition. Therefore, as shown in FIG. 2(b), the step 6
A is completely metal-deposited, and the wiring 2 and the conductive layer 3 are connected. However, the step 6b is in the shadow with respect to the deposition direction, so the step 6b is not deposited and the conductive layer 3 and the conductive layer 2 are connected. There is a problem that the wire will be disconnected.

即ち、半導体集積回路装置の半導体基板上には、第2図
に示すような配線パターンが、種々の方向て複数形成さ
れているので、蒸着方向をいずれかに決めても、必ず、
どれかの配線パターンに配線の段切れが起きるという問
題がある。
That is, on the semiconductor substrate of a semiconductor integrated circuit device, a plurality of wiring patterns as shown in FIG.
There is a problem that a break in the wiring occurs in one of the wiring patterns.

本発明の目的は、半導体基板上に段差があっても、その
段差部上に金属蒸着により形成された配線が断線しない
半導体集積回路装置を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device in which wiring formed by metal vapor deposition on a semiconductor substrate does not become disconnected even if there is a step on the semiconductor substrate.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体集積回路装置は、半導体基板上に一方向
に伸る段差を直角に横切って形成された配線を有する半
導体集積回路装置において、前記配線の下に形成される
前記段差の側面から前記配線の伸る方向に直交して突出
するかまたは内側に凹む長辺形状の段差部が設けられる
とともにこの段差部が前記配線の伸びる方向に対して直
交もしくは平行な辺を少なくとも三辺以上を有すること
を備え構成される。
In the semiconductor integrated circuit device of the present invention, in a semiconductor integrated circuit device having a wiring formed perpendicularly across a step extending in one direction on a semiconductor substrate, the semiconductor integrated circuit device has a wiring formed on a semiconductor substrate at right angles across a step extending in one direction. A long-sided stepped portion that protrudes perpendicularly to the direction in which the wiring extends or is recessed inward is provided, and the stepped portion has at least three sides that are perpendicular or parallel to the direction in which the wiring extends. It is configured with this in mind.

〔実施例〕 次に、本発明について図面を参照して説明する。〔Example〕 Next, the present invention will be explained with reference to the drawings.

第1図は本発明による一実施例を示す半導体基板の部分
平面図である。この半導体集積回路装置は、同図に示す
ように、導電層3の段差6a及び6bより導電層3側に
凹んで矩形状の段差部7a及び7bを設けたことである
。それ以外は、従来例と同じである。
FIG. 1 is a partial plan view of a semiconductor substrate showing one embodiment of the present invention. As shown in the figure, this semiconductor integrated circuit device is provided with rectangular step portions 7a and 7b that are recessed toward the conductive layer 3 from the steps 6a and 6b of the conductive layer 3. Other than that, it is the same as the conventional example.

この段差部7a及び7bの底面は、半導体基板1の表面
と同一面である。また、この段差部7a及び7bの各辺
は、配線2の伸びる方向に対して平行な辺が二辺、直交
する辺が一辺あり、合計三辺の辺をもつことになる。
The bottom surfaces of the stepped portions 7a and 7b are flush with the surface of the semiconductor substrate 1. Further, each side of the step portions 7a and 7b has two sides parallel to the direction in which the wiring 2 extends and one side perpendicular to the direction in which the wiring 2 extends, for a total of three sides.

このような段差部7a及び7bを設けることにより、例
えば、段差6a及び6bに対して、矢印9の斜め方向で
、半導体基板向1の上から蒸着しても、この蒸着方向に
対して影にならない段差部7a及び7bの辺は、厚い金
属層が蒸着されて接続部10が形成される。また、影に
なる辺は、蒸着されず切断部11となる9更に、蒸着方
向を種々変えてみても、この段差部7a及び7bには、
蒸着方向に対して影にならない辺があるので、この辺が
金属蒸着されて、配線2と導電層3とは確実に接続され
る。
By providing such step portions 7a and 7b, for example, even if the step portions 6a and 6b are vapor-deposited from above the semiconductor substrate direction 1 in the diagonal direction of the arrow 9, there will be no shadow in this vapor deposition direction. A thick metal layer is deposited on the sides of the stepped portions 7a and 7b where the connecting portion 10 is formed. In addition, the shadowed sides are not vapor deposited and become cut portions 119.Furthermore, even if the vapor deposition direction is variously changed, the step portions 7a and 7b have no evaporation.
Since there is a side that is not shaded in the vapor deposition direction, metal is deposited on this side, and the wiring 2 and the conductive layer 3 are reliably connected.

ここで、この実施例では、二つの段差部7a及び7bを
それぞれの導電層3に設けたが一つでもよい、例えば、
電源線のような場合は、複数個の段差部を設けた方がよ
いが、信号線の場合は、つでもよい。また、この段差部
を段差6aがら突出するように、突出部8aの形状で出
張って設けてもよい。
Here, in this embodiment, two step portions 7a and 7b are provided on each conductive layer 3, but it is also possible to provide only one step portion, for example,
In the case of a power supply line, it is better to provide a plurality of step portions, but in the case of a signal line, one step may be provided. Further, the stepped portion may be provided in the shape of the protruding portion 8a so as to protrude from the stepped portion 6a.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明の半導体集積回路装置は、配
線が段差を横切る部位の段差の側面がら、配線の伸る方
向に直交して突出するがまたは内側に凹む長辺形状の段
差部を設け、この段差部の形状を配線の伸びる方向に対
して直交もしくは平行な辺を少なくとも三辺以上をもた
せることにより、蒸着方向に対して影にならない辺をも
つことになる。従って、この段差部のいずれかの辺が金
属蒸着され、確実に接続出来るという効果がある。
As described above, the semiconductor integrated circuit device of the present invention is provided with a step portion having a long side that protrudes perpendicularly to the direction in which the wire extends or is recessed inward from the side surface of the step where the wire crosses the step. By shaping the stepped portion to have at least three sides that are perpendicular or parallel to the direction in which the wiring extends, it has sides that are not shadowed in the direction of vapor deposition. Therefore, metal is deposited on either side of the stepped portion, and there is an effect that a reliable connection can be achieved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による一実施例を示す半導体基板の部分
平面図、第2図(a)及び(b)は従来の一例を示す半
導体基板の部分平面図及びAA断面図である。 1・・・半導体基板、2・・・配線、3・・・導電層、
4.9・・・矢印、5・・・ゲート層、6a、6b・・
・段差、7a、7b・・・段′差部、8a、8b・・・
突出部、10・・・接続部、11・・・切断部。
FIG. 1 is a partial plan view of a semiconductor substrate showing an embodiment of the present invention, and FIGS. 2(a) and 2(b) are a partial plan view and an AA sectional view of a semiconductor substrate showing an example of the conventional art. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Wiring, 3... Conductive layer,
4.9...Arrow, 5...Gate layer, 6a, 6b...
・Steps, 7a, 7b...Steps, 8a, 8b...
Projecting portion, 10... Connection portion, 11... Cutting portion.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に一方向に伸る段差を直角に横切って形成
された配線を有する半導体集積回路装置において、前記
配線の下に形成される前記段差の側面から前記配線の伸
る方向に直交して突出するかまたは内側に凹む長辺形状
の段差部が設けられるとともにこの段差部が前記配線の
伸びる方向に対して直交もしくは平行な辺を少なくとも
三辺以上を有することを特徴とする半導体集積回路装置
In a semiconductor integrated circuit device having a wiring formed perpendicularly across a step extending in one direction on a semiconductor substrate, a line extending from a side surface of the step formed below the wiring at right angles to the direction in which the wiring extends. A semiconductor integrated circuit device characterized in that a step portion having a long side that protrudes or is recessed inward is provided, and the step portion has at least three sides orthogonal to or parallel to the direction in which the wiring extends. .
JP1670789A 1989-01-25 1989-01-25 Semiconductor integrated circuit device Pending JPH02196466A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1670789A JPH02196466A (en) 1989-01-25 1989-01-25 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1670789A JPH02196466A (en) 1989-01-25 1989-01-25 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH02196466A true JPH02196466A (en) 1990-08-03

Family

ID=11923744

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1670789A Pending JPH02196466A (en) 1989-01-25 1989-01-25 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH02196466A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004014567A (en) * 2002-06-03 2004-01-15 Murata Mfg Co Ltd Magnetoelectric transducer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004014567A (en) * 2002-06-03 2004-01-15 Murata Mfg Co Ltd Magnetoelectric transducer

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