JPH02194785A - Block encoding device - Google Patents

Abstract

PURPOSE:To favorably interpolate an additional code to represent a block at a decoded side by making a spatial boundary between the blocks non-linear. CONSTITUTION:One field portion of digital video data is written successively in the field memory 31 of a scan conversion circuit 2. Then, an address control signal for forming a readout address is supplied from a ROM 38 to an address generation circuit 32, and the readout address is set so that the spatial boundary between the blocks becomes non-linear. Accordingly, it can be avoided that the boundary of the block coincides with the edge of a picture, and in the case where additional data to represent the block falls into error data, restoration data with very strong correlation is obtained. Thus, the additional code can be favorably interpolated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a block encoding device that compresses and transmits original image data by utilizing two-dimensional correlation of images, and particularly relates to a block structure.

[Summary of the invention]

In this invention, in a block encoding device that compresses and encodes each block of predetermined pixels with a bit number smaller than the number of bits of original pixel data and transmits the data, the spatial boundary line between blocks is non-linear. By selecting the block structure, the additional code representing the block can be interpolated favorably on the decoding side.

[Conventional technology]

One feature of image information is that it has two-dimensional correlation. As one type of encoding that utilizes this two-dimensional correlation, block encoding is known in which an image is divided into a large number of two-dimensional blocks and each block is encoded.

As an example of block encoding, patent application No. 59-26640
ADRC (encoding adapted to dynamic range) described in Japanese Patent Application No. 7 and Japanese Patent Application No. 60-232789 has been proposed by the applicant of the present application. ADRC calculates the dynamic range, which is the difference between the maximum and minimum values of multiple pixels included in a two-dimensional block or three-dimensional block, and adapts this dynamic range to create a quantization code with a smaller number of bits than the original number of bits. form.

That is, the dynamic range is divided into a plurality of level ranges according to the number of bits of the quantization code, and a quantization code corresponding to the level range to which the image data after minimum value removal belongs is generated.

In the above-mentioned ADRC, two pieces of data out of the dynamic range, maximum value, and minimum value of each block are used as additional codes, and the quantization code and the additional code are transmitted.

During the transmission process, if the additional code determined for each block is incorrect, decoding becomes impossible and all pixel data in that block becomes error data. Therefore, it is necessary to interpolate (conceal) the erroneous additional code on the decoding side.

The applicant utilizes the fact that adjacent pixels have a strong correlation with the block to be decoded, and decodes multiple reconstructed pixels that are included in blocks adjacent to the block to be decoded and adjacent to the block to be decoded. We propose a method to interpolate additional codes from data. That is, in an example in which one block is composed of (4 lines x 4 pixels) as shown in FIG. 6, when attempting to decode block 3, the four pixels of block 3 are Additional data is interpolated from the pixel 1 and the four adjacent pixels of block 1 that have already been decoded. Of course, the accuracy of interpolation can be increased by using restored data of not only four adjacent pixels but also eight, 12, or 16 adjacent pixels. Special request 1976
In the method described in Japanese Patent No. 2-90602, additional codes are interpolated from adjacent reconstructed data using the method of least squares. The method described in Japanese Patent Application No. 62-91795 is a method commonly used when transmitting the average value and standard deviation of all pixels in a block as an additional code.

[Problem to be solved by the invention]

In the above-mentioned previously proposed interpolation method, when all adjacent reconstructed data have the same level, the error becomes white noise, that is, it is no longer random, and a solution cannot be found using the least squares method. Such a situation occurs, for example, when the boundaries between blocks coincide with the edges of the image.

Therefore, an object of the present invention is to provide block encoding having a block structure that can prevent interpolation failure when interpolating additional codes using restored data of adjacent pixels of adjacent blocks, as described above. The goal is to provide equipment.

[Means to solve the problem]

In this invention, in a block encoding device that compresses and encodes each block of predetermined pixels with a bit number smaller than the number of bits of original pixel data and transmits the data, the spatial boundary line between blocks is non-linear. A block structure is selected.

[Effect]

Since the boundaries between blocks are assumed to be non-linear, the edges of the image are prevented from coinciding with the boundaries of the blocks, the errors are random, and the additive code can be interpolated using the method of least squares.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an image data transmission system according to this embodiment, in which digital video data in which one sample is digitized into 8 bits is supplied to an input terminal indicated by 1. The data arrangement of the video data is converted from the order of scanning lines to the order of blocks in a scan conversion circuit 2, which will be described later.

The output signal of the scan conversion circuit 2 is supplied to a maximum value and minimum value detection circuit 3 and a delay circuit 4. The detection circuit 3 detects the maximum value MAX and minimum value MIN of the block. The delay circuit 4 delays the data for the time it takes to detect the maximum value MAX and the minimum value MIN. In the subtraction circuit 5 (MAX-MIN
) is calculated, and the dynamic range D is calculated from the subtraction circuit 5.
R is obtained. In the subtraction circuit 6, the minimum value MIN is subtracted from the video data from the delay circuit 4, and video data from which the minimum value has been removed is obtained from the subtraction circuit 6.

The output data and dynamic range DR of the subtraction circuit 6 are supplied to a quantization circuit 7. From the quantization circuit 7, a quantized code DT having a bit number smaller than the original bit number (8 bits), for example, 4 bits, is obtained. Dynamic range DR
The minimum value MIN and the quantization code DT are supplied to the framing circuit 8, and the transmission data is taken out to the output terminal 9. The framing circuit 8 has a dynamic range DR1
The minimum value MIN and the quantization code DT are arranged byte serially to form transmission data to which a synchronization signal is added. Further, the framing circuit 8 also uses additional codes (DR,
An error correction code is encoded for each of the quantization code DT (MIN) and the quantization code DT.

The quantization circuit 7 performs quantization adapted to the dynamic range DR, that is, the dynamic range DR is (2'
-16) The video data from which the minimum value has been removed is divided by the equally divided quantization step Δ, and the value obtained by rounding down the quotient to an integer is set as the quantization code DT. The quantization circuit 7 can be composed of a division circuit or a ROM.

The transmission data taken out to the output terminal 9 of the frame forming circuit is supplied to the frame disassembling circuit 12 from the receiving side input terminal 11 via the transmission line 10 shown by the broken line. Transmission line 1
0 is a recording and reproducing process composed of, for example, a magnetic tape and a rotary head.

The frame decomposition circuit 12 decomposes the transmission data and separately extracts the dynamic range DR, minimum value MIN, and quantization code DT. Also, frame decomposition circuit 1
2, the error correction code of the additional code and the quantization code DT is decoded. The error flag EF generated from the frame decomposition circuit 12 indicates the presence or absence of an error in the additional code after decoding the error correction code. For example, the error flag EF is a 1-bit code, which is "O" when there is no error and "1" when there is an error.

The dynamic range DR for each block is supplied to the ROM 13, and the quantization step Δ is obtained from the ROM 13.

This quantization step Δ is supplied to one input terminal of a selection circuit 15 via a delay circuit 14. The other input terminal of the selection circuit 15 is supplied with a quantization step Δ' from an additional code recovery circuit 16.

The minimum value MIN from the frame decomposition circuit 12 is the delay circuit 1
The minimum value MIN' is supplied from the additional code recovery circuit 16 to the other input terminal of the 0 selection circuit 18, which is supplied to one input terminal of the selection circuit 18 via 7. These selection circuits 15 and 18 are controlled by an error flag EF. When the error flag EF is “Om”, the delay circuit 14
The selection circuits 15 and 18 select the quantization step Δ and the minimum value MIN output from the quantization steps Δ and 17, respectively. When the error flag EF is “1”, the additional code recovery circuit 1
The quantization step Δ' and the minimum value MIN' from 6 are selected by selection circuits 15 and 18, respectively.

A quantization code DT is supplied from the frame decomposition circuit 12 via a delay circuit 19 to a zero multiplication circuit 20 to which the quantization step from the selection circuit 15 is supplied. Delay circuits 14.17.19 are additional code recovery circuits 16 and 0 multiplication circuits 20 having a delay amount corresponding to the time required for the quantization Δ' and the minimum value MIN'' to be recovered. The output signal is supplied to the adder circuit 21, and the selection circuit 1
The minimum value from 8 is added to the output signal of the multiplier circuit 20. The output of this adder circuit 21 provides restored data.

The additional code recovery circuit 16 includes a quantization code DT,
Reconstructed data of adjacent images of adjacent blocks from memory 22 is provided. The additional code restoration circuit 16 utilizes the extremely strong correlation between multiple images located above, below, or to the left and right of the boundary between the adjacent block and the current block, and calculates the quantization step Δ' and the minimum value MIN' by the least squares method. restore. This additional code restoration circuit 16 is the same as that described in Japanese Patent Application No. 1982-90602, which was previously proposed by the applicant of the present invention, and therefore a detailed explanation thereof will be omitted.

The restored data from the adder circuit 21 is supplied to the scanning inverse conversion circuit 23. The scan inverse conversion circuit 23 rearranges the data arrangement from the block order to the scan line order, contrary to the scan conversion circuit 2 provided on the transmission side. Restored video data is obtained at the output terminal 24 of the scan inverse conversion circuit 23.

An example of the scan conversion circuit 2 is shown in FIG. 2, in which one field of digital video data is sequentially written into a field memory indicated by 31. Field memory 31 is supplied with an address signal from address generation circuit 32 .

A sample clock from the terminal 33 and a clock obtained by dividing this sample clock into 1716 by the frequency dividing circuit 34 are supplied to the address generation circuit 32. A write address for writing data into the field memory 31 is formed from the sample clock.

Further, a clock obtained by dividing the line clock from the terminal 35 into 1/4 by a frequency dividing circuit 36 is supplied to the address generating circuit 32. Furthermore, the sample clock from terminal 37 is R
An address control signal for forming a read address is supplied from the ROM 38 to the address generation circuit 32. The read addresses are set so that the spatial boundaries between blocks are non-linear, such that the output data has the block structure shown in FIG. 3, for example.

FIG. 3 shows an example of configuring a block consisting of 16 pixels, with two blocks above and below a block 3 in the center, representing multiple blocks provisionally divided by (4×4) as blocks 1 to 5. 1 and block 5 are located, and block 2 and block 4 are located on the left and right thereof. The number within each pixel indicated by a white circle indicates the block number, and the pixels forming block 3 are indicated by double circles.

As can be seen from FIG. 3, the boundaries between the blocks are not rectangular, but are regions surrounded by non-straight lines that are uneven.

The address control signals written in the ROM 38 are generated in the order shown in FIG. The line numbers in Figure 3 are expressed as (n, n+1...., n+5), and the sample numbers are expressed as (m, m+1,..., m+5). As shown, (n
, m+3) (n+1, m + 3) (n + 1
, m+4) (n+1, m+5)... (n+5, m
+2) address control signals are generated sequentially. Therefore, the data of the 16 pixels of block 3 in FIG. 3 are sequentially read out from the field memory 31. When the reading of the 16 pixel data of block 3 is completed, the value of n is incremented by (+4), the value of m is incremented by (+4), and the pixel data constituting the next block is read out.

The field memory 31 is composed of two field memories, and when input data is being written to one field memory in a certain field period,
Data is read from the other field memory.

The block structure in which the boundaries between blocks are non-linear is not limited to the example shown in FIG. 3.

FIG. 5 shows another example of a block structure to which the present invention is applied. In the example shown in FIG. 5, blocks are constructed by replacing pixels along the boundaries of rectangular areas.

Further, the present invention is applicable not only to ADRC in which pixel data is converted into fixed length data for each two-dimensional block, but also to variable length ADRC in which pixel data is converted into variable length data. In addition, ADR such as block encoding in which pixel data within a block is encoded into a 1-bit code signal using the average value and standard deviation representative of the block as additional codes.
It can also be applied to other than C.

〔Effect of the invention〕

In this invention, since the block boundaries are non-linear, it is possible to avoid the block boundaries from coinciding with the edges of the image. Therefore, when additional data representing a block turns out to be error data, the additional code can be favorably interpolated using reconstructed data that has a very strong correlation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of this invention, FIG. 2 is a block diagram of an example of a scan conversion circuit, FIG. 3 is a route diagram showing an example of a block structure in which this invention is applied, and FIG. 4 is a block diagram of an example of a scan conversion circuit. FIG. 5 is a route map used to explain the scan conversion circuit, FIG. 5 is a route map showing another example of the block structure to which the present invention is applied, and FIG. 6 is a route map used to explain the conventional block structure. Explanation of main symbols in the drawings 1: Digital video signal input terminal, 2: Scan conversion circuit, 1 (l transmission line, 16: Additional code recovery circuit, 23: Scan inverse conversion circuit.

Claims (1)

[Claims] In a block encoding device that compresses and encodes each block of predetermined pixels using a bit number smaller than the number of bits of original pixel data and transmits the data, the spatial boundaries between the blocks are non-linear. A block encoding device characterized in that a block structure such as the following is selected.