JPH02192732A - Manufacture of thin film transistor - Google Patents

Abstract

PURPOSE:To make it possible to control threshold voltage without reducing an ON-current by a method wherein a non-doped layer and a doped layer are laminated on a gate insulating film, and a part, which comes into contact with an ohmic electrode, of the doped layer is removed before the formation of the ohmic electrode. CONSTITUTION:A gate electrode 9 having a prescribed pattern and a gate insulating film (an SiN film) 2, with which the electrode G is covered, are formed on an insulative substrate (a glass substrate) 1 and a non-doped semiconductor operating layer (a B-doped a-Si layer) 4 and a one conductivity type impurity-doped semiconductor layer (a non-doped a-Si layer) 3 are formed in order thereon. Then, a resist film 5 aligned to the electrode G is formed on the layer 3, the exposed parts of the layer 3 are removed using the film 5 as a mask and an opposite conductivity type impurity-doped semiconductor layer (an n<+> a-Si layer) 6 and a metal film (a Ti film) 7 are formed in order on the layer 3 including the film 5. Then, the film 5 is removed and a lift-off of the film 7 and the layer 6, which are adhered on the film 5, is performed to form source and drain electrodes S and D. Thereby, as a loss of voltage is not generated at the time of operation, a reduction in an ON-current can be prevented.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a method for manufacturing an inverted staggered thin film transistor used for driving a liquid crystal display device, electroluminescence (EL), etc., which can increase the dark value voltage without causing a decrease in on-current. The purpose of controlling the off-state current is to suppress off-state current by forming a gate electrode having a predetermined pattern on an insulating substrate, a gate insulating film covering the gate electrode, and a non-doped operating semiconductor layer and one conductivity type impurity thereon. A resist film aligned with the gate electrode is formed on the semiconductor layer doped with an impurity of one conductivity type, and then, using the resist film as a mask, a semiconductor layer doped with an impurity of one conductivity type is formed. An exposed portion of the semiconductor layer doped with a type impurity is removed, and then a semiconductor layer doped with an opposite conductivity type impurity and a metal film are sequentially formed on the semiconductor layer including the resist film, and then,
The method includes a step of removing the resist film and lifting off a semiconductor layer doped with an impurity of a conductivity type opposite to that of the metal film attached thereon.

[Industrial application field]

The present invention relates to a liquid crystal display device, an electroluminescence (
The present invention relates to a method of manufacturing an inverted staggered thin film transistor used for driving an EL device, etc.

Active matrix display devices are used as thin display devices for information terminals together with simple matrix display devices, and liquid crystal is often used as the display medium.

Comparing the characteristics of the two, the active matrix type can drive a large number of pixels independently,
Therefore, even if the number of lines increases with an increase in display capacity, unlike the simple matrix type, problems such as a decrease in contrast I and a decrease in viewing angle due to a decrease in driving duty ratio do not occur.

In thin film transistors used in active matrix display devices, when the leakage current of the thin film transistor (TPT) as a switching element when off exceeds a certain level, the effective voltage applied to the liquid crystal cell fluctuates, resulting in a decrease in display quality. There's a problem. This problem occurs conspicuously in, for example, the gate-connected opposed matrix type active matrix proposed in Japanese Patent Application No. 61-212696.

Therefore, in active matrix display devices, impurities are added to part or all of the active semiconductor layer constituting the channel region of the TPT to control the dark voltage.
This reduces leakage current when the device is off.

[Conventional technology]

The structure of a conventional TPT and its manufacturing method will be explained with reference to FIG. 3(a).

The TPT shown in the figure is an electronic accumulation type TP.
This is an example in which the active semiconductor layer 4 is doped with B (boron). The source/drain electrodes S and D have a laminated structure of an n''a-3i layer 6 as a blocking layer formed on the active semiconductor layer 4 to suppress hole current, and a metal film 7 disposed thereon. has.

To manufacture the TPT having the above structure, first, a metal film such as a Ti (titanium) film is formed on an insulating substrate 1 such as a glass substrate, and the gate electrode G is formed by patterning this.

On top of that is a gate insulating film 2 such as a 5iN (silicon nitride) film, and an a-3i (B-doped) active semiconductor layer 4.
Amorphous silicon) layers are stacked.

A resist film (not shown) is formed on this p-type active semiconductor layer 4 in a self-aligned manner with the gate electrode G, and a source film is formed on the n″aSiaSi layer 6 on the exposed surface of the active semiconductor N4. Drain electrode S.

A metal film 7 constituting D is formed.

The n''a-3i layer 6 acts as a contact layer for realizing ohmic contact between the metal film 7 and the active semiconductor layer 4, and as a blocking layer for suppressing hole current.

After this, the resist film is removed and the TPT film as shown in the figure is formed.
is completed.

As mentioned above, in the conventional TPT, p-type impurities such as B are added to the active semiconductor layer 4 in the electron accumulation type.
In the hole accumulation type, by doping n-type impurities and doping impurities of the opposite conductivity type into the blocking layer 6, off-current is suppressed.
The energy barrier between the active semiconductor layer 4 and the metal film 7 is reduced.

[Problem to be solved by the invention]

Operating semiconductor layer 4 of the electron accumulation type TPT
Since is p-type, a p/n" junction occurs at the interface with the source/drain electrodes S and D. In this configuration, the dark voltage can be shifted in the positive direction by doping B into the active semiconductor layer 4. However, there is a problem in that the on-current decreases due to voltage loss due to the p/n'' interface being biased in the opposite direction during operation.

In the hole accumulation type TPT as well, this problem occurs in the same way as in the electronic accumulation type, since p and n in the above explanation are simply interchanged.

FIG. 3 Φ) is a diagram showing the change in characteristics of TPT doped into the conventional operating semiconductor layer 4. Compared to the characteristics of undoped TPT shown by curve I, when doped,
As shown by the curve ■, the dark value voltage shifts in the positive direction, but the decrease in the on-current during operation cannot be ignored.

SUMMARY OF THE INVENTION In order to solve these difficulties, it is an object of the present invention to suppress the off-state current by controlling the dark voltage without causing a decrease in the on-state current.

[Means to solve the problem]

In order to control the dark voltage, it is sufficient to dope only the channel portion, that is, the upper part of the gate electrode in the active semiconductor layer, and doping to the ohmic electrode portion is not necessary. Further, even if the active semiconductor layer is a non-doped layer on the gate insulating film side, the dark voltage can be controlled.

The present invention has been made from this point of view, and in order to form the active semiconductor layer into a non-doped/doped layer structure from the gate insulating film side, a non-doped layer and a doped layer are stacked as the active semiconductor layer on the gate insulating film. Prior to forming the ohmic electrode, the doped layer in contact with the ohmic electrode is removed by etching, and then the ohmic electrode is formed.

[For production]

By using the above manufacturing method, the interface between the active semiconductor layer and the ohmic electrode has a structure in which the non-doped layer and the n1 layer are in contact with each other in the electron accumulation type, and the non-doped layer and the p' layer are in contact with each other in the hole accumulation type.
No voltage loss occurs during operation. Therefore, since the doped layer is present in the channel portion, the dark voltage can be controlled to shift in the positive direction without reducing the on-state current.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1(a) to (C). In this example, the active semiconductor layer is a −3i
An example will be explained below.

[See FIG. 1(a)] A gate electrode made of a metal such as Ti is formed on an insulating substrate such as the glass substrate 1, and is grown by plasma chemical vapor deposition (P-CVD). A SiN film 2 with a thickness of about 3000 as a gate insulating film and a SiN film 2 with a thickness of about 1 as an active semiconductor layer.
An undoped a-3i layer 3 having a thickness of about 100 mm and a B-doped a-3i layer 4 having a thickness of about 100 mm are successively deposited.

The film forming conditions for each of these layers are as follows: SiN film 2 has a reaction pressure of approximately 0.
．． 2Torr, 5iHn and NH flow rate ratio is approximately 1:
5. The discharge power is about 50W, and the non-doped A-3T layer 3 has a reaction pressure of about 0. The flow rate of 7Torr 5iHn is about 50sec, the discharge power is about 30W1, and the reaction pressure of B-doped a-3i layer 4 is about 017Torr, B
2 The flow rate ratio of H6 and SiH4 is approximately 10-3. The discharge power was approximately 30W.

[See figure (b)]

Next, a resist film 5 for etching the B-doped Me layer 4 and lifting off the ohmic electrode is formed.

Using this resist film 5 as a mask, gas plasma etching is performed to remove the exposed portion of the B-doped aSi layer 4.

The above gas plasma etching conditions are such that the reaction pressure is approximately 0.
, 3Torr, CFa and 0! The flow rate of each is approximately 10
1005c and 5sccm, and the discharge power was approximately 100W.

[See figure (C)]

Next, while leaving the resist film 5, the n''a-3i layer 6 doped with P (phosphorus) was heated to a reaction pressure of about Q, 5 Torr.
r, PH: The flow rate ratio of SiH4 to l is approximately 0.5%,
The discharge power was about 50 W, the resist film was formed to a thickness of about 500 mm, a Ti film 7 was formed thereon to a thickness of about 100 mm, and finally the resist film was removed. The n″a-3i layer 6 and Ti film 7 deposited thereon are lifted off,
Source/drain electrodes S and D are formed.

The TPT manufactured in this example as described above has B-doped a-3i directly below the source/drain electrodes S and D.
Since the layer 4 is removed in advance, the active semiconductor layer in contact with the n0a-3i layer 6 becomes the non-doped a-3i layer 3.

Therefore, since no p/n" junction is formed in this part, no voltage loss occurs during operation. Therefore, a decrease in on-current can be prevented. On the other hand, the channel part is doped with B-doped a-
Since the 3i layer 4 is present, the dark value voltage can be shifted in the positive direction as before.

In the above embodiment, an example was explained in which an electron accumulation type TPT in which the active semiconductor layer was doped with B was manufactured using the present invention. However, when manufacturing a hole accumulation type TPT, an impurity-doped active semiconductor layer The layer 4 is doped with P (phosphorus) or As (arsenic) instead of B, and the n"a-3i layer 6 is doped with p'"a.
-3i layer may be used. In addition, the active semiconductor layer is a-3i
Polycrystalline (poly) St can also be used instead of the layer.

Figure 2 shows the drain current 1d - gate voltage Vg characteristics of the TPT (curve ■) manufactured in the above example, and the TPT (curve ■) whose dark voltage was controlled by doping in the conventional example.
) and TPT without dark value control by doping.
(Curve I).

From the figure, it will be understood that by using the present invention, it is possible to suppress the decrease in on-current and shift control of the dark value in the positive direction.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to control the dark value voltage with almost no decrease in on-current compared to non-doped TPT.

[Brief explanation of the drawing]

Figures 1 (a) to (C) are diagrams showing one embodiment of the present invention in the order of manufacturing steps, Figure 2 is an explanatory diagram of the effects of the above embodiment, and Figures 3 (a) and (b) are diagrams showing the conventional manufacturing process. FIG. 2 is an explanatory diagram of a problem with TFT. In the figure, 1 is an insulating substrate (glass substrate), 2 is a gate insulating film, 3 is a non-doped active semiconductor layer (a-3i layer), and 4 is an impurity-doped active semiconductor layer (p-type a-3i layer).
i layer), 5 is a resist film, 6 is a blocking layer (n”a
-3i layer), 7 is a metal film (Ti film), and G, S, and D are a gate electrode, a source electrode, and a drain electrode, respectively. Figure 1 IQ Q Vg (V) So-huge (Sha 6-day - Detective Z force 4-49.) Tashika Shimo offering day] "l [Z Figure 2 (b) vg (V) Summer

Claims (1)

[Claims] A gate electrode (G) having a predetermined pattern on an insulating substrate (1), and a gate insulating film (2) covering the gate electrode.
), a non-doped operational semiconductor layer (4) and a semiconductor layer (3) doped with an impurity of one conductivity type are sequentially formed thereon, and then a semiconductor layer (3) doped with an impurity of one conductivity type is formed.
A resist film (
Next, using the resist film (5) as a mask, the exposed portion of the semiconductor layer (3) doped with one conductivity type impurity is removed, and then the semiconductor layer (3) including the resist film (5) is removed. 3) A semiconductor layer (6) doped with impurities of opposite conductivity type and a metal film (7) are sequentially formed on the resist film (5), and then the resist film (5) is removed and the metal film (7) attached thereon is deposited. ) and a step of lifting off a semiconductor layer (6) doped with an impurity of the opposite conductivity type.