JPH0218784A - Sense amplifier circuit - Google Patents

Abstract

PURPOSE:To shorten an amplifying time by change the connection of the supplying line of a power source, which is temporarily connected to a common source node, to the power source of a high voltage so that the operating voltage of a transistor, which constitutes a sense amplifier circuit, can be much higher during the amplifying period of the sense amplifier circuit. CONSTITUTION:By connecting the common node of a flip-flop type or current mirror type sense amplifier circuit, which is composed of the plural transistors, through a first switch element 6 to the supplying line of a first power source voltage 6, the sense amplifier circuit 1 is activated and the amplification of fine potential difference between a pair 2 of bit lines is started. Further, the supplying line of a second power source voltage 5 and common node are connected through a second switch element 3 so that the operating voltage of the transistor, which constitutes the sense amplifier circuit 1, can be higher than the first power source voltage 6. Thus, the current driving ability of the transistor can be improved and the amplifying time can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a sense amplifier circuit used in a semiconductor memory circuit.

2. Description of the Related Art A conventional sense amplifier circuit and its operation will be explained with reference to FIGS. 6 to 8.

First, FIG. 6 is a circuit diagram of a conventional P-type sense amplifier, in which 1 is a P-type flip-flop circuit, 2 is a bit line pair,
Reference numeral 3 denotes a switch element for connecting the common source node of the P-type flip-flop circuit 1 to the internal power supply vcce which is stepped down from the external power supply Vcc5.

Next, the operation will be explained using FIG. 6.

First, by reading the memory cell, a potential difference ΔV is generated in the bit line pair 2. Next, in order to amplify the potential difference ΔV, the switch element 3 is turned on and the flip-flop circuit 1 is activated.

Furthermore, FIG. 7 is a circuit diagram of a conventional N-type sense amplifier, in which 10 is an N-type flip-flop circuit, 2 is a bit line pair, and 30 is a common source node of the N-type flip-flop circuit 30 connected to an external power source. This is a switch element that should be connected to Vss50. Further, the substrate potential of the N-type MO3 transistor constituting the flip-flop circuit 10 and the switch element 30 is fixed to the potential VBB output from the substrate bias generation circuit 40.

Next, the operation will be explained using FIG.

First, by reading the memory cell, a potential difference ΔV is generated in the bit line pair 2. Next, in order to amplify the potential difference ΔV, the switch element 30 is turned on to activate the flip-flop circuit 1Q.

Problems to be Solved by the Invention However, in order to ensure the reliability of the oxide film in the memory cell, if the power supply voltage of the memory cell section is lowered, naturally,
The operating voltage of the flip-flop circuit 1 will be reduced accordingly. On the other hand, if the threshold value vth of the transistor constituting the flip-flop circuit remains unchanged, the current drive capability of the transistor will decrease as can be solved from equation (1).

...(1) In formula (1), Ib1t is the charge/discharge current, W is the gate width of the transistor, L is the gate length of the transistor, and μ
is the mobility, COX is the gate oxide film capacitance of the transistor, vbt is the potential of the bit line, and Vs is the potential of the common source node.

This means that the current drive capability of the transistor decreases.
This means that the charging and discharging current driving capability of the bit line is reduced, and the time required for amplification becomes longer, resulting in a reduction in the read speed of the memory.

The above problems will be solved in the future as semiconductor memory becomes smaller.

This is an extremely important issue as power supply voltage tends to decrease due to reliability issues as density increases.

In view of the above-mentioned problems, the present invention aims to realize a sense amplifier circuit capable of high-speed reading.

Means for Solving the Problems The present invention provides a means for connecting a common node of a flip-flop type or current mirror type sense amplifier circuit composed of a plurality of transistors to a first power supply voltage supply line via a first switch element. and further connect the common node to a second power supply voltage supply line having a voltage higher than the first power supply voltage via a second switch element. The present invention provides a sense amplifier circuit that uses a switch element to temporarily switch and amplify a power supply voltage supply line connected to the common node from a first power supply voltage to a second power supply voltage. be.

Effect of the present invention is to connect a common node of a flip-flop type or current mirror type sense amplifier circuit composed of a plurality of transistors to a first power supply voltage supply line through a first switch element. The sense amplifier circuit is activated to start amplifying the minute potential difference ΔV on the bit line 7↑, and then the first power supply voltage is applied to the transistors constituting the sense amplifier circuit through the second switch element. By connecting the second power supply voltage supply line and the common node so that the operating voltage is high, the current driving ability of the transistor can be increased, and a high-speed sense amplifier circuit that requires short amplification time can be realized.

Example FIG. 1 shows an example of a sense amplifier circuit according to the present invention.

The circuit according to the first embodiment of the present invention shown in FIG. 1 basically has the same configuration as the conventional circuit shown in FIG. 2, so the same components are given the same numbers. Detailed explanation will be omitted.

First, to explain the configuration of the sense amplifier circuit shown in the first example, the common source node of the flip-flop circuit 1 consisting of two P-type MO3 type transistors is connected to the first switch element 6 consisting of a PIMO8 type transistor. Through,
Connect to the internal power supply voltage vccs supply line. here,
Vcc is a power supply voltage obtained by lowering the external power supply voltage 6 by the down converter 4.

Furthermore, the common north node is connected to the external power supply voltage 5 via a second switch element 3 consisting of a P-type MO5 transistor.
Connect to the supply line.

The operation of this sense amplifier circuit will be explained using FIG.

By raising the word line, the memory cell is read, and a potential difference ΔV is generated in the bit line pair 2.

Thereafter, the sense amplifier control signal 10 is set low to turn on the first switch element 6 and connect the common source node to the supply line of Vcc6. Then, the sense amplifier circuit 1 is activated and starts amplification.

However, as explained in the conventional example, since the power supply voltage is stepped down, the operating voltage of the transistors constituting the P-type flip-flop circuit 1 is low, and the current driving ability is reduced. Therefore, there was a problem that the time required for amplification became longer. However, in the first embodiment, in order to accelerate amplification, the sense amplifier control signal 1o is set to high and the control signal 2Q is set to low. Reconnecting the supply line of the internal power supply voltage Vcc 6 connected to the common source node of the type flip-flop 7 circuit 1 with the supply line of the external power supply voltage Vcc 5,
The operating voltage of the transistors constituting the P-type flip 70 tube circuit 1 is increased to increase the current and driving ability. After the amplification is accelerated, the line pair 2) becomes the internal power supply voltage Vcc.
By setting the sense amplifier control signal 1 to low and the control signal 2 to high at the timing when the bit line pair 2 is amplified to the voltage level of e, it is confirmed that the bit line pair 2 is amplified to a voltage level higher than that of the internal power supply voltage Vcc 6. prevent. Further, since the substrate potential of each transistor is fixed at a high voltage Vccs, the source and drain regions of each transistor are not in a forward bias relationship with respect to the substrate, so there is no problem of leakage.

As described above, in the first embodiment, P
type sense amplifier circuit can be realized.

Next, FIG. 3 shows a circuit example of a second embodiment of the present invention.

To explain the configuration of the sense amplifier circuit shown in FIG. 3, the common source node of the flip-flop circuit 1 consisting of two N-type MOS transistors is connected to the N-type MO8).
Via the first switch element 70 consisting of a transistor,
Connect to the supply line of external power supply Vss 60. Further, the common source node is connected to a supply line for the substrate potential VBH generated by the substrate bias generation circuit 4o via a second switching element 3° made of an N-type MOS transistor.

The operation of this sense amplifier circuit will be explained using FIG. 4.

By raising the word line, the memory cell is read out, and a potential difference ΔV is generated between the bit line pair 2.

Thereafter, the sense amplifier control signal 100 is set high to turn on the first switch element 7o and connect the common north node to the supply line of Vss 50.

Then, the sense amplifier circuit 1o is activated and starts amplification. However, as explained in the conventional example, since the power supply voltage is stepped down, the operating voltage of the transistors forming the sense amplifier circuit 10 is low, and the current driving ability is reduced. Therefore, there was a problem that the time required for amplification became longer, but in the aE2/7i11i example, in order to accelerate amplification, the sense amplifier control signal 100 is set high and the -1 control signal 200 is set high. , sense amplifier circuit 10
connected to a common source node. Vssso
Reconnect the supply line with the supply line of substrate potential VBB 60.

The operating voltage of the transistors constituting the N-type flip 70 tube circuit 10 is increased to increase the current driving ability. After the amplification is accelerated, at the timing when bit line pair 2 is amplified to the voltage level of Vss 50, bit line pair 2 is set to Vss by setting the sense amplifier control signal 100 to NO and setting the control signal 200 to low. Prevents the voltage from going below a voltage level of 50.

Father, the substrate potential of each transistor is a low voltage VBB
60, the source and drain regions of each transistor are not in a forward bias relationship with respect to the substrate, so there is no problem of leakage.

As described above, in the second embodiment, N
type sense amplifier circuit can be realized.

Further, as can be easily considered, a CMOS sense amplifier circuit that combines the first embodiment and the second embodiment of the present invention can of course be easily realized.

Effects of the Invention According to the present invention, the operating voltage of the sense amplifier circuit decreases and the amplification time increases due to the internal power supply voltage becoming lower due to the reliability of the oxide film of the memory cell. The problem is that during the amplification period of the sense amplifier circuit, the operating voltage of the transistors forming the sense amplifier circuit becomes higher. This problem can be solved by changing the connection to a higher voltage power supply line, which has great practical effects.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG. 2 is a circuit diagram of a first embodiment of the present invention.
FIG. 3 is a circuit diagram of the second embodiment of the present invention, FIG. 4 is an explanatory diagram of the operation of the circuit of the second embodiment, and FIGS. Conventional circuit diagrams, FIG. 6 and FIG. 8 are explanatory diagrams of the operation of the conventional circuit. 1...P-type flip-flop circuit, 2...
...Bit line pair, 3, 8, 30, 70...
- Switch element, 5.60... Second power supply voltage, e, 60... First power supply voltage. Name of agent: Patent attorney Shigetaka Awano and one other person. IL Fig. Fig. If) Fig. Fig. Potential chart

Claims (4)

[Claims] (1) A common node of a flip-flop type or current mirror type sense amplifier circuit composed of a plurality of transistors is connected to a first power supply voltage supply line via a first switch element, and further the common node is connected to a second power supply voltage supply line having a voltage higher than the first power supply voltage through a second switch element, and the first switch element and the second switch element are used to temporarily A sense amplifier circuit characterized in that a power supply voltage supply line connected to the common node is switched from the first power supply voltage to a second power supply voltage for amplification. (2) Generate the first power supply voltage with a down converter,
2. The sense amplifier circuit according to claim 1, wherein the second power supply voltage is an external power supply voltage. (3) A common node of a flip-flop type or current mirror type sense amplifier circuit composed of a plurality of transistors is connected to a first power supply voltage supply line via a first switch element, and the common node is further connected to A second power supply voltage supply line having a voltage lower than the first power supply voltage is connected through a second switch element, and the first switch element and the second switch element are used to temporarily A sense amplifier circuit characterized in that a power supply voltage supply line connected to the common node is switched from the first power supply voltage to a second power supply voltage for amplification. (4) The sense amplifier circuit according to claim 3, wherein the first power supply voltage is an external power supply voltage, and the second power supply voltage is generated by a substrate bias generation circuit.