JPH02186618A - Manufacture of integrated circuit - Google Patents
Manufacture of integrated circuitInfo
- Publication number
- JPH02186618A JPH02186618A JP630189A JP630189A JPH02186618A JP H02186618 A JPH02186618 A JP H02186618A JP 630189 A JP630189 A JP 630189A JP 630189 A JP630189 A JP 630189A JP H02186618 A JPH02186618 A JP H02186618A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- circular
- wafer
- electron beam
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 6
- 238000000034 method Methods 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 4
- 238000010894 electron beam technology Methods 0.000 abstract description 10
- 235000012431 wafers Nutrition 0.000 description 13
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
Landscapes
- Electron Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は集積回路の製造方法に関し、特に電子ビーム露
光装置を用いてマスクパターンを形成する際の識別パタ
ーンの形成法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing an integrated circuit, and more particularly to a method of forming an identification pattern when forming a mask pattern using an electron beam exposure apparatus.
従来、電子ビーム露光装置を用い、ウェーハ上に集積回
路のパターンを形成する際に、複数種類の拡散および配
線工程に対応するパターンを重ね合せる必要があるが、
その際に使用する目合せパターンの形状は第４図（ａ）
〜（ｂ）に示す様に棒状や矩形状またはその組合された
形状となっている。Conventionally, when forming integrated circuit patterns on wafers using electron beam exposure equipment, it is necessary to overlay patterns corresponding to multiple types of diffusion and wiring processes.
The shape of the alignment pattern used in this case is shown in Figure 4(a).
As shown in ~(b), it has a rod shape, a rectangular shape, or a combination thereof.
ｒ発明が解決しようとする課題〕
上述した従来の電子ビーム露光装置を用いた直接描画法
によって集積回路の拡散工程、配線工程に対応するパタ
ーンを重ね合わせる際には、電子ビーム露光装置から出
る電子ビームで目合せパターンを走査し、走査して得ら
れる電子ビームの反射信号を電気信号に変換し、正確な
位置を計測し、重ね合わせのパターンの位置精度の向上
をはかつている。rProblems to be Solved by the Invention] When overlapping patterns corresponding to the diffusion process and wiring process of integrated circuits by the direct writing method using the conventional electron beam exposure apparatus described above, the electrons emitted from the electron beam exposure apparatus are The alignment pattern is scanned with a beam, and the reflection signal of the electron beam obtained by scanning is converted into an electrical signal to measure the accurate position, thereby improving the positional accuracy of the overlapping pattern.
しかしながら目合せパターンの形状が第４図に示す様に
矩形状又は棒状で、チップの種類等を区別するための情
報が含まれていないために同一ウェーハ上に複数種のチ
ップを形成する場合、その確認に手間どり、目合せ作業
が煩雑になるという欠点があった。However, the shape of the alignment pattern is rectangular or bar-like as shown in FIG. 4, and it does not contain information to distinguish the type of chip, so when multiple types of chips are formed on the same wafer, There are disadvantages in that it takes time to confirm and the alignment work becomes complicated.
本発明の集積回路の製造方法は、半導体チップの種類を
区別するための円形または円弧状の識別パターンをウェ
ーハ」二に形成するものである。The integrated circuit manufacturing method of the present invention is to form a circular or arcuate identification pattern on a wafer to distinguish the type of semiconductor chip.
本発明によれば識別パターンか円形または円弧状である
なめ、電子ヒーノ＼の走査方向とウェーハの位置の調整
を時間をかけてする必要はなく、どの方向にウェーハが
置かれていたとしても電子ヒーム走査により位置情報及
びチップの種類の情報を認識することか可能である。年
輪状にパターンを形成すれはその輪の数１輪の位置関係
からコード化された情報として検知することか可能であ
る。According to the present invention, since the identification pattern is circular or arcuate, there is no need to spend time adjusting the scanning direction of the electronic heater and the position of the wafer, and no matter which direction the wafer is placed, the electronic It is possible to recognize position information and chip type information by beam scanning. If a pattern is formed in the shape of annual rings, it is possible to detect it as coded information from the positional relationship of several rings.
次に、本発明の実施例について図面を参照し２て説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１−図は本発明の第１の実施例を説明するための識別
パターンを示ず図である。FIG. 1 is a diagram illustrating a first embodiment of the present invention without showing an identification pattern.
電子ビーム露光装置を用いウェーハー１−に目合ぜパタ
ーンを形成する際に、同時に複数の円形パターン２（２
Ａ〜２Ｅ）からなる識別パターン１を形成する。この円
形パターン２はチップの種類を区別するための情報を含
んたコー１〜となっているため、Ｌ］、、Ｌ２で示すよ
うに、電子ビームをとの方向から走査してもこのコー１
〜を電気信号として読み取ることかできる、
第２図は本発明グ）第２の実施例を説明する／ごめのウ
ェーハのＬ面図である。When forming an alignment pattern on a wafer 1- using an electron beam exposure device, a plurality of circular patterns 2 (2
An identification pattern 1 consisting of A to 2E) is formed. Since this circular pattern 2 has codes 1 to 1 that include information for distinguishing the type of chip, even if the electron beam is scanned from the direction shown by L], , L2, this code 1
~ can be read as an electrical signal. Figure 2 is an L-side view of the wafer of the present invention.
第２図に示づ−ように、１枚のウェーハ３上に３種類の
チップＡ、Ｂ、Ｃを形成する場合、各チップの情報を有
する識別パターン］、Ａ、］、Ｒ，］、Ｃを形成する。As shown in FIG. 2, when three types of chips A, B, and C are formed on one wafer 3, an identification pattern containing information about each chip], A, ], R, ], C form.
このように複数個の識別パターン１八〜］Ｃを形成する
場合は、パターンの重ね合せに用いる目合せパターンと
しても利用することがてきる。When a plurality of identification patterns 18 to 1C are formed in this way, they can also be used as alignment patterns for overlapping patterns.
第３し１は本発明の第３の実施例を説明するだめのウェ
ーハの−［−面図である。No. 3 and 1 is a -[-] side view of a blank wafer for explaining a third embodiment of the present invention.
目合ぜパターンを形成する際に、つ工−ハ３の外周部に
複数本の円弧からなる識別パターン］Ｄを形成する。こ
のようにウェーハ３の外周部に識別パターンを形成した
場合は、電子ビームの走査か容易てあろため、識別パタ
ーンからの情報の読み取りは更に容易になるという利点
カーある。When forming the alignment pattern, an identification pattern D consisting of a plurality of circular arcs is formed on the outer periphery of the tool C3. When the identification pattern is formed on the outer periphery of the wafer 3 in this way, it is easy to scan with an electron beam, so there is an advantage that information from the identification pattern can be read more easily.
以上説明したように本発明は、半導体チップの種類を区
別するための円形または円弧状の識別パターンをウェー
ハ上に形成することにより、情報か容易に得られるため
、集積回路の製造におＧ−Ｊる目合せ時間を大幅に短縮
できるという効果がある。As explained above, the present invention is advantageous in the manufacture of integrated circuits because information can be easily obtained by forming a circular or arc-shaped identification pattern on a wafer to distinguish the types of semiconductor chips. This has the effect of greatly shortening the alignment time.
第１図は本発明の第１の実施例を説明するための識別パ
ターンを示す図、第２図及び第３図は本発明の第２及び
第３の実施例を説明するためのウェーハの上面図、第４
図は従来の目合せパターンを示す図である。
１ ］Ａ〜］Ｄ・・・識別パターン、２・・・円形パタ
ーン、３・・・ウェーハ。FIG. 1 is a diagram showing an identification pattern for explaining the first embodiment of the present invention, and FIGS. 2 and 3 are the top surfaces of wafers for explaining the second and third embodiments of the present invention. Figure, 4th
The figure shows a conventional alignment pattern. 1]A~]D...Identification pattern, 2...Circular pattern, 3...Wafer.
Claims (1)
状の識別パターンをウェーハ上に形成することを特徴と
する集積回路の製造方法。A method for manufacturing an integrated circuit, comprising forming a circular or arc-shaped identification pattern on a wafer to distinguish between types of semiconductor chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP630189A JPH02186618A (en) | 1989-01-13 | 1989-01-13 | Manufacture of integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP630189A JPH02186618A (en) | 1989-01-13 | 1989-01-13 | Manufacture of integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02186618A true JPH02186618A (en) | 1990-07-20 |
Family
ID=11634553
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP630189A Pending JPH02186618A (en) | 1989-01-13 | 1989-01-13 | Manufacture of integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02186618A (en) |
-
1989
- 1989-01-13 JP JP630189A patent/JPH02186618A/en active Pending
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