JP2001274067A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacturing method of semiconductor devices, which is contrived so as to be able to identify the positions of a plurality of the semiconductor devices on a wafer. SOLUTION: The manufacturing method of semiconductor devices has a process that semiconductor device patterns are moved in order on a wafer 100 by the width ΔX of regions 101 on the wafer 100, and that the device patterns are exposed in order on the wafer 100, has a first process that scale patterns 102x and 102y are exposed in the direction to coincide with the direction of movement of the device patterns at the time when the device patterns are exposed in order in every region 101, where the device patterns are exposed, and a second process that the device patterns are moved in order on the wafer 100 by a distance (ΔX+A) longer as much as one scale than the width ΔX of the regions 101 moved in order on the wafer when the device patterns are exposed in order, and a mark is exposed to the positions along the scale positions 102x and 102y.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which positions of a plurality of semiconductor devices formed on one wafer can be identified on the wafer.

[0002]

2. Description of the Related Art When manufacturing semiconductor devices such as field effect transistors, a method of forming a plurality of semiconductor devices on one wafer is generally employed. After that, the wafer on which the plurality of semiconductor devices are formed is cut for each semiconductor device, and cut into individual semiconductor devices. in this case,
Before cutting out a semiconductor device, the electrical characteristics of the semiconductor device are measured using, for example, an auto prober, and the semiconductor device is classified into non-defective products and defective products. The semiconductor devices determined to be non-defective are further finely classified according to their electrical characteristics before being sealed in a package or the like.

In the case of ranking, if the position of a semiconductor device on a wafer is known, electrical characteristic data measured on the wafer using an autoprober can be used. However, if individual semiconductor devices cut out from the wafer are mixed in a subsequent process, the position on the wafer cannot be determined, and measurement data on the wafer cannot be used. In such a case, the electrical characteristics of each semiconductor device are measured again, and ranking is performed.

Here, a conventional method for manufacturing a semiconductor device will be described with reference to FIG.

FIG. 4A is a schematic view showing a wafer 400 on which a plurality of semiconductor devices 401, for example, field effect transistors are formed. The electrical characteristics of the semiconductor device 401 are measured by an auto prober, and the scratch mark 40 is added to the semiconductor device 401 determined to be defective.
2 is added. After that, the wafer 400 is cut in the vertical direction m and the horizontal direction n, and the semiconductor devices 401 are cut out one by one. From the cut semiconductor device 401, only non-defective products without the scratch mark 402 are extracted, and FIG.
Are arranged as shown.

Next, as shown in FIG. 4C, the electrical characteristics of the semiconductor device 401 determined to be non-defective are again measured by the auto prober 403, and the semiconductor device 401 is finely classified. In this case, the measurement of the electrical characteristics is performed for items necessary for ranking.

Next, as shown in FIG. 4D, the semiconductor devices 401 are sorted into a product group A or a product group B according to the rank.

[0008]

In the case of the conventional method of manufacturing a semiconductor device, finer semiconductor devices determined as non-defective in the measurement of electrical characteristics are required to be finer in accordance with the electrical characteristics before being sealed in a package. Ranking is performed. In this case, if the semiconductor devices cut out from the wafer are separated and mixed, and the position of the semiconductor device on the wafer is not known, the electrical characteristic data measured on the wafer cannot be used. Therefore, when ranking, one more
Therefore, the electrical characteristics are measured, and the productivity is reduced.
In addition, an error may occur in the measurement of the electrical characteristics for ranking, and the semiconductor device may be damaged, and the re-measurement of the electrical characteristics also causes a reduction in yield.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device which can solve the above-mentioned drawbacks and can identify the positions of a plurality of semiconductor devices on a wafer.

[0010]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of sequentially moving a predetermined distance on a wafer and sequentially exposing the semiconductor device pattern on the wafer. For each region to be exposed, a first step of exposing a scale pattern in a direction coinciding with the movement direction during the sequential exposure, and a distance longer or shorter than the predetermined distance sequentially moving on the wafer during the sequential exposure. A second step of sequentially moving on the wafer and exposing a mark pattern at a position along the scale pattern.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. 1 taking as an example a case where one semiconductor device pattern is exposed on a wafer by one successive exposure.

FIG. 1A is a schematic view showing one wafer 100. The wafer 100 is divided into a plurality of regions 101 in a vertical direction and a horizontal direction, respectively. Each of the regions 101 has a horizontal width of ΔX and a vertical width of ΔY, and one semiconductor device such as a field effect transistor is formed in each region 101. In the drawing, for example, the lowermost area is indicated by reference numerals W00, W10, W20, W30,..., And the upper area is indicated by reference numerals W01, W11, W21, W31,.

When a semiconductor device is formed on the above-described wafer 100, the wafer 100 is set, for example, in a sequential exposure reduction projection device. Then, an arrow Y is drawn on the wafer 100.
1, the mask pattern for forming the semiconductor device is sequentially reduced in the Y2 direction, and each region 1 on the wafer 100 is reduced.
In step 01, a semiconductor device pattern is exposed. For example, first,
The region W00 is exposed with a semiconductor device pattern. Next, the wafer W is moved to an adjacent area W10, and the area W10 is exposed to a semiconductor device pattern. As described above, the semiconductor device pattern is sequentially and sequentially exposed to one laterally located region, for example, regions W00, W10, W20,.

When the exposure of the semiconductor device pattern for one step is completed, the step moves to the next step and the horizontal area in the step, for example,..., W31, W21,.
The semiconductor device pattern is sequentially exposed to W11 and W01. According to such a procedure, the semiconductor device pattern is exposed to the entire region on the wafer 100. The exposed semiconductor device pattern is then formed on the semiconductor device through a process such as printing.

In the above-described semiconductor device pattern exposure process, a scale pattern 102x, 1 is provided for each region 101, for example, scales are provided in the horizontal and vertical directions in the figure.
02y is exposed. Scale pattern 102x, 102y
Are exposed at the same time as the semiconductor device pattern and are provided in a direction coinciding with the moving direction of the sequential exposure. The graduation patterns 102x, 102y are, like the semiconductor device pattern, thereafter subjected to a baking process or the like to produce graduations 102x, 102y.
02y.

The scale patterns 102x and 102y are shown in FIG.
As shown in (b), the mark is formed at a fixed scale interval A. In order to make it easy to read the position on the scale, for example, the starting point is set to 0, and a number such as 5 or 10 is attached every 5 scales from the starting point 0. Have been. On the graduations 102x and 102y, thereafter, in order to show the position of each area 101 on the wafer 100, a mark pattern of a mark as shown in FIG.
The stamp is formed through a process such as baking.

Here, the scales 102x, 102y of the respective areas
Next, a method of forming a mark pattern will be described with reference to FIG. ▽ mark pattern has two scales 102
Exposure is performed in the same manner on x and 102y. For this reason, in the drawing, a case will be described in which a mark pattern is formed along the horizontal scale 102x.

First, in the area W00, a mark pattern is prepared such that a mark is placed at, for example, the starting point 0 of the scale 102x, and the mark is exposed at the position of the starting point "0" of the scale 102x.

Next, the area W10 is moved to the right area W10.
The pattern is exposed. In the case of sequentially exposing a semiconductor device pattern by using a sequential exposure reduction projection apparatus, the moving distance on the wafer 100 at the time of sequential exposure is
Is set to be equal to the width ΔX. However, in the case of exposing the mark pattern, for example, ΔX + A (A is a scale 10
Move by 2 x 1 scale). Therefore, the area W10
Then, the mark “▽” is exposed at the position of the scale “1”.

Next, move to another area W20 on the right side,
The area W20 is exposed with a mark pattern. Also in this case, after the exposure of the mark pattern in the area W10, the mark is exposed by moving by ΔX + A. Therefore, in the area W20, the mark “▽” is exposed at the position of the scale “2”. By repeating such a method, the ▽ marks are sequentially exposed to the respective horizontal regions located at the same level.

After that, when the exposure of the ▽ mark to the horizontal area for one step is completed, the step moves to the next higher step, and the ▽ mark pattern is sequentially exposed for each horizontal area in that step.

In this stage, for example, the exposure area of the mark pattern returns from right to left in the figure. In this case, the position where the mark is exposed is returned extra by X + A on the scale 102x every time the exposure region of the mark pattern moves. Therefore, a mark “▽” is exposed at a position on the scale 102x where the scale is reduced by one.

The above description has been made by sequentially moving in the horizontal direction,
This is a description of a case where a mark “露 光” is exposed on the scale 102x. However, when the exposure region indicated by the mark moves to the upper level, for example, similarly to the case where the exposure area moves in the horizontal direction, the position at which the mark is exposed changes on the vertical scale 102y every time it moves to the upper level. I do.

For example, in the areas W00, W10, W20,..., A mark is exposed at the starting point on the scale 102y, that is, at the position of the scale "0". Areas W01, W11, W2 one level above
At 1, W31, for example, the mark is moved by ΔY + A (A is one scale on the scale 102y), and the mark “▽” is exposed at the position of the scale “1” on the scale 102y.

According to the above method, in the case of the area W00,
On the scale 102x, the mark ▽ is formed at the position of the starting point “0”, and thereafter, each time the exposure position moves once, the mark ▽ is formed at a scale position shifted by one scale A. For example, in the n-th exposure position in the same horizontal direction, a mark is formed at a scale position shifted by n × A.

In the case of the area W00, a mark "▽" is formed at the starting point "0" on the scale 102y. Thereafter, each time the exposure position is moved up and down by one step, a mark "▽" is formed at a position shifted by one scale A. Is formed. For example, when it is moved upward or downward by n steps, a mark ▽ is formed at a scale position shifted by n × A on the scale 102y.

Therefore, in the region of the semiconductor device located at the n-th exposure in the X direction from the starting point and at the m-th stage in the Y direction from the starting point, a mark に is placed at the position of the scale “n” on the scale 102x. And the scale “m” on the scale 102y.
Mark is added to the position of.

Conversely, as shown in FIG. 2, a mark "3" is placed at the position of the scale "3" on the scale 102x.
If the mark on the scale “1” is marked on y,
The region is the third exposure position in the horizontal direction from the starting point, and the third exposure position from the starting point, and the position of the semiconductor device on the wafer is identified.

Next, another embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. In this embodiment, a plurality of semiconductor device patterns are exposed by one exposure using a sequential exposure reduction projection device. FIG. 3 shows, for example, four regions W1 to W4 which are vertically and horizontally adjacent to each other on the wafer. The figure shows a case where a device pattern is exposed, and in the subsequent exposure, a semiconductor device pattern is exposed in each of a region W3 and a region W4.

In this case, in order to distinguish two regions where the semiconductor device pattern is simultaneously exposed, for example, the region W1 and the region W2, for example, different number patterns (1) are used.
(2) is used, the number pattern (1) is exposed to the area W1, and the number pattern (2) is exposed to the area W2.
These number patterns (1) and (2) are scales 102x,
The exposure is performed simultaneously with the exposure of the 102y pattern. Similarly, the number pattern (1) is exposed to the area W3, and the number pattern (2) is exposed to the area W4.

The positions from the starting point when exposing the semiconductor device pattern to the regions W1 and W2 and the regions W3 and W4 are positioned on the scales 102x and 102y in the same manner as described with reference to FIGS. Are identified by the positions marked with a ▽.

For example, in the areas W1 and W2, the scale 10
The scale “2” on 2x is marked with a triangle, and the scale “1” on the scale 102y is marked with a triangle. This indicates that the exposure position is the second exposure position in the horizontal direction (x direction) from the starting point and the first exposure position in the upward direction (y direction) from the starting point. The number patterns (1) and (2) indicate that the area W1 is the first chip at the same exposure position as the area W2,
The region W2 is the second chip at the same exposure position as the region W1.

In the embodiment shown in FIG. 3, a case where two semiconductor device patterns are exposed by one exposure is described.
However, even when three or more semiconductor device patterns are exposed in one exposure, if three or more different number patterns are exposed to a region where the semiconductor device patterns are simultaneously exposed, the wafer of each semiconductor device pattern is exposed. The upper position is identified.

In each of the above embodiments, the position of the semiconductor device on the wafer is described only in the plus direction in both the X and Y directions. However, if scales in the minus direction are provided on the scales 102x and 102y, the present invention can be applied to the case of moving in the minus direction.

In the above embodiment, the moving distance for sequentially moving the mark pattern at a position along the scale pattern is one time smaller than the predetermined distance for sequentially moving on the wafer during the sequential exposure. It is lengthened by the scale. In this case, the position of the mark coincides with the scale, the position on the scale marked with the mark can be easily read, and the position of the semiconductor device on the wafer can be quickly identified. However, it is not always necessary to increase the length by one graduation of the graduation pattern. For example, the graduation pattern can be lengthened by an integral fraction.
Also, the length of the scale pattern can be shortened by one graduation without being lengthened, or can be shortened by an integral fraction of one graduation.

In each of the above embodiments, the case where the semiconductor device is a field-effect transistor has been described. However, the present invention can be applied to semiconductor devices other than the field-effect transistor.

The shape of the scale pattern, the number pattern, and the symbol “▽” described in the above embodiment are merely examples, and the scale pattern, the number pattern, and the symbol “▽” of other shapes may be used.

As described above, according to the present invention, position information on a wafer is added to each region where a semiconductor device is formed. Therefore, even after the semiconductor device is cut out and mixed, the semiconductor device is marked on the scale.
By observing the marks and numbers, the position of the semiconductor device on the wafer can be easily read. Therefore, when a semiconductor device is ranked using electric characteristics, electric characteristic data measured on a wafer using an auto blower or the like can be used. As a result, it is not necessary to repeatedly measure the electrical characteristics of the semiconductor device, and it is possible to provide a method of manufacturing a semiconductor device capable of reducing the manufacturing cost.

[0039]

According to the present invention, a method of manufacturing a semiconductor device in which the positions of a plurality of semiconductor devices on a wafer can be identified.

[Brief description of the drawings]

FIG. 1 is a schematic diagram for explaining an embodiment of the present invention.

FIG. 2 is a schematic diagram for explaining a method of identifying a position on a wafer of a semiconductor device according to the present invention.

FIG. 3 is a schematic diagram for explaining another embodiment of the present invention.

FIG. 4 is a schematic diagram for explaining a conventional example.

[Explanation of symbols]

 100: Wafer 101: Area for dividing the area on the wafer ΔX: Horizontal width of the area ΔY: Vertical width of the area 102x: Horizontal scale 102y: Vertical scale A: 1 scale interval Δ mark Marks attached along the scale

Claims (6)

[Claims] 1. A method of manufacturing a semiconductor device, comprising the steps of: sequentially moving a predetermined distance on a wafer and sequentially exposing a semiconductor device pattern on the wafer, wherein the sequential exposure is performed for each region where the semiconductor device pattern is exposed. A first step of exposing a graduation pattern in a direction coinciding with a moving direction at the time, and sequentially moving on the wafer by a distance longer or shorter than the predetermined distance to sequentially move on the wafer during the sequential exposure, A second step of exposing the mark pattern to a position along the scale pattern. 2. A method of manufacturing a semiconductor device, comprising the steps of sequentially moving a predetermined distance on a wafer and sequentially exposing a semiconductor device pattern to a plurality of regions on the wafer simultaneously. A first step of exposing a scale pattern in a direction coinciding with a moving direction in said sequential exposure, a second step of exposing different code patterns to a plurality of regions simultaneously exposing a semiconductor device pattern, and A third step of sequentially moving on the wafer by a distance longer or shorter than the predetermined distance moving on the wafer in order, and exposing a mark pattern at a position along the scale pattern. Method. 3. The method according to claim 2, wherein the first step and the second step are performed in the same exposure step. 4. The method according to claim 1, wherein the step of exposing the semiconductor device pattern and the first step are performed in the same exposure step. 5. A moving distance that is sequentially moved when exposing a mark pattern at a position along the scale pattern is longer or shorter by one scale of the scale pattern than a predetermined distance that sequentially moves on a wafer during sequential exposure. Claim 1
A method for manufacturing a semiconductor device according to claim 2. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the graduation pattern in the direction coinciding with the moving direction in the sequential exposure is exposed in two directions orthogonal to each other.