JPH0845830A - Aligner - Google Patents

Abstract

PURPOSE:To provide alignment marks, without occupying chip regions, by forming the alignment marks on other blank regions of the chip regions than the main body of chip among many chip regions arranged in all directions. CONSTITUTION:A chip region 20 is composed of an essential chip part 21 and blank region 22 at the periphery of the chip part. In respect of the region 22, alignment marks 23 are previously formed on a semiconductor wafer 12. A photomask is provided with alignment marks composed of light screens at regions facing the marks 23 on the lower face of the mask. Thus, the alignment marks does not occupy the chip region and hence more chips can be produced from one semiconductor wafer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure apparatus for performing alignment when a chip pattern of a photomask is printed on a semiconductor wafer by batch projection exposure of equal size.

[0002]

2. Description of the Related Art Conventionally, in an exposure apparatus (proximity mask aligner) which adopts 1 × batch projection exposure, etc., an alignment mark when a chip pattern of a photomask is printed on a silicon wafer etc. by 1 × batch projection exposure is For example, as shown in FIG. 8, among a large number of chips 2 arranged vertically and horizontally on a semiconductor wafer 1 (or a photomask), a plurality (6 in the case shown) of chips 2a.
It is provided for (shaded). The individual alignment marks 3 on each chip 2a are formed, for example, as shown in FIG. 9, and in order to avoid misalignment with each other, as shown by arrow P in FIG.
Laser-scan alignment that slides over μm is used.

[0003]

However, when the automatic alignment using the alignment mark of the conventional exposure apparatus is performed, the semiconductor wafer 1
Since the alignment mark is formed on a plurality of chips 2a among the plurality of chips 2 defined above, the region of the plurality of chips 2a is used to form a semiconductor chip. However, there is a problem in that the total yield is reduced because it cannot be used.

In view of the above problems, it is an object of the present invention to provide an exposure apparatus that is provided with an alignment mark without occupying a chip area.

[0005]

According to the present invention, there is provided an exposure apparatus having a photomask and an alignment mark arranged on a semiconductor wafer, wherein at least a pair of alignment marks are provided. , The alignment marks are provided in the vacant areas of the photomask and the chips of the semiconductor wafer, respectively.

In the exposure apparatus according to the present invention, the alignment mark is preferably detected by laser scanning.

In the exposure apparatus according to the present invention, the alignment mark preferably has a size of about 10 μm.

[0008]

According to the above construction, the alignment mark is provided in a vacant area other than the chip body in a plurality of chip areas out of a large number of chip areas arranged side by side on the photomask and the semiconductor wafer. Since the alignment mark does not occupy the chip area on the semiconductor wafer, more chips can be manufactured from one semiconductor wafer, and the manufacturing efficiency can be improved.

When the alignment mark is detected by laser scanning, it can be surely detected even if the alignment mark itself is small.

When the alignment mark has a size of about 10 μm, the area occupied by the mark formed on the surface of the semiconductor wafer can be eliminated to the minimum.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on the embodiments shown in the drawings. FIG. 1 is a plan view showing a chip area provided with an alignment mark according to the present invention, and FIG. 2 is a perspective view showing a schematic configuration of an embodiment of an exposure apparatus according to the present invention.

In FIG. 2, the exposure apparatus 10 is shown focusing on the contact portion between the photomask and the semiconductor wafer, and the semiconductor wafer 12, the photomask 13, and the back plate 14 are sequentially mounted on the wafer table 11. It is supposed to be placed. The laser scan auto-alignment unit and the pattern recognition signal processing unit are omitted.

The wafer table 11 has markings 11a for alignment with the semiconductor wafer 12 on its upper surface.

The photomask 13 is formed by dividing each pattern of a large number of chip areas to be exposed in advance.

On the other hand, the semiconductor wafer 12 is exposed by dividing a pattern into each of the numerous chip areas to be exposed.

Here, in the photomask 13 and the semiconductor wafer 12, among the above-mentioned many chip areas, any chip area, for example, four chip areas shown by A and B in FIG. It is configured as shown in FIG. That is, in FIG. 1, the chip area 20 includes an original chip portion 21 and an empty area 22 around the chip portion.
It consists of and. Then, in the case of the vacant area 22, six alignment marks 23 are formed in advance on the semiconductor wafer 12 in the illustrated case.

On the other hand, the photomask 13 is provided with an alignment mark composed of a light shielding portion 13a (see FIG. 3) on the lower surface thereof in a region facing the alignment mark 23.

As shown in FIG. 4, the alignment mark 23 and the light-shielding portion 13a are first aligned with the alignment mark 23 and the light-shielding portion 13a in the horizontal direction (ie, the x-direction) and the vertical direction (ie, the y-direction). Direction) laser scanning is performed. Thereby, as shown in FIG. 5, the boundary between the alignment mark 23 and the light shielding portion 13a is detected by detecting the reflectance of the laser beam.

Thus, when the alignment is performed, the work is performed according to the flowchart shown in FIG. That is, according to the flowchart of FIG. 6, laser scanning is first performed in the x direction and the y direction. As a result, the data a and b in the x direction and the data c and d in the y direction in FIG. 4 are read.

Here, the data a and b in the x direction and the data c and d in the y direction are compared with each other. If a = b and c = d are not satisfied, (ab) is positive in the x direction. In the + x direction, and if (a-b) is negative, -x.
The semiconductor wafer 12 is moved by driving the wafer table 11 by ((ab) / 2) in the direction. Also, y
Regarding the direction, if (c-d) is positive, the wafer table 11 is moved in the + y direction, and if (c-d) is negative, the wafer stage 11 is moved by ((c-d) / 2). By driving
The semiconductor wafer 12 is moved.

After that, laser scanning in the x and y directions is performed again, and the data a and b in the x direction and the data c and d in the y direction are read. Then, again, the data a and b in the x direction and the data c and d in the y direction are compared with each other.

By repeating the above operation, a = b, c = regarding the read data in the x direction and the y direction.
When d is reached, alignment is completed. Then, the semiconductor wafer 12 and the photomask 13 are locked, exposure is performed, and the pattern provided in the photomask 13 is printed on the semiconductor wafer 12.

Here, the alignment mark 23 of the semiconductor wafer 12 and the light shielding portion 13a of the photomask 13 are appropriately selected in number as shown in FIGS. 7A to 7E, that is, in FIG. In this case, by selecting between 1 and 5, it is possible to use each semiconductor device in order to discriminate each semiconductor device or as a shipping inspection mark when manufacturing a plurality of types of semiconductor devices. .

Further, the alignment mark 23 is
Based on the accuracy of laser scanning, it can be formed to have a size of, for example, about 10 μm. Therefore, it can be easily accommodated in the empty area in each chip area of the semiconductor wafer.

Although the automatic alignment has been described in the above embodiment, the present invention is not limited to this, and similar effects can be obtained in manual alignment.

[0026]

As described above, according to the present invention, among a large number of chip areas arranged side by side in the vertical and horizontal directions of the photomask and the semiconductor wafer, in a plurality of chip areas, there is a space other than the chip body. Since the alignment mark is provided in the area, the alignment mark does not occupy the chip area on the semiconductor wafer, so that more chips can be manufactured from one semiconductor wafer, which improves the manufacturing efficiency. Can be done.

Further, since all the chip areas can be used for chip manufacturing, an error such as a pitch deviation of each chip area does not occur.

When the alignment mark is detected by laser scanning, it can be surely detected even if the alignment mark itself is small.

When the alignment mark has a size of about 10 μm, the alignment mark can be used as a shipping mark, and the mark formed on the surface of the semiconductor wafer can be eliminated to the minimum. Become.

Thus, according to the present invention, the alignment mark is provided without occupying the chip area.
An excellent exposure apparatus can be provided.

[Brief description of drawings]

FIG. 1 is a plan view showing one chip region of a semiconductor wafer in an embodiment of an exposure apparatus of the present invention.

FIG. 2 is a perspective view showing a schematic configuration of an embodiment of the exposure apparatus of the present invention.

3 is a cross-sectional view of the semiconductor wafer of FIG. 1 in the vicinity of an alignment mark.

FIG. 4 is a schematic diagram showing a method for detecting the alignment mark of FIG. 3 by laser scanning.

5 is a graph showing an output signal from a detector by the laser scanning of FIG.

FIG. 6 is a flowchart at the time of automatic alignment and exposure by the exposure apparatus of FIG.

7A to 7C are schematic views showing various examples of forming alignment marks formed in the chip region of FIG.

FIG. 8 is a schematic plan view showing a semiconductor wafer provided with alignment marks in an example of a conventional exposure apparatus.

9 is a schematic diagram showing an example of an alignment mark in FIG.

[Explanation of symbols]

 10 Exposure Device 11 Wafer Stage 11a Positioning Marking 12 Semiconductor Wafer 13 Photomask 13a Light-shielding Part (Alignment Mark) 14 Back Plate 20 Chip Area 21 Chip Part 22 Empty Area 23 Alignment Mark

Claims (3)

[Claims] 1. An exposure apparatus having a photomask and alignment marks arranged on a semiconductor wafer, wherein at least a pair of alignment marks are provided, and each alignment mark is provided on each of the photomask and the semiconductor wafer. An exposure apparatus, which is provided in an empty area of a chip. 2. The exposure apparatus according to claim 1, wherein the alignment mark is detected by laser scanning. 3. The exposure apparatus according to claim 1, wherein the alignment mark has a size of about 10 μm.