JPS60192332A - Semiconductor substrate with positioning mark and method for detection of marked position on substrate - Google Patents

Semiconductor substrate with positioning mark and method for detection of marked position on substrate

Info

Publication number
JPS60192332A
JPS60192332A JP59048409A JP4840984A JPS60192332A JP S60192332 A JPS60192332 A JP S60192332A JP 59048409 A JP59048409 A JP 59048409A JP 4840984 A JP4840984 A JP 4840984A JP S60192332 A JPS60192332 A JP S60192332A
Authority
JP
Japan
Prior art keywords
mark
pattern
reference position
width
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59048409A
Other languages
Japanese (ja)
Inventor
Hiroaki Morimoto
森本 博明
Yaichiro Watakabe
渡壁 弥一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59048409A priority Critical patent/JPS60192332A/en
Publication of JPS60192332A publication Critical patent/JPS60192332A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Electron Beam Exposure (AREA)

Abstract

PURPOSE:To detect the reference position without fail even when the position of a scanning charged beam is shifted as well as to enable to perform a position detection smoothly even when different exposing methods are used in combination by a method wherein a pattern-line- combined positioning mark, having the line width differentiated in proportion to the distance in X-Y axis direction with the reference position as the center point, is provided. CONSTITUTION:A mark 11 is constituted by combining three pattern lines, for example, in X and Y axial directions having a different line width respectively in accordance with the distance between the reference position P and the X-Y axial direction. Pertaining to the width of said pattern lines in the X-axis direction lines, for example, the center pattern line 11a which passes the reference position is formed at 15mum in width, the pattern line 11b located at the lower part parting 70mum from the pattern line 11a, is formed at 10mum in width, the pattern line 11c located at the upper part parting 70mum from the pattern line 11a is formed at 20mum in width, and the lines in Y-axis direction are also formed in the same manner as above. A charged beam 6 is scanned in X and Y axis direction on the positioning mark 11, the width of the pattern lines is detected by the obtained mark signal, and the reference position P of the positioning mark 11 is detected.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、半導体ウェーハなと半導体基板上に位置合
わせマークを施し、このマークの基準位置を荷電ビーム
の走査により検出するようにした、位置合わせマーク付
き半導体基板及びこの基板のマーク位置検出方法に関す
る0 〔従来技術〕 半導体基板の製造工程において、1μm程度又はこれ以
下の非常に微細な回路パターンを必要とする場合や、小
量多品種製品を開発・製造したりする場合に、電子ビー
ム露光やイオンビーム露光などの荷電ビーム露光がしば
しば用いられるようになった。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an alignment method in which an alignment mark is formed on a semiconductor substrate such as a semiconductor wafer, and the reference position of the mark is detected by scanning a charged beam. 0 Regarding semiconductor substrates with marks and methods for detecting mark positions on such substrates [Prior art] In the manufacturing process of semiconductor substrates, there are cases in which very fine circuit patterns of approximately 1 μm or less are required, and in cases where small-scale production of a wide variety of products is required. Charged beam exposure such as electron beam exposure and ion beam exposure has come to be frequently used in development and manufacturing.

このような電荷ビーム露光においては、前工程で形成さ
れた回路パターンに、露光すべき回路パターンを精度よ
く重ね合わせるために、専用の位置合わせマークが用い
られている。
In such charge beam exposure, a dedicated alignment mark is used to precisely overlap the circuit pattern to be exposed with the circuit pattern formed in the previous process.

位置合わせマークを回路パターン中、又は半導体ウェー
ハ(以下「ウェーハ」と称する)中に付しておき、荷電
ビーム露光時にこれらのマーク上を走査し、得られる反
射ビームや二次電子などの信号によりマークの基準位置
をめるようにしている。
Alignment marks are attached to the circuit pattern or to the semiconductor wafer (hereinafter referred to as "wafer"), and these marks are scanned during charged beam exposure, and the reflected beam, secondary electrons, and other signals obtained are used to I try to set the reference position of the mark.

このような、位置合わせマーク付きウェーハを第1図に
平面図で示す。ウェーハ(1)には多数のチップ部(2
)が区分されている。(3)は位置合わせマーク(以下
「マーク」と称する)で、A、B及びCの3箇所に施さ
れている。
Such a wafer with alignment marks is shown in plan view in FIG. The wafer (1) has many chip parts (2
) are classified. (3) are alignment marks (hereinafter referred to as "marks"), which are placed at three locations A, B, and C.

荷電ビーム描画に先立ち、マーク(3)上をA、B。Prior to charged beam writing, move marks A and B over the mark (3).

0の順で走査し、各の座標をめ、露光すべき座標系のX
、Y軸方向の利得と回転を決定する0ウエーハ(1)の
従来のマークは、第2図に拡大図で示すようになってい
た。(4)はマークで、同一の線幅で十字状に形成され
ている。(6)はマーク(4)上を走査している荷電ビ
ームを表わす。Pはマーク(4)の基準位置を示す。
Scan in the order of 0, find each coordinate, and set the X of the coordinate system to be exposed.
, the conventional marks on the 0 wafer (1) that determine the gain and rotation in the Y-axis direction are shown in an enlarged view in FIG. (4) is a mark, which is formed in a cross shape with the same line width. (6) represents a charged beam scanning over mark (4). P indicates the reference position of mark (4).

従来のマークの他の例を第3図に拡大図で示し、マーク
(7)は同一の線幅でL字状に形成されている。
Another example of the conventional mark is shown in an enlarged view in FIG. 3, and the mark (7) is formed in an L-shape with the same line width.

上記従来のマークを付したウェーハ(1)の場合、露光
装置の座標系とウェーハ(1)の座標系が大きくずれて
いると、マーク(4) 、 (71の基準位置Pがめら
れない。これを第4図に示し、走査している荷電ビーム
(6)がマーク(4)から大きく外れ、マーク(4)か
らの反射信号が得られない。また、得られたとしても誤
った信号となり、マーク(4)の基準位置Pをめること
ができない、という問題があった。
In the case of the wafer (1) with the conventional marks described above, if the coordinate system of the exposure apparatus and the coordinate system of the wafer (1) are largely misaligned, the reference position P of the marks (4) and (71) cannot be found. is shown in Fig. 4, the scanning charged beam (6) deviates significantly from the mark (4), and the reflected signal from the mark (4) cannot be obtained.Also, even if it is obtained, it will be an incorrect signal, There was a problem in that the reference position P of the mark (4) could not be set.

この場合、従来は作業者がウェーハ(1)を移動してマ
ーク(4)位置を探す作業が必要であり、自動化を妨げ
る原因となっていだ0 このような問題は、特に、異なる露光装置間、又は異な
る露光方法(例えば電子ビーム露光方法と光露光方法)
間で混用した場合によく生じる0〔発明の概要〕 この発明は、上記従来のものの欠点をなくするためにな
されたもので、基準位置を中心とし、この位置からのX
軸及びY軸方向の距離に応じて線幅を異にした、X軸及
びY軸方向の複数木兄のパターン線を組合わせた位置合
わせマークを半導体基板上に施し、この位置合わせマー
ク上を荷電ビームでX軸及びY軸方向に走査し、得られ
たマーク信号により、パターン線幅を検知し、これによ
り位置合わせマークの基準位置を検出するようKし、位
置合わせマークから走査荷電ビームの位置がずれていて
も、基準位置が確実に検出され、また、異なる露光方法
を組合わせた露光工程であっても、位置検出が支障なく
でき、自動化を可能にしだ、位置合わせマーク付き半導
体基板及びこの基板のマーク位置検出方法を提供するこ
とを目的としている。
In this case, conventionally, the operator had to move the wafer (1) and search for the mark (4) position, which hindered automation. , or different exposure methods (e.g. electron beam exposure method and light exposure method)
[Summary of the Invention] This invention was made to eliminate the drawbacks of the above-mentioned conventional products.
An alignment mark that combines multiple pattern lines in the X-axis and Y-axis directions with different line widths depending on the distance in the axis and Y-axis directions is made on the semiconductor substrate, and the alignment mark is The charged beam is scanned in the X-axis and Y-axis directions, and the pattern line width is detected using the obtained mark signal.The reference position of the alignment mark is detected from this, and the scanned charged beam is scanned from the alignment mark. Semiconductor substrates with alignment marks that can reliably detect the reference position even if the position is misaligned, and enable position detection without any problems even in the exposure process that combines different exposure methods, making automation possible. The present invention also aims to provide a method for detecting a mark position on this substrate.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例を、第5図に示す位置合わせ
マーク部の拡大図により説明する。α→はウェーハ(1
)に施されたマークで、マークの基準位置(この場合中
央点)PからのX軸及びY軸方向の距離に応じ、それぞ
れ線幅が異なるY軸及びX軸方向の3本宛のパターン線
の組合せからなっている。これらの各パターン線の線幅
は、例えば、X軸方向線では、基準位置Pを通る中央の
パターン線(lla)は15μm、この線から下方に7
0μm離れたパターン線(11b)は10μm、パター
ン線(lla)から上一方に70μm離れたパターン線
(llc)は20μmにしている。まだ、Y軸方向線で
は基準位置Pを通る中央のパターン線(lld)は15
μm、この線から左方に70μm離れパターン線(11
θ)は10μm、パターン線(1,1111)から右方
に70μm離れだパターン線(11f)は20μmにし
である。
Hereinafter, one embodiment of the present invention will be described with reference to an enlarged view of the alignment mark portion shown in FIG. α→ is the wafer (1
), which is a pattern line for three lines in the Y-axis and It consists of a combination of The line width of each of these pattern lines is, for example, in the X-axis direction line, the center pattern line (lla) passing through the reference position P is 15 μm, and the line width is 7 μm downward from this line.
The pattern line (11b) which is 0 .mu.m apart is 10 .mu.m, and the pattern line (llc) which is 70 .mu.m away from the pattern line (lla) on the upper side is 20 .mu.m. Still, in the Y-axis direction line, the center pattern line (lld) passing through the reference position P is 15
μm, pattern line (11
θ) is 10 μm, the pattern line (11f) is 70 μm to the right from the pattern line (1, 1111), and the pattern line (11f) is 20 μm apart.

このようなマーク01)を用いたウェーハ(1)の座標
系と、露光装置の座標系が大きくずれている場合の、位
置検出方法を説明する○まず、X方向及びY方向に数回
の電荷ビーム(6)による走査を、走査幅60μmで行
う0マ一ク信号が得られなければ、10μm走査位置を
ずらして再びマーク走査を行う0この操作を繰返してい
くと、第5図に示すように、マークαη上を走査してマ
ーク信号が得られる。
We will explain the position detection method when the coordinate system of the wafer (1) using such mark 01) and the coordinate system of the exposure device are largely misaligned. Scanning with the beam (6) is performed with a scanning width of 60 μm. If no mark signal is obtained, shift the scanning position by 10 μm and scan the mark again. By repeating this operation, as shown in Figure 5, Then, a mark signal is obtained by scanning the mark αη.

このように少しでもマークα→に走査がかかると、この
マーク信号から、電子計算機により走査したマーク01
)のパターン線幅がわかる。図の例では、X方向が20
μm、Y方向が20μmであることがわかる0この値か
ら、電子計算機により今の走査でまる座標は、基準位置
PからX方向、Y方向とも+70μmの位置であること
がわかり、マークaηの基準位置Pの検出ができ、ウェ
ーハ(1)位置の自動修正が行える。
In this way, if the mark α→ is scanned even slightly, from this mark signal, the mark 01 scanned by the electronic computer
) pattern line width. In the example shown, the X direction is 20
μm, Y direction is 20 μm 0 From this value, it can be seen that the coordinates determined by the current scan by the electronic computer are +70 μm in both the X direction and Y direction from the reference position P, and the reference point of the mark aη The position P can be detected and the wafer (1) position can be automatically corrected.

このように、形成したマークαηにより、露光装置の座
標系がずれていても、位置検出が支障なく行え、自動化
ができる。
In this way, even if the coordinate system of the exposure apparatus is shifted by the formed mark αη, position detection can be performed without any problem and automation can be achieved.

なお、上記実施例では、Y軸及びX軸方向3木宛のパタ
ーン線によるマーク0ηを用い、その大きさは160μ
m X 160μmの場合を示したが、形状はこれに限
らず、まだ、大きさは実際に起こりうる最大のずれと同
程度の大きさのマークを用いるようにする。
In the above example, a mark 0η made of pattern lines for three trees in the Y-axis and X-axis directions is used, and its size is 160μ.
Although the case of m x 160 μm is shown, the shape is not limited to this, and it is preferable to use a mark having a size similar to the maximum deviation that can actually occur.

〔発明の効果〕〔Effect of the invention〕

以上のように1この発明によれば、マークの基準位置を
中心とし、この点からのX軸及びY軸方向の距離に応じ
て線幅を異にした、Y軸及びX軸方向の複数木兄のパタ
ーン線を組合わせてなる位置合わせマークを半導体基板
上に施し、この位置合わせマーク上を荷電ビームでX軸
及びY軸方向に走査し、得られたマーク信号により、そ
のパターン線幅を検知し、位置合わせマークの基準位置
を検出するようにし、位置合わせマークから走査荷電ビ
ームの位置がずれていても、基準位置が確実に検出でき
、半導体基板の露光が行なえる。また、異なる露光方法
を組合わせた工程であっても、位置検出が支障なくでき
、自動化することが可能になる。
As described above, (1) according to the present invention, multiple trees in the Y-axis and An alignment mark made by combining the older brother's pattern lines is made on a semiconductor substrate, and a charged beam is scanned over this alignment mark in the X-axis and Y-axis directions, and the pattern line width is determined by the mark signal obtained. The reference position of the alignment mark is detected, and even if the position of the scanning charged beam deviates from the alignment mark, the reference position can be reliably detected and the semiconductor substrate can be exposed. Further, even in a process that combines different exposure methods, position detection can be performed without any problem and automation can be achieved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は位置合わせマークを施した半導体ウェーハの平
面図、第2図及び第3図は従来の位置合わせマークの各
側を示す拡大平面図、第4図は第2図の位置合わせマ゛
−りをずれた位置でビーム走査している状態を示す平面
図、第5図はこの発明の一実施例を示す半導体ウェーハ
の位置合わせマーク部の拡大平面図である。 1・・・半導体ウェーハ、6・・・走査荷電ビーム、1
1・・・位置合わせマーク、11a〜llf・・・パタ
ーン線なお、図中同一符号は同−又は相当部分を示す。 代理人 大岩増雄 第1図 第2図 第3図
FIG. 1 is a plan view of a semiconductor wafer with alignment marks, FIGS. 2 and 3 are enlarged plan views showing each side of conventional alignment marks, and FIG. 4 is a plan view of a semiconductor wafer with alignment marks. FIG. 5 is an enlarged plan view of an alignment mark portion of a semiconductor wafer showing an embodiment of the present invention. 1... Semiconductor wafer, 6... Scanning charged beam, 1
1... Alignment mark, 11a-llf... Pattern line Note that the same reference numerals in the drawings indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】 (1) マークの基準位置を中心とし、この位置からの
X軸及びY軸方向の距離に応じてそれぞれ異なる線幅に
した、Y軸及びX軸方向の複数木兄のパターン線を組合
わせてなる位置合わせマークが施された半導体基板。 (2)位置合わせマークは印字状をなすことを特徴とす
る特許請求の範囲第1項記載の半導体基板0(3)半導
体基板に、マークの基準位置を中心とし、との位置から
のX軸及びY軸方向の距離に応、じてそれぞれ異なる線
幅にした、Y軸及びX軸方向の複数木兄のパターン線を
組合わせてなる位置合わせマークを半導体基板に施し、
この位置合わせマーク上に荷電ビームをX軸及びY軸方
向匠走査し、得られたマーク信号により、走査したY軸
及びX軸方向の上記パターン線の線幅を検知し、これら
の線幅値から上記位置合わせマークの基準位置を検出す
るようにする、基板のマーク位置検出方法。 (4)位置合わせマークは印字状をなすことを特徴とす
る特許請求の範囲第3項記載の基板のマーク位置検出方
法。
[Claims] (1) A plurality of lines in the Y-axis and A semiconductor substrate with alignment marks made from a combination of pattern lines. (2) The semiconductor substrate according to claim 1, wherein the alignment mark is in the form of a print. and a positioning mark formed by combining multiple pattern lines in the Y- and X-axis directions, each having a different line width depending on the distance in the Y-axis direction, is applied to the semiconductor substrate,
A charged beam is scanned over this alignment mark in the X-axis and Y-axis directions, and the line widths of the scanned pattern lines in the Y-axis and X-axis directions are detected using the obtained mark signals, and these line width values are detected. A method for detecting a mark position on a board, wherein a reference position of the alignment mark is detected from the reference position of the alignment mark. (4) The method for detecting the position of a mark on a substrate according to claim 3, wherein the alignment mark is in the form of a print.
JP59048409A 1984-03-12 1984-03-12 Semiconductor substrate with positioning mark and method for detection of marked position on substrate Pending JPS60192332A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59048409A JPS60192332A (en) 1984-03-12 1984-03-12 Semiconductor substrate with positioning mark and method for detection of marked position on substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59048409A JPS60192332A (en) 1984-03-12 1984-03-12 Semiconductor substrate with positioning mark and method for detection of marked position on substrate

Publications (1)

Publication Number Publication Date
JPS60192332A true JPS60192332A (en) 1985-09-30

Family

ID=12802502

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59048409A Pending JPS60192332A (en) 1984-03-12 1984-03-12 Semiconductor substrate with positioning mark and method for detection of marked position on substrate

Country Status (1)

Country Link
JP (1) JPS60192332A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6657203B2 (en) 1999-12-28 2003-12-02 Kabushiki Kaisha Toshiba Misalignment inspection method, charge beam exposure method, and substrate for pattern observation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6657203B2 (en) 1999-12-28 2003-12-02 Kabushiki Kaisha Toshiba Misalignment inspection method, charge beam exposure method, and substrate for pattern observation

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