JPH02185024A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH02185024A
JPH02185024A JP556789A JP556789A JPH02185024A JP H02185024 A JPH02185024 A JP H02185024A JP 556789 A JP556789 A JP 556789A JP 556789 A JP556789 A JP 556789A JP H02185024 A JPH02185024 A JP H02185024A
Authority
JP
Japan
Prior art keywords
conductive layer
opening
wiring
aluminum
opening section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP556789A
Other languages
Japanese (ja)
Other versions
JP2701239B2 (en
Inventor
Noriyuki Shimoji
規之 下地
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP1005567A priority Critical patent/JP2701239B2/en
Publication of JPH02185024A publication Critical patent/JPH02185024A/en
Application granted granted Critical
Publication of JP2701239B2 publication Critical patent/JP2701239B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To apply a conductive layer for a wiring positively along a taper, and to ensure coverage sufficiently by evaporating the conductive layer for the wiring onto the side face of an opening section under the state in which a tapered conductive layer is left. CONSTITUTION:The surface of a phosphate glass layer 8 is coated with a photo- resist 10, and the pattern of a contact hole is formed. The phosphate glass layer 8 and an SiO2 film 6 are etched while using the photo-resist 10 as a mask, and an opening section 9 is shaped. A conductive layer 12 is anisotropic-etching through RIE, and the conductive layer 12 is left only on the sidewall section of the opening section 9. Aluminum is evaporated again, and a conductive layer 14 for a wiring is shaped onto aluminum. The side face of the opening section 9 is formed to a tapered shape by the conductive layer 12 in the opening section 9 at that time. Accordingly, aluminum is applied positively and continuously, thus ensuring sufficient coverage.

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は半導体装置の製造方法、特にその配線用導電
層の形成に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to the formation of a conductive layer for wiring therein.

[従来の技術] 半導体装置の製造過程において、半導体基板に形成され
ているベース、エミッタ等の導電領域に配線を施す工程
がある。この工程は、半導体基板の表面上の絶縁層にコ
ンタクト・パターニングをすることによって行われてい
る。まず、前記絶縁膜の表面にフォトレジストを使って
配線パターンを形成し、次にこのフォトレジストをマス
クにして導電型領域内の絶縁層をエツチングして開口す
る。その後、アルミニウムのような配線用導電層を蒸着
した後、不要な部分を除去する。
[Background Art] In the manufacturing process of a semiconductor device, there is a step of wiring conductive regions such as a base and an emitter formed on a semiconductor substrate. This process is performed by contact patterning an insulating layer on the surface of a semiconductor substrate. First, a wiring pattern is formed on the surface of the insulating film using a photoresist, and then, using the photoresist as a mask, the insulating layer in the conductivity type region is etched to form an opening. After that, a conductive layer for wiring such as aluminum is deposited, and then unnecessary portions are removed.

開口部形成のための、絶縁層のエツチングとしては、一
般に、等方性エツチングが用いられている。ウェット・
テーパー・エツチングのような等方性エツチングによる
と、絶縁層の開口部の肩部分がややだれ気味になって、
テーパー状となる。
Isotropic etching is generally used for etching the insulating layer to form openings. wet
When using isotropic etching such as taper etching, the shoulder portion of the opening in the insulating layer becomes slightly sagging.
It becomes tapered.

したがって、アルミニウム層を蒸着する際に、なだらか
になった肩部分に沿って、アルミニウム層が円滑に被着
され、アルミニウム層の途絶がない。
Therefore, when depositing the aluminum layer, the aluminum layer is deposited smoothly along the gentle shoulder portion, and there is no discontinuity in the aluminum layer.

、すなわち、十分な、アルミニウムのカバレジが得られ
る。
That is, sufficient aluminum coverage is obtained.

また、熱処理を行って、開口部の肩部分を滑らかにする
コンタクトリフローを行う場合もある。
Contact reflow may also be performed to smooth the shoulder portion of the opening by heat treatment.

[発明が解決しようとする課題] しかしながら、上記のような等方性エツチングによる場
合には、開口部の肩が滑らかに落とされているので、開
口部の占める面積が太き(なってしまう。そのため、1
μm程度の微細コンタクトの形成が困難となったりして
、集積密度が向上しないという問題があった。
[Problems to be Solved by the Invention] However, in the case of isotropic etching as described above, since the shoulder of the opening is smoothly dropped, the area occupied by the opening becomes large. Therefore, 1
There is a problem in that it is difficult to form fine contacts on the order of micrometers, and the integration density cannot be improved.

また、コンタクトリフローを行った場合には、熱処理に
よって、絶縁層へ燐がオートドープされるという問題を
生じていた。
Furthermore, when contact reflow is performed, there is a problem that phosphorus is auto-doped into the insulating layer due to heat treatment.

上記のような問題を解決するため、反応性イオンを用い
る異方性エツチングを採用することも考えられる。この
方法によれば、開口部の肩がだれることがないので、開
口部分を小さくすることができる。しかし、アルミニウ
ムの蒸着時に、蒸着粒子が、開口部の内部に被着しにく
くなってしまう。すなわち、アルミニウムのカバレジが
確保できなくなってしまい、場合によっては、アルミニ
ウムが開口の内部において連続しないという問題を生じ
る。
In order to solve the above problems, it is also possible to employ anisotropic etching using reactive ions. According to this method, the shoulder of the opening does not sag, so the opening can be made smaller. However, during vapor deposition of aluminum, it becomes difficult for vapor deposition particles to adhere to the inside of the opening. That is, coverage of the aluminum cannot be ensured, and in some cases, a problem arises in that the aluminum is not continuous inside the opening.

この発明は、上記のような問題点を解決して、配線用導
電層のカバレジを確保しつつ、開口部を小さく形成する
ことのできる製造方法を提供することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a manufacturing method capable of solving the above-mentioned problems and forming a small opening while ensuring coverage of a conductive layer for wiring.

[課題を解決するための手段] この発明に係る半導体装置の製造方法は、半導体基板表
面の絶縁膜に、異方性エツチングによって開口部を形成
する工程、 開口部および絶縁膜上に、蒸着によって導電層を形成す
る工程、 異方性エツチングを行い、開口部側壁付近のみに導電層
を残す工程、 開口部および絶縁膜上に、蒸着によって配線用導電層を
形成する工程、 を備えている。
[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes a step of forming an opening in an insulating film on a surface of a semiconductor substrate by anisotropic etching, and forming an opening on the opening and the insulating film by vapor deposition. The method includes a step of forming a conductive layer, a step of performing anisotropic etching to leave the conductive layer only near the side walls of the opening, and a step of forming a conductive layer for wiring by vapor deposition on the opening and the insulating film.

[作用] この発明では、開口部の側面にテーパー状の導電層が残
された状態で配線用導電層を蒸着するようにしている。
[Function] In the present invention, the wiring conductive layer is deposited with a tapered conductive layer left on the side surface of the opening.

したがって、配線用導電層が、このテーパーに沿って確
実に被着される。
Therefore, the wiring conductive layer is reliably deposited along this taper.

また、異方性エツチングを用いているので、開口部の面
積を小さく抑えることができる。
Furthermore, since anisotropic etching is used, the area of the opening can be kept small.

さらに、熱処理を行っていないので、オートドープ等が
生じない。
Furthermore, since no heat treatment is performed, autodoping and the like do not occur.

[実施例] この発明の一実施例による半導体装置の製造方法を第1
図A、B、C,Dに示す。ここでは、半導体基板2の表
面に、導電領域(ソース、ドレイン等)4が形成されて
おり、それらの上部に、絶縁膜であるSiO□膜6、燐
ガラス層8が形成されているものとする。この導電領域
4に配線を施すものとして説明する。
[Example] A method for manufacturing a semiconductor device according to an example of the present invention is described in a first embodiment.
Shown in Figures A, B, C, and D. Here, a conductive region (source, drain, etc.) 4 is formed on the surface of a semiconductor substrate 2, and an SiO□ film 6, which is an insulating film, and a phosphor glass layer 8 are formed on top of these. do. A description will be given assuming that wiring is provided in this conductive region 4.

まず、燐ガラス層8の表面に、フォトレジストlOを塗
布して、コンタクトホールのパターンを形成する。次に
、第1図Aに示すように、このフォトレジストlOをマ
スクにして、燐ガラス層8.5iO8膜6のエツチング
を行い、開口部6を形成する。
First, a photoresist lO is applied to the surface of the phosphor glass layer 8 to form a contact hole pattern. Next, as shown in FIG. 1A, the phosphor glass layer 8.5iO8 film 6 is etched using this photoresist lO as a mask to form an opening 6.

このエツチングは、異方性エツチングにより行う。This etching is performed by anisotropic etching.

フォトレジストlOを除去した後、アルミニウムを蒸着
して、導電層12を形成する。この状態を示したのが第
1図Bである。この導電層12の厚さとしては、1μm
程度である。
After removing the photoresist IO, aluminum is deposited to form a conductive layer 12. FIG. 1B shows this state. The thickness of this conductive layer 12 is 1 μm.
That's about it.

次に、導電層12をRIHによって異方性エツチングを
行う。これにより、第1図Cに示すように、開口部9の
側壁部の4みに、導電層12を残留させる。
Next, the conductive layer 12 is anisotropically etched by RIH. As a result, as shown in FIG. 1C, the conductive layer 12 is left only on the sidewall portion 4 of the opening 9.

この後、再び、アルミニウムを蒸着して、配線用導電層
14をその上に形成する(第1図り参照)。
Thereafter, aluminum is deposited again to form a wiring conductive layer 14 thereon (see first diagram).

この時、開口部9内では、その側面が導電層12によっ
てテーパー状となっているので、アルミニウムが確実に
連続して被着し、十分なカバレジが確保できる。
At this time, since the side surfaces of the opening 9 are tapered by the conductive layer 12, the aluminum can be deposited continuously and ensure sufficient coverage.

なお、上記実施例では配線用導電層14としてアルミニ
ウムを用いたが、その他の導電性金属を用いてもよい。
In addition, although aluminum was used as the wiring conductive layer 14 in the above embodiment, other conductive metals may be used.

[発明の効果] この発明に係る半導体装置の製造方法では、開口部側面
にテーパー状の導電層が残された状態で配線用導電層を
蒸着するようにしている。したがって、このテーパーに
沿って配線用導電層が確実に被着され、カバレジが十分
に確保される。
[Effects of the Invention] In the method for manufacturing a semiconductor device according to the present invention, a conductive layer for wiring is deposited with a tapered conductive layer left on the side surface of the opening. Therefore, the conductive layer for wiring is reliably deposited along this taper, and sufficient coverage is ensured.

また、開口形成および開口部側壁への導電層残留を異方
性エツチングによって行うので、開口部の面積を小さく
抑えることができ、1μm程度の微細コンタクトも形成
可能となる。
Further, since the opening is formed and the conductive layer remains on the side wall of the opening by anisotropic etching, the area of the opening can be kept small, and fine contacts of about 1 μm can be formed.

さらに、熱処理を行っていないので、オートドープ等の
問題を生じることがない。
Furthermore, since no heat treatment is performed, problems such as autodoping do not occur.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図AないしDは、この発明の一実施例による半導体
装置の製造工程を示す断面図である。 2・・・半導体基板 6・・・5in2膜 8・・・燐ガラス層 9・・・開口部 10・・・フォトレジスト 12・・・導電層 14・・・配線用導電層
FIGS. 1A to 1D are cross-sectional views showing the manufacturing process of a semiconductor device according to an embodiment of the present invention. 2... Semiconductor substrate 6... 5in2 film 8... Phosphorus glass layer 9... Opening 10... Photoresist 12... Conductive layer 14... Conductive layer for wiring

Claims (1)

【特許請求の範囲】[Claims] (1)半導体基板表面の絶縁膜に、異方性エッチングに
よって開口部を形成する工程、 開口部および絶縁膜上に、蒸着によって導電層を形成す
る工程、 異方性エッチングを行い、開口部側壁付近のみに導電層
を残す工程、 開口部および絶縁膜上に、蒸着によって配線用導電層を
形成する工程、 を備えたことを特徴とする半導体装置の製造方法。
(1) A step of forming an opening in an insulating film on the surface of a semiconductor substrate by anisotropic etching. A step of forming a conductive layer by vapor deposition on the opening and the insulating film. Performing anisotropic etching and forming an opening on the side walls of the opening. A method for manufacturing a semiconductor device, comprising: a step of leaving a conductive layer only in the vicinity; and a step of forming a conductive layer for wiring by vapor deposition over the opening and the insulating film.
JP1005567A 1989-01-11 1989-01-11 Method for manufacturing semiconductor device Expired - Fee Related JP2701239B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1005567A JP2701239B2 (en) 1989-01-11 1989-01-11 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1005567A JP2701239B2 (en) 1989-01-11 1989-01-11 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH02185024A true JPH02185024A (en) 1990-07-19
JP2701239B2 JP2701239B2 (en) 1998-01-21

Family

ID=11614790

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1005567A Expired - Fee Related JP2701239B2 (en) 1989-01-11 1989-01-11 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2701239B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0552968A2 (en) * 1992-01-23 1993-07-28 Samsung Electronics Co. Ltd. Semiconductor device including a wiring layer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5893255A (en) * 1981-11-30 1983-06-02 Toshiba Corp Manufacture of semiconductor device
JPS60224218A (en) * 1984-04-20 1985-11-08 Toshiba Corp Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5893255A (en) * 1981-11-30 1983-06-02 Toshiba Corp Manufacture of semiconductor device
JPS60224218A (en) * 1984-04-20 1985-11-08 Toshiba Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0552968A2 (en) * 1992-01-23 1993-07-28 Samsung Electronics Co. Ltd. Semiconductor device including a wiring layer

Also Published As

Publication number Publication date
JP2701239B2 (en) 1998-01-21

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