JPH02183623A - Sample and hold circuit - Google Patents

Abstract

PURPOSE:To reduce the cost and to make the circuit small in size by using one A/D converter so as to allow the circuit to cope with plural analog signals. CONSTITUTION:When analog switches S11, S12 are switched sequentially while being synchronously with each other, corresponding analog signals A11-A1n are sampled and held in plural sampling circuits B11-B1n. Then when the analog switch S13 is switched to connect the circuit B11 and a storage means 13, for example, then a sampling charge stored in the circuit B11 is stored in the storage means 13, the stored charge is converted into a digital value by the A/D converter 14 and outputted. That is, in the case of converting digitally plural charges stored in the sampling circuits B11-B1n, one A/D converter 14 is enough for the purpose. Thus, the cost is reduced and the circuit is made small in size.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sample and hold circuit, and particularly to a sample and hold circuit that sequentially samples a plurality of analog signals.

Generally, the most commonly used method for converting analog signals into digital signals is the double integration method, and sample-and-hold circuits are widely used. Incidentally, as the number of analog signals increases, the number of signal lines also increases, which is undesirable in terms of circuit scale. Therefore, in order to simplify the transmission system, a plurality of analog signals are transmitted through one signal line.

[Conventional technology]

FIG. 4 is a diagram showing an example of a conventional sample and hold circuit. In the figure, L1 to L are input signal lines that transmit multiple analog signals A and -A, Sl is an analog switch that sequentially selects A1 to A7, 1 is a signal line, and S2 is an input signal line that transmits analog signals on the signal line. An analog switch that sequentially switches and outputs the analog signal from S2 is held in each of the sampling circuits 81 to Bfi,
A/ connected to the output side of sampling circuits B, -B,
The signals are digitally converted by D converters C1 to C and output.

Therefore, according to this configuration, a plurality of analog signals can be transmitted through one signal line l, so that the transmission system can be simplified.

[Problem to be solved by the invention]

However, such a conventional sample-and-hold circuit requires a sampling circuit and an A/D conversion circuit for each of a plurality of analog signals.

That is, since the number of sampling circuits and A/D conversion circuits is equal to the number of analog signals, there are problems in terms of cost and circuit scale.

Therefore, the present invention solves the problem that the main cause of the above problem is the number of A/D converters, since the price of A/D converters is generally high, the number of parts constituting the circuit is large, and the circuit area is large. By focusing on one thing and making it possible to handle multiple analog signals with one A/D converter,
The aim is to reduce costs and miniaturize the circuit.

[Means to solve the problem]

In order to achieve the above object, the sample hold circuit according to the present invention sequentially selects a plurality of analog signals and transmits them through one signal line, and transmits the selected analog signals to one of the plurality of sampling circuits paired with the analog signals. The sample and hold circuit for holding includes an analog switch for selectively taking out charges held in each of the plurality of sampling circuits, one storage means for storing charges taken out by the analog switch, and storage means for storing charges in the storage means. The device includes an A/D converter that converts the generated charges into digital values.

[Effect]

In the present invention, charges held in each of a plurality of sampling circuits are selectively taken out by analog switches, stored in storage means, and then digitally converted by one A/D converter.

Therefore, the number of A/D converters, which is particularly problematic in terms of circuit scale and cost, can be reduced to one regardless of the number of analog signals.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

1 to 3 are diagrams showing one embodiment of a sample and hold circuit according to the present invention.

First, the configuration will be explained. FIG. 1 is a diagram showing the principle configuration of one embodiment. In this figure, L, to L I+1 are input signal lines that transmit a plurality of analog signals A11 to A I m, S,
are A11 to A3. , 11 is a signal line, SI□ is an analog switch that sequentially switches and outputs analog signals on the signal line, and this analog switch SI□ and the analog switch S,
can be switched synchronously. Also, Bll~B+,,
are sampling circuits having the same number as the number of analog signals and in a pairwise relationship, and each of the sampling circuits Bll to BIn has a capacitor Ca and an operational amplifier OPa, and constitutes an accumulation circuit. That is, according to the above configuration,
A plurality of analog signals A + l''A +. are sequentially selected and transmitted through one signal input 11, and A, ~ A l n
A plurality of sampling circuits B, ~B I in a pair relationship with
This provides a function to hold n to n.

On the other hand, S13 is the analog switch described in the gist of the present invention, and this analog switch S13 selectively takes out the charge held in each of the sampling circuits B and ~Blfi, and the taken out charge is transferred to the capacitor c.
b and an operational amplifier OPb are stored in a storage means 13 that constitutes a storage circuit, and the stored charges are converted into a digital value by one A/D converter 14 and output.

In the above configuration, when the analog switch S11 and the analog switch S1□ are synchronized and sequentially switched, the corresponding analog signals A11 to AH, respectively, are sampled and held in the plurality of sampling circuits Bll to B1. Ru. Then, when the analog switch SI3 is switched to connect, for example, 811 and the storage means 13,
The sampling charge held in B11 is accumulated in the accumulation means 13, and this accumulated charge is converted into a digital value by the A/D converter 14 and output.

That is, sampling circuits B, ~B1. ．． When converting a plurality of charges held in a digital signal into digital data, this can be performed by one A/D converter 14. Therefore, cost reduction and circuit miniaturization can be achieved.

FIG. 2 is a diagram specifically showing the principle configuration diagram of FIG. 1. In FIG. 2, the same parts as in FIG. 1 are given the same numbers.

In FIG. 2, 20. ~20. ．． ．． 301-30. ,
and 40. -40 are switches each consisting of an FET and a diode, and switches 201-20. l constitutes an analog switch S, and switch 30.l constitutes an analog switch S. ~30. l constitutes an analog switch S1□, and switch 40.l constitutes an analog switch S1□. ~4
0° constitutes an analog switch SI3. 50 is a pulse generation circuit, and the pulse generation circuit 50 generates an internal clock signal CKI synchronized with an external clock signal CK. Coils 51 to 56 have the same delay amount (Td), and the coils 51 to 56 and the delay circuit 57 produce delayed clock signals DCK, -DCK3, DcK41 to DCK, as shown in the timing chart of FIG. is generated. In FIG. 3, DCK, ~DCK, are signals sequentially delayed by the delay lTd of the coils 51-56, and DCK41-DCK4fi are sequentially delayed by a delay amount Td' that is slightly smaller than the above-mentioned Td. This is a signal. Again in FIG. 2, the delay circuit 57 outputs the signal CKAD for driving the A/D converter 14 to the A/D converter 14 via the coil 58, and the A/D converter 14 outputs the signal CKAD for driving the A/D converter 14. The digital conversion process is executed at an appropriate timing according to the following.

In such a configuration, each of analog switch S and analog switch S1□ has CK +
, D CK l” D CK 3 has been added,
Therefore, the analog switch S and the analog switch S1□ are switched synchronously.

On the other hand, DCK 41 to DCK an delayed by Td' from CK, , DCK, to DCK3 are added to each switch of the analog switch Sll, for example, the switch 30 of the analog switch S1□. When is on, His Highness's switch 40:l of the analog switch S13 is on. Therefore, while charge is being accumulated in a sampling circuit in a given stage, a parallel operation can be performed in which charge is taken out from a sampling circuit in a lower stage.
The digital conversion operation by the converter 14 can be performed in parallel. Also, one A/D converter 14 is provided. It is possible to convert the analog signals A, ~AI, . . . of one loss into digital values and output them. That is, regardless of the number of analog signals, the number of A/D converters 14 can be reduced to one, and the cost can be reduced and the circuit can be made smaller.

〔Effect of the invention〕

According to the present invention, it is possible to digitally convert a plurality of analog signals with one A/D converter, and it is possible to reduce costs and miniaturize the circuit.

[Brief explanation of the drawing]

1 to 3 are diagrams showing one embodiment of the sample and hold circuit according to the present invention. FIG. 1 is a diagram of its principle configuration, FIG. This is a timing chart. FIG. 4 is a block diagram of a conventional sample and hold circuit. A, ~A1. ．． ...Analog signal, B, ~B
Ill...Sampling circuit, Sl:l...
... Analog switch, 11 ... Signal line, 13 ... Storage means, 14 ... A/D converter.

Claims (1)

[Scope of Claims] A sample and hold circuit that sequentially selects a plurality of analog signals, transmits them through one signal line, and holds them in one of a plurality of sampling circuits in a paired relationship with the analog signals, comprising: An analog switch that selectively takes out the charge held in each of the sampling circuits, one storage means that stores the charge taken out by the analog switch, and one that converts the charge stored in the storage means into a digital value. A sample hold circuit comprising: an A/D converter;