JPH08340256A - Microcomputer - Google Patents

Abstract

PURPOSE: To reduce the load of a microcomputer to software by sampling and holding an analog signal in accordance with sample-and-hold(S/H) time sent from an AD control means. CONSTITUTION: Plural sensors 18a, 18b,... such as temperature sensors for sending analog signals are connected to plural analog signal input terminals 17a, 17b,.... An AD control means 13 prepares and sends S/H time for sampling and holding each analog signal and an S/H means 15 samples and holds the analog signal in accordance with the S/H time sent from the means 13. Since the S/H time is prepared by the means 13, the means 13 acts so as to reduce the load of the microcomputer to software at the time of A/D conversion and shorten redundant time based upon software control.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a microcomputer having an A / D converter.

[0002]

2. Description of the Related Art In a microcomputer having a plurality of analog signal input terminals, an analog signal output from a sensor such as a temperature sensor is supplied to the analog signal input terminal, and the supplied analog signal is sampled and digitalized. It is provided with an A / D converter for converting into a signal. An approximate equivalent circuit of the sampling circuit for sampling the analog signal has the configuration shown in FIG. Note that FIG. 6 shows the configuration of a sampling circuit for one analog signal input terminal. On the external side of the microcomputer, the sensor 1 having an output impedance of Rs is connected to the analog signal input terminal 2, and on the internal side of the microcomputer, the analog signal input terminal 2 is a multiplexer configuring the sampling circuit. 3 and sample hold circuit 4
Is connected. The multiplexer 3 connected to the analog signal input terminal 2 includes an analog switch SW2. An analog switch SW is provided on the output side of the multiplexer 3.
1, a capacitor 5 for storing an analog value, and a sample hold circuit 4 including a buffer amplifier 6 connected to an A / D converter are connected. It should be noted that the analog switch SW1 has an on-resistance having a constant value of Rsh and the analog switch SW2 has an on-resistance having a constant value of Rmx. On the other hand, the output impedance value Rs of the sensor 1 differs depending on each sensor 1.

[0003]

Since the equivalent circuit shown in FIG. 6 is a CR integrator circuit, the capacitance 5 when the switch SW1 and SW2 are turned on when the terminal voltage of the capacitance 5 is 0V.
The terminal voltage VO and the output voltage Vs of the sensor 1 have the following relationship.

[0004]

[Equation 1]

Therefore, the terminal voltage VO of the capacitor 5 is a function of time (t), and as shown in FIG. 7, the terminal voltage VO exponentially approaches the output voltage Vs of the sensor 1. Further, the waveform of the terminal voltage VO has a gradual rise or a sharp rise according to the magnitude of the output impedance value Rs of the sensor 1. In FIG. 7, it can be seen that the time for the output voltage Vs of the sensor 1 to reach a certain output voltage Vs ′ of the sensor 1 is short when the value Rs of the output impedance is small, and long when the value Rs is large. Therefore, in a microcomputer having a plurality of analog signal input terminals, in order to digitize an analog signal at the time of sampling without error, in consideration of the output impedance of each sensor 1, the A / D of the external input signal is considered. The time until the converted value stabilizes, that is, the on-time of the analog switch for sampling and holding the output signal of the sensor 1 must be determined for each sensor 1.
Therefore, there is a problem that the load on the software of the microcomputer becomes large and the redundancy time under the software control becomes large. The present invention has been made to solve such a problem, and even when a sensor having different output impedance values is connected to an analog input terminal of a microcomputer and various analog signals are supplied from the sensor. An object of the present invention is to provide a microcomputer capable of reducing the load on the software of the microcomputer in the A / D conversion of the analog signal and reducing the redundancy time by software control.

[0006]

SUMMARY OF THE INVENTION The present invention is directed to an analog signal input terminal to which an analog signal is supplied, sample and hold means electrically connected to the analog input terminal to sample and hold the analog signal, and the sample. A microcomputer comprising: an A / D conversion unit that is electrically connected to a holding unit and that converts the sampled and held analog signal into a digital signal. The microcomputer holds the analog signal in the sample and hold unit. Is provided with AD control means, and the sample hold means performs sample hold of the analog signal based on the sample hold time supplied from the AD control means.

The present invention also includes a plurality of analog signal input terminals to which respective analog signals are supplied,
Sample and hold means for sampling and holding the analog signal supplied through the analog signal input terminal, and A for digitally converting the sample and hold analog signal connected to the sample and hold means.
A D / D conversion means, the input side of which is connected to the plurality of analog signal input terminals and the output side of which is connected to the sample hold means, and which outputs one of the analog signals to be sent to the sample hold means. Selecting means for selecting, sample and hold time creating means for creating sample and hold times corresponding to the analog signals selected by the selecting means and supplied to the sample and hold means, and the sample and hold from the selecting means Selection signal transmitting means for transmitting a selection signal for selecting the one analog signal to be transmitted to the means, the sample hold time generating means supplies the respective sample hold times, and the selection signal transmitting means supplies the sample hold times. A selection signal is supplied and based on the selection signal the above Select one from respective sample hold time, characterized by comprising: a sample-and-hold time sending means for sending to said sample hold means as the time for sampling and holding the analog signal.

[0008]

The AD control means creates and sends the sample hold time for sample-holding the analog signal, and the sample hold means performs the sample hold of the analog signal according to the sample hold time sent by the AD control means. Therefore, since the sample hold time is created by the AD control means, the AD control means acts to reduce the load on the software of the microcomputer at the time of A / D conversion of the analog signal.
It also acts to reduce the redundancy time under software control.

When a plurality of analog signals are supplied, the selecting means selects one analog signal to be sent to the sample and hold means based on the selection signal sent by the selection signal sending means. The sample hold time creating means creates a sample hold time corresponding to each analog signal. In order to send the sample hold time corresponding to the analog signal sent to the sample hold means to the sample hold means, the sample hold time sending means selects from among the plurality of sample hold times created by the sample hold creating means. Based on the selection signal, the corresponding sample hold time is selected and sent to the sample hold means. As described above, the selection signal sending means, the sample hold time creating means, and the sample hold time sending means sample the sample hold time corresponding to each analog signal even when the analog signals having different sample hold times are supplied. Since it acts to send to the holding means, it acts to reduce the load on the software of the microcomputer and also to reduce the redundancy time under software control.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A microcomputer which is an embodiment of the present invention will be described below with reference to the drawings. Further, in each figure, the same components are designated by the same reference numerals. As an example of executing the same function as the selecting means, a multiplexer is used in the present embodiment, and as an example of executing the same function as the sample hold time creating means, in the present embodiment, the frequency dividing circuit and the sample clock switching circuit of each channel are used. In this embodiment, a channel switching register is used as an example of executing a function similar to that of the selection signal transmitting means, and as an example of executing a function similar to that of the sample hold time transmitting means, a timing generating circuit is used in this embodiment. There is.

As shown in FIG. 1, the microcomputer of this embodiment includes a CPU core 11, an address decoder 12 connected to the CPU core 11 via an address bus 19, the CPU core 11 and a data bus 20. An A / D control circuit 13 and an A / D converter 14, which are connected via a sample hold circuit 15, a multiplexer 16, and analog signal input terminals 17a, 17b. In the microcomputer of this embodiment, these constituent parts are formed on one semiconductor substrate. The plurality of analog signal input terminals 17a, 17b ... (May be referred to as the analog signal input terminal 17 as a representative) include, for example, a plurality of sensors 18a, 18b. Sensor 18
Sometimes referred to as)) is connected. Although the number of the analog signal input terminals 17 and the number of the sensors 18 is four in the present embodiment, the number is not limited to this, and one or more can be selected. Analog signal input terminal 1
A multiplexer 16 is connected to 7, and the output side of the multiplexer 16 is connected to the sample hold circuit 15. The multiplexer 16 has each analog signal input terminal 1
7a, 17b ... And switches 16a, 16b ... Which are turned on / off by a channel switching signal (CHSW signal) described later transmitted from the A / D control circuit 13, and the output side of each switch 16a etc. is a sample hold circuit. Connected to 15. Therefore, analog signal input terminal 1
When a plurality of analog signals are supplied to the microcomputer through the multiplexer 7, one of them is selected by the multiplexer 16 and the sample hold circuit 15 is selected.
Sent to

The sample and hold circuit 15 is a circuit for sampling and holding the analog signal at a sample and hold time corresponding to the supplied analog signal.
A switch 15a that is turned on and off by a SHSW signal (described later) sent from the D control circuit 13, a capacitor 15b,
It is composed of a buffer amplifier 15c. The sample and hold circuit 15 configured as described above is operated by the switch 15a for a predetermined sample and hold time by the SHSW signal.
Is turned on, the analog signal passing through the switch 15a is sampled and held in the capacitor 15b. The output side of the sample hold circuit 15 is connected to the A / D converter 14. Note that the configuration of the A / D converter 14 is a known configuration and will not be described.

The A / D control circuit 13 will be described. A
The / D control circuit 13, as shown in FIG.
, Sample clock switching circuits 31a, 31b ... (Alternatively referred to as sample clock switching circuit 31) connected to the frequency dividing circuit 30, and timing generation connected to the output side of the sample clock switching circuit 31. Circuit 32
And a channel switching register 33. The frequency divider circuit 30 divides the supplied clock signal (CLK) to generate three kinds of frequency-divided signals of, for example, CLK1 to CLK3, which have different frequencies, respectively, and generate these CLK1 to CLK1. Each divided signal of CLK3 is sent to each of the sample clock switching circuits 31. Further, such a divided signal becomes a signal indicating the sample hold time. In this embodiment, the frequency-divided signal CLK1 is obtained by dividing the clock signal by 2, the frequency-divided signal CLK2 is obtained by dividing the clock signal by 4, and the frequency-divided signal C is obtained.
LK3 is obtained by dividing the clock signal by 8.
Further, the number of frequency-divided signals sent from the frequency dividing circuit 30 is not limited to the above three, and is not related to the number of analog signals supplied, that is, the number of analog signal input terminals 17.

The sample clock switching circuit 31 is connected to the data bus 20 and, in accordance with an instruction supplied from the CPU core 11 via the data bus 20, the divided signal CLK1 supplied to each sample clock switching circuit 31.
~ Any one of CLK3 is selected, and the selected divided signal is sent to the timing generation circuit 32. The number of sample clock switching circuits 31 matches the number of analog signals supplied, that is, the number of analog signal input terminals 17, and is four in this embodiment. The signal sent from the sample clock switching circuit 31a to the timing generating circuit 32 is CH1CLK, and the sample clock switching circuit 31
CH2 is a signal to be sent from b to the timing generation circuit 32.
CLK, the signal sent from the sample clock switching circuit 31c to the timing generating circuit 32 is CH3CLK, and the signal sent from the sample clock switching circuit 31d to the timing generating circuit 32 is CH4CLK. or,
The correspondence relationship between each of the sample clock switching circuits 31a to 31d and the analog signal input terminals 17a to 17d depends on an instruction from the CPU core 11. Further, different sample clock switching circuits 31 may send the same kind of frequency-divided signals to the timing generation circuit 32.

The channel switching register 33 is a channel for connecting to the data bus 20 and for turning on / off the above-mentioned switches 16a to 16d provided in the multiplexer 16 in response to an instruction supplied from the CPU core 11 via the data bus 20. The switching signals CHSW1 to CHSW4 are sent to the multiplexer 16, and the timing generation circuit 32
Also send to.

The timing generation circuit 32 sends the SHSW signal indicating the sample hold time corresponding to the analog signal supplied to the sample hold circuit 15 to the switch 15a of the sample hold circuit 15. That is, as described above, the timing generation circuit 32 includes various CH1CLK to CH4CLK signals corresponding to the sample hold time and the switches 16a to 1 provided in the multiplexer 16.
Since the channel switching signal CHSW indicating which of the 6d is turned on is supplied, the timing generation circuit 32 is
Which of the input terminals 17 is currently connected to the sample hold circuit 15?
Recognizes whether the analog signal that has passed through is being supplied,
The CHCLK signal corresponding to the recognized analog signal is selected, and the selected CHCLK signal is sent to the switch 15a as the SHSW signal. In this embodiment,
The sensor 18 connected to each input terminal 17 does not change, and the CHCLK signal can be selected based on the channel switching signal. On the other hand, when each sensor 18 connected to each input terminal 17 changes, the connection relationship between each input terminal 17 and each sensor 18 is written in the CPU core each time.

In the above timing generation circuit 32,
In the frequency dividing circuit 30, the divided signals CLK1 ... Are created and sent to the respective sample clock switching circuits 31a.
Not limited to this, as shown in FIG. 4, instead of the sample clock switching circuit 31 shown in FIG.
b (also sometimes referred to as the frequency dividing circuit 41), and the frequency dividing circuit 41 is CH1CLK to CH4CL.
Timing generation circuit 4 outputs timing signals CKST1 to CKST4 for instructing the timing of generating the K signal.
2 may be sent to each frequency dividing circuit 41. By adopting the configuration shown in FIG. 4, the following effects can be obtained. That is, in the sample clock switching circuit 31 shown in FIG. 2, a waiting time of one cycle or less in the CH1CLK to CH4CLK signals occurs, and when the cycle is long in time, the CPU core 11 gives an instruction. There will be a long waiting time. Specifically, as shown in FIG. 3, for example, when the CH1CLK signal is selected as the SHSW signal, the time “A” shown as the waiting time is generated, and for example, the CH2CLK signal is SHS.
When selected as the W signal, the time "a" shown in the figure as the waiting time occurs. On the other hand, when the frequency dividing circuit 41 shown in FIG. 4 is used, the CH1 to 4CLK signals can be sent out when the timing signals CKST1 to 4 are supplied to the frequency dividing circuit 41. Specifically, as shown in FIG. 5, for example, the timing signal CKST
The CH4CLK signal is sent in synchronism with the rising edge of the CLK signal after the signal 4 has been set to the "H" level by the instruction from the CPU core 11. As described above, the circuit configuration shown in FIG. 4 can shorten the processing time as compared with the circuit configuration shown in FIG.

The operation of the microcomputer thus configured will be described below. The clock signal CLK shown in FIG. 3 is supplied to the frequency dividing circuit 30 which constitutes the A / D control circuit 13, and the frequency dividing circuit 30 divides the clock signal CLK into two.
Frequency-divided signal CLK1, Frequency-divided signal CLK that is divided by 4
A frequency-divided signal CLK3 that is frequency-divided by 2 or 8 is created, and these frequency-divided signals CLK1 to CLK3 are converted into sample clock switching circuits 31.
a, 31b ... Each sample clock switching circuit 31 selects one of the signals CLK1 to CLK3 according to an instruction supplied from the CPU core 11 via the data bus 20. Then, as described above, the sample clock switching circuit 31a outputs any one of the selected signals CLK1 to CLK3 as the signal C.
It is sent to the timing generation circuit 32 as H1CLK, and the sample clock switching circuit 31b outputs the signal CH2CLK,
The sample clock switching circuit 31a uses the signal CH3CLK
The sample clock switching circuit 31b outputs the signal CH4CL.
K is sent to the timing generation circuit 32.

On the other hand, in response to an instruction from the CPU core 11, the channel switching register 33 sends a channel switching signal (CHSW1 to CHSW4) for turning on any of the switches 16a to 16d forming the multiplexer 16 to the switches 16a to 16d. For example, when an analog signal supplied to the analog input terminal 17a is to be A / D converted, the channel switching register 33 turns on the switch 16a connected to the input terminal 17a according to an instruction from the CPU core 11, The CHSW1 signal of H (high) level is sent to the switch 16a. The CHSW1 signal is also supplied to the timing generation circuit 32.

As described above, the timing generation circuit 32 based on the CHSW1 to CHSW signals determines which analog signal is currently A / D.
You can see if you are going to convert,
CH1CLK ~ corresponding to any of the HSW1 ~ 4 signals
Select one of the CH4CLK signals. Further, since the sensor 18 connected to each input terminal 17 does not change, the above C
The H1CLK to CH4CLK signals specify the analog signal to be A / D converted. In the above example, since the signal CHSW1 is supplied to the timing generation circuit 32, the timing generation circuit 32 selects the signal CH1CLK corresponding to the analog signal input terminal 17a from the supplied signals CH1CLK to CH4CLK.
Is sent to the switch 15a of the sample hold circuit 15 as an SHSW signal which is a signal instructing the sample hold time. Therefore, the sample hold circuit 15 is in the H level period of the signal CH1CLK, that is, SHS.
The analog signal supplied to the input terminal 17a is sampled and held according to the H level period of the W signal. After that, the timing generation circuit 32 sends an ADST signal (A / D conversion start instruction signal) to the A / D converter 14. As a result, the A / D converter 14 outputs A / D of the analog signal supplied.
Start execution of D conversion.

As described above, the analog signal input terminal 1
A / D conversion of the analog signal supplied to 7a is performed, and then the analog signal supplied to the analog signal input terminal 17b is A / D converted. The operation in this case will be described. The channel switching circuit 3 is instructed by the CPU core 11.
3 is a multiplexer 1 connected to the input terminal 17b
CHSW2 signal to H to turn on switch 16b of No. 6
Level. The timing generation circuit 32 is supplied with the CHSW2 signal as in the above-described operation,
The CH2CLK signal corresponding to the analog signal supplied to the input terminal 17b is selected from the 1CLK to CH4CLK signals and sent to the switch 15a of the sample hold circuit 15 as the SHSW signal. Therefore, the sample hold circuit 15 samples and holds the analog signal supplied to the input terminal 17b at a time corresponding to the H level period of the CH2CLK signal. Other input terminals 17
The analog signals supplied to c and 17d are sampled and held and A / D converted in the same operation.

Next, the operation of the A / D control circuit 13 having the above-mentioned configuration shown in FIG. 4 will be described.
An example is given in which the analog signal supplied to the analog signal input terminal 17d is A / D converted. In order to A / D-convert the analog signal supplied to the analog signal input terminal 17d, as shown in FIG.
The SW4 signal is supplied to the switch 16d of the multiplexer 16. On the other hand, in the meantime, a timing signal CKS for instructing the timing of generating the frequency-divided signal CH1CLK or the like by the instruction from the CPU core 11.
T4 is the timing generation circuit 4 at time t1 shown in FIG.
2 is sent to the frequency dividing circuit 41d. As a result, the frequency dividing circuit 41d sends the CH4CLK signal obtained by frequency-dividing the clock signal CLK to the timing generating circuit 42 from the time t2 immediately after the time t1. Therefore, the timing generation circuit 42 outputs the CH4CLK signal from time t2 to SHS.
The switch 15 of the sample hold circuit 15 as the W signal
Send to a. The subsequent operation is the same as the operation described above with reference to FIG. As described above, in the A / D control circuit having the configuration of FIG. 4, since the SHSW signal can be sent to the sample hold circuit 15 immediately after the timing signal CKST is sent, no processing time loss occurs.

As described above, according to the microcomputer of the present embodiment, even when a sensor having a different output impedance value is connected to the analog signal input terminal of the microcomputer, the sample hold time corresponding to each analog signal. Is selected and the sample-and-hold of the analog signal is executed at the sample-and-hold time, the load on the software of the microcomputer can be reduced, and the redundancy time by software control can be shortened.

In the above-described embodiment, the case where a plurality of analog signals are supplied to the microcomputer has been shown, but there is one input terminal and different analog signals are supplied to the input terminals. This microcomputer can be applied. In this case, the multiplexer 16 is unnecessary.

[0025]

As described above in detail, according to the present invention, the AD control means for creating and transmitting the sample hold time for sampling and holding the analog signal is provided, and the sampling time of the external signal corresponds to the output impedance of the external signal. Therefore, since the analog signal is sampled and held in accordance with the sample and hold time sent by the AD control means, it is not necessary to process the sample and hold time by software, and the software for the microcomputer can be used. The load can be reduced, and the redundancy time under software control can be shortened.

Further, according to the present invention, when a plurality of analog signals are supplied, the selection means outputs one analog signal to be sent to the sample hold means based on the selection signal sent by the selection signal sending means. select. The sample hold time creating means creates a sample hold time corresponding to each analog signal. In order to send the sample hold time corresponding to the analog signal sent to the sample hold means to the sample hold means, the sample hold time sending means selects from among the plurality of sample hold times created by the sample hold creating means. Based on the selection signal, the corresponding sample hold time is selected and sent to the sample hold means. As described above, the selection signal sending means, the sample hold time creating means, and the sample hold time sending means use the samples corresponding to the analog signals even when analog signals having different sample hold times are supplied to the microcomputer. Since the hold time is sent to the sample hold means, each analog signal is sampled and held according to the sample hold time, so that the load on the software of the microcomputer can be reduced and the software control can be performed. It is possible to reduce the redundancy time due to.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a microcomputer that is an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of an A / D control circuit shown in FIG.

FIG. 3 is a timing chart showing the operation of the A / D control circuit shown in FIG.

FIG. 4 is a block diagram showing another configuration example of the A / D control circuit shown in FIG.

5 is a timing chart showing the operation of the A / D control circuit shown in FIG.

FIG. 6 is a diagram showing a configuration of a conventional sampling circuit.

FIG. 7 is a graph showing characteristics of the sampling circuit when analog signals having different output impedances are supplied to the conventional sampling circuit.

[Explanation of Codes] 11 ... CPU core, 13 ... A / D control circuit, 14 ... A /
D converter, 15 ... Sample-hold circuit, 15a ... Switch, 16 ... Multiplexer, 16a to 16d ... Switch, 17a to 17d ... Analog signal input terminal 30 ... Dividing circuit, 31a to 31d ... Sample clock switching circuit, 32 ... Timing Generating circuit, 33 ... Channel switching register, 41a to 41d ... Dividing circuit, 4
2 ... Timing generation circuit.

Claims (3)

[Claims] 1. An analog signal input terminal to which an analog signal is supplied, sample and hold means electrically connected to the analog input terminal to sample and hold the analog signal, and electrically connected to the sample and hold means. A microcomputer comprising: an A / D conversion means for converting the sampled and held analog signal into a digital signal; and an AD for sending a sample hold time for performing sample hold of the analog signal in the sample hold means. A microcomputer comprising a control means, wherein the sample hold means performs sample hold of the analog signal based on the sample hold time supplied from the AD control means. 2. A plurality of analog signal input terminals to which respective analog signals are supplied, sample-hold means for sample-holding the analog signals supplied via the analog signal input terminals, and the sample-hold. A A / D conversion means for converting the sampled and held analog signal into digital form, the input side being connected to the plurality of analog signal input terminals and the output side being the sample and hold means. Selecting means for selecting one of the analog signals to be sent to the sample and hold means, and sample and hold time corresponding to each of the analog signals selected by the selecting means and supplied to the sample and hold means. Sample hold time creation means Selection signal transmitting means for transmitting a selection signal for selecting the one analog signal to be transmitted from the selecting means to the sample and hold means, and the respective sample and hold times are supplied from the sample and hold time creating means, Further, the selection signal is supplied from the selection signal sending means, and one of the respective sample hold times is selected based on the selection signal and sent to the sample hold means as a time for sample-holding the analog signal. A sample hold time sending means, and a microcomputer. 3. The sample-and-hold time creating means is provided with one clock signal and divides the clock signal to create a plurality of divided clock signals corresponding to the sample and hold time. 3. The microcomputer according to claim 2, further comprising a plurality of sample clock switching means which are supplied with the plurality of generated divided clock signals and which select and send any one of the plurality of divided clock signals.