JPH0217821B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a data transfer method between a processing device and a storage device in a parallel data processing device including a plurality of processing devices and a storage device.

[Technical background of the invention and its problems]

In recent years, with the development of VLSI technology, it has become easier to construct a parallel data processing device consisting of a large number of processing devices manufactured by VLSI. The biggest problem in constructing these devices is how to connect the storage unit, which is a component thereof, to the large number of processing units. Figure 1 shows a method that has been commonly used in computer systems and the like. This figure shows how a plurality of processing devices 12 to 14 are connected to a storage device 10 via a storage control section 11. The storage control unit 11 receives access requests from the processing devices 12 to 14, selects one of the processing devices issuing those requests, and controls the access to the storage device. This method is
As the number of processing devices increases, the structure of the storage control unit 11 becomes complex and a large amount of hardware is required.
The number of processing devices was limited to about eight at most.
However, once a parallel data processing device is constructed using the method shown in FIG. Almost impossible. Always preparing such extra ports is not an effective use of hardware resources and is extremely undesirable. Furthermore, each processing device 12 to 14 must always manage which part of the data stored in the storage device should be processed, and since this management is usually done by a program, each processing device It makes the program complicated. Also, when the number of processing devices is changed due to a malfunction or other reason,
It is necessary to change the program part in each processing device that manages data access, and in some cases, complicated processing such as rerotating the program for each processing device may be required.

In order to overcome the drawbacks mentioned above, the second
As shown in the figure, registers 22 to 24 are installed in each of the processing devices 12 to 14, and these registers and the control unit 11 of the storage device 10 are connected in a ring shape, so that data between the storage device and each processing device is A possible method is to force the transfer to take place. When the number of processing devices is n, the n registers 22 to 24 are configured as a shift register, and the control unit 11 reads n data from the storage device and configures the shift register via the transfer path 20. Register 22~
24, each processing device receives the data, each processing device 12-14 processes the received data and stores the result in the corresponding register 22-24, and then the shift register 22-2
4. The result is sent to the control unit 11 via the transfer path 21 and written into the storage device 10. In this method, in order to increase the number of processing devices, it is sufficient to add one register on a path connected in a ring shape and connect the processing device to that register. It is easy to add registers on the path, and any number of processing devices can be added. Further, in this case, the processing procedure of each processing device may be a procedure of receiving data from a corresponding register regardless of the number of processing devices, and storing the result in the register after processing, and there is no need to change the program. All that is required is to send data for the number of control units 11 and processing devices and to receive the same number of processing results. However, a major drawback of this method is that processing cannot be started while data is being distributed to all processing devices, leaving the processing devices idle.

Let me explain this situation in a little more detail. It is now assumed that data is transferred one after another between the registers 22 to 24 at intervals of time τ, and that each processing device processes the received data for T times. In this case n
The time required to process these pieces of data is the sum of the time nτ for sending data to n shift registers and the processing time T, nτ+T. Processing results in register 2
The time required to send the data to the control unit 11 of the storage device via channels 2 to 24 can be used to distribute the n pieces of data to be processed next to each processing device, and there is no need to add it to the above time. That is, processing devices 12 to 14
However, when the results are stored in the registers 22 to 23, the control unit 11 may send out the data to be processed one after another. Of this nτ+T time, the processing devices are operating only during the T time.If the number of processing devices is increased and the transfer time nτ and processing time are approximately the same, the operating rate of each processing device will be 1/ I'm about 2 years old.

Furthermore, if the processing time for each data is different, in this method, the data cannot be transferred until the processing that takes the longest time is completed, further increasing the possibility that the processing device will idle. For example, four processing devices have different processing times16 as shown in Figure 3.
The time it takes to process all of the data and send it back to the storage device is 4τ transfer time for 4 sets of data, 20τ processing time, and 20τ processing time for the last set of data. It takes 4τ time to send back the result, resulting in a total of 100τ hours, and the overhead of the transfer becomes very large.

[Purpose of the invention]

The present invention has been made in view of the above, and an object thereof is to provide a parallel data processing device in which a storage device and a plurality of processing devices are combined, in which processing devices can be easily added. It's about doing.

Another objective is to ensure that even if the number of processing devices changes due to the addition of processing devices or failures, the control procedures for reading and writing to storage devices and the control procedures for data transmission and reception of each processing device will be maintained. The object of the present invention is to provide a parallel data processing device that does not require any changes.

Still another object is to provide a parallel data processing device that minimizes the overhead time during which the processing device is at rest because it cannot receive data to be processed when transferring data between a storage device and a processing device. .

[Summary of the invention]

The present invention provides a system in which a storage device having a control unit and n processing devices are connected in a ring shape as nodes, and data is transferred in one direction by packets on the nodes. and an identifier for determining whether the packet is of type 1 or type 2, and the control unit generates one packet of type 1 and n packets of type 2. means for generating these packets and when receiving them from a node on the ring.
If the packet is a type 2 packet, it is sent to the node in an empty state without storing any data; if the packet is a type 2 packet, the data to be processed is read from the storage device, stored in the packet, and sent to the node; When a packet is received from a node,
If the packet holds data, it is provided with a means for extracting the data and storing it in the storage device.On the other hand, when each processing device receives the packet, (1) the data is stored in the packet, and the If the processing device does not hold the data that is being processed or has finished processing, it receives the data in the packet and forwards the empty packet to the next node; (2) If the packet is empty, the processing device is holding data that is being processed or has finished processing, and if processing is in progress, waits for the processing to complete, stores the processing result in a packet, and transfers it to the next node, (3) (1) above. , In cases other than (2), the received packet is forwarded to the next node.

It has the means.

〔Effect of the invention〕

According to the present invention, in a parallel data processing device that combines a storage device and a plurality of processing devices, since each device is connected in a ring shape as a node, adding a processing device can be performed very simply. In addition, the data transfer procedure is affected only by the status of the packets received by each device, and data can be sent and received regardless of the number of processing devices, and the number of processing devices changes. Even if the data transmission/reception is performed, it is possible to realize a coupling means that does not require any change in the data transmission/reception control procedure. Further, data transfer and processing can be performed in parallel, and even when data processing times are different, data transfer overhead can be minimized.

Furthermore, since the control section does not need to know at all which processing device transmits data or which processing device receives received data, it can have an extremely simple circuit configuration.

[Embodiments of the invention]

Next, the present invention will be explained in detail based on examples. Figure 4 shows the overall configuration. 10 is a storage device storing data, 11 is a control unit thereof, and processing devices 12 to 14 are connected in a ring shape by transfer paths 20, 21, etc., each serving as a node. Reference numeral 31 in the control unit 11 is an address counter for fetching data from the storage device 10. 32 is the result sent from the processing device.
This is an address counter for storing data in . 3
For each of 1 and 32, the starting address of data is set at the time of initial setting, and is incremented by 1 when accessing the storage device. 34 is a register that temporarily stores read data, and 35 is a register that temporarily stores data sent from the processing device. 33 is a register having a FIFO (First Fn First Out) configuration that temporarily stores packets circulating on the ring. It is assumed that n units of processing units 12 to 14 are connected. Processing device 12
42 to 44 in 14 are registers for storing packets, and 45 to 47 are parts for processing data.

As shown in FIG. 5, the data format on the transfer paths 20 and 21 that transfer data includes, in addition to a field 54 for storing data, an EXIST field 51 that becomes 1 when a packet exists on the transfer path, and an EXIST field 51 that becomes 1 when a packet exists on the transfer path. It is assumed that the field consists of a FULL field 52 which becomes 1 when the packet exists, and an N field 53 which becomes 1 when the packet is the first type packet. As will be explained in detail later, the FIFO 33 for storing packets does not need to store the entire packet shown in FIG. 5, but only the state of the N field 53 indicating whether the packet is of the first type. All you have to do is remember,
The FIFO data width only needs to be 1 bit.

First, the control section 11 generates n+1 packets. One of the packets is of the first type, and n packets are of the second type. The procedure for setting one packet as the first type (setting the N field to 1) will be explained. It is assumed that packets move between nodes every τ time, and the movement is performed synchronously. In the initial state, it is assumed that the address counter 31 contains the starting address of the storage device 10 where data to be processed is stored, and the address counter 32 contains the starting address of the area in the storage device 10 that stores the processed processing results. . Control unit 11
At the first timing, the packet is sent to the processing device 12 with the FULL feed set to 0 (indicating an empty state in which no data is stored) and the N field set to 1 (indicating that it is a first type packet).
EXIST field is set to 1).

Next, the address counter 31 determines whether the storage device 1
The data is sequentially read from 0, set in the data field 54, and the packets with the FULL field set to 1 and the N field set to 0 (indicating the second type of packet) are sent one after another to the processing device. These n packets pass through each processing device in turn, and the first packet (the first type packet with the N field set to 1) returns to the control unit 11 exactly at the (n+1)th clock. If the control unit 11 stops generating packets at this point, n+1 packets will have been generated.

Each of the n processing devices exchanges data with a packet in the following procedure. When it is detected by the field EXIST that the packet has been stored in the registers 42 to 44 corresponding to the processing device, one of the following actions is taken. This procedure will be referred to as a processing device packet transfer procedure.

(1) It is detected that the packet stores data because the FULL field is set to 1, and the processing device is not processing the previously sent data or has finished processing. If the data is not held (already sent), extract the data from the packet, start processing, set the FULL field to 0, and send it to the next node (2) The FULL field of the received packet will be set to 1.
However, if the processing device is already holding data (processing previously received data or has not yet sent out the processing result), it sends the packet as is to the next node (3) When the FULL field is 0 (no data is stored in the packet) and there is no data held by the processing device, send the packet as is to the next node (4). And if the processing device holds data that is being processed or has finished processing, if it is processing, it waits for the processing to finish, stores the processing result in a packet,
Set the FULL field to 1 and send it to the next node An example of a circuit of a processing device that performs these operations will be explained.

Although FIG. 6 shows a circuit diagram corresponding to the processing device 12, other processing devices may have a similar configuration. Transfer path 2
EXIST, FULL, indicated by 61 to 64 above 0
N field and data are in register 42, 65
-68 are set when a signal is applied to clock 98, respectively. Clock signal 98 is generated by controlling clock 97, which is commonly sent to all processing units, by AND gate 73. The control method will be explained in detail later. Note that the explanation will be made assuming that the signal line 95 is 1 for a while. A flip-flop 70 indicates whether or not the processing section 45 holds data, and is reset through a signal line 80 when the processing section 45 receives data, and is set when the processing section 45 sends out a processing result. Now processing section 45
The operation of the circuit will be explained step by step assuming that the flip-flop 70 is set and the signal line 83 is set to 1.

Since the signal line 83 is set to 1, the R gate 7
7, the outputs of the AND gate 74 and the R gate 76 each become 1, the clock signal 97 is applied to the output of the AND gate 73, and the state of the transfer path 20 is taken into the register 42. now register 42
When the field 65 is 0, that is, the EXIST field is 0, the processing section 45 detects that no packet has arrived via the signal line 82 and does nothing. The state where this field 65 is 0 is
The signal is transmitted via the AND gate 75 and the signal line 91 to the next processing device.

Next, consider the case where the EXIST field is 1 and the FULL field of field 66 is 1, that is, when a packet storing data arrives ((1) above). Since the processing unit 45 does not hold data to be processed, the processing unit 45 uses the data line 85 to
The data stored in register 42 at 68 is received, flip-flop 70 is reset, and processing begins. Further, the signal line 84 is set to 0, the B input of the multiplexer 71 is selected, the signal line 92 is set to 0 (FULL field is set to 0), and the next processing device is informed that the packet containing no data is to be transferred. . At this time, even though the signal line 83 becomes 0, the signal line 87 remains 1, so the register 4
The contents of 2 are directly transmitted to the signal line 91 via the AND gate 75. Note that the signal line 84 is set to 0 and the B input of the multiplexer 71 is selected until the next stage processing device receives the packet.
Whether or not the next-stage processing device has received the packet can be determined from the signal line 95, and the details will be explained later. When flip-flop 70 is in the reset state (i.e., holding data being processed), even if field 65 of register 42 becomes 0 (even if no packet is present), or if field 65 is 1 and field 65 is It is easy to see from the circuit diagram that even if 66 becomes 1 (even if a packet containing data arrives: (2) above), the contents of register 42 are transmitted as they are to the next processing device.

Next, suppose that an empty packet arrives while the flip-flop 70 is in the reset state ((4) above). That is, this is the case when the field 65 of the register 42 becomes 1 and the field 66 becomes 0. Assuming that the processing has not yet finished and the flip-flop 70 remains reset, the output of the R gate 77 will be 0, the output of the AND gate 75 will be 0, and the output of the R gate 76 will be the output of the inverter 78. Since it is 0, it becomes 0, the output of 73 is suppressed, no clock is applied to register 42, and its contents remain unchanged. In other words, it is in a state where it cannot receive the next packet. This state is notified to the preceding device by the signal line 96 becoming 0. Furthermore, since the output of the AND gate 75 becomes 0, data with an EXIST field of 0 is sent to the next processing device, which means that the packet is not transferred. Now, let us assume that the processing in the processing section 45 has ended. At this time, the flip-flop 70 is set by the signal line 80, and the data line 80 is set.
6 is loaded with the processing result, the signal line 84 is set to 1, and the B inputs of the multiplexers 71 and 72 are selected. At this time, the signal lines 91 and 92 become 1, and the packet storing the processing result can be sent to the next processing device. As described above, the circuit shown in FIG. 6 can realize the processing device packet transfer procedure described above.

As mentioned in the above explanation, there are cases where the packet cannot be sent to the next device. There are two possible reasons for this. One is that, as mentioned in the explanation above, an empty packet with a FULL field of 0 has been received, but processing has not yet been completed and the packet cannot be passed on to the next one. The other case is the case (4) above, and the other case is that the processing device itself can send the packet to the next stage, but the next processing device does not receive the packet. In the former case, as explained above, the output of the R gate 77 becomes 0, suppressing the output of the AND gate 73, prohibiting the application of the clock, and transmitting packets to the previous stage device via the signal line 96. It informs you that it cannot be received. In the latter case, the next stage processing device is connected to the signal line 9.
This is a case where it is notified that the packet cannot be received by setting 5 to 0. If there is no packet present in the register 42, the packet can be received from the previous stage regardless of the state of the next stage. In FIG. 6, when the field 65 of the register 42 is 0, the output of the inverter 78 is 1 and the output of the R gate 76 is 1 regardless of the state of the signal line 95, so that the clock is applied to the register 42 and the packet is not received. It is becoming possible to do this. Next, consider the case where there is already a packet in register 42. In this case, since the output of the inverter 78 is 0, the state of the signal 95 is transmitted as is to the signal 96, thereby informing the preceding device that the packet cannot be received. Note that the control unit of the storage device also controls the processing device in the previous stage.
A signal indicating whether or not packets can be received is output (however, in this system, the control unit has a FIF for storing packets, so it is always ready to receive packets). Further, this control section controls the sending of packets in accordance with a signal sent from the next stage processing device indicating whether or not the packet can be received.

Next, the operation of the control section of the storage device 10 will be explained.
Its basic operation is performed in the following steps. This will be referred to as the control section packet transfer procedure.

(1) When a packet is received from the processing device and the packet stores data, the data is written to the address of the storage device indicated by the address counter 32 shown in FIG. A field indicating whether the packet is a packet) is stored in the FIF 33. After that, add 1 to the contents of address counter 32 (2) If the sent packet is empty, add N of the packet.
The field is simply stored in the FIF33 (3) If the next processing device is able to receive the packet, extracts the data at the beginning of the FIF33, and the value is 0 (it is not a type 1 packet). ), address counter 31
Read the data and write the packet as FULL
Configure the field as 1 and the N field as 0, and send it to the next stage along with the data. At this time, the contents of the address counter 31 are incremented by 1 (4) If the next stage processing device is able to receive the packet and takes out the data at the beginning of the FIF 33 and is 1 (meaning it is a first type packet) ), set the FULL field to 0 and the N field to 1 (no data is stored) and send it to the next stage device.

FIG. 7 shows an example of a circuit of a control section that performs the above operations. Whether or not a packet has been sent can be determined by the EXIST field 101 on the transfer path.
If 101 is 1, a packet is being sent from the processing device, and at that time FULL field 102 is 1.
((1) above), the data on 104 is transferred to register 35.
, and write it into the storage device 10 using the address counter 32 as the address. At this time, the value of N field 103 indicating whether or not the packet is of type 1 is
Store in FIF33. Also, if the FULL field 102 of the sent packet is 0 ((2) above), no data has been sent, and the value of the N field is
Just import it into FIF33. These controls are carried out by the control circuit 100 through signal lines 112, 114,
115. The signal 96 indicating whether or not the next-stage processing device can receive the packet is 1 (indicating that the packet can be received), and the output from the FIF 33 indicating whether the packet is of the first type is 0 ((3) above). )), the address counter 31 is used as the address to read from the storage device 10, and the data stored in the register 34 is sent to the processing device. At this time, set the EXIST field 61 on the transfer path 20 to 1,
Set FULL field 62 to 1 (indicates that data is stored in the packet), N field 63
Let be 0.

Field 63 outputs FIF33 as is
Then, by outputting the inverted value by the inverter 107 to the field 62, the field 62,
63 control can be easily realized. Also FIF33
When the output is 1 ((4) above) (when it is a first type packet), the FULL field 62 becomes 0 and the N field 63 becomes 1, meaning that a packet containing no data has been sent. (In this case, reading from the storage device 10 does not occur). Reading from the storage device 10 and taking out data from the FIF 33 are performed by the control circuit 100 via signal lines 112, 113, and 115. Note that the signal 95 has the function of indicating whether or not the packet can be received by the processing device at the previous stage;
Since there is O33, packets can always be received, so it is always 1. As explained above, the circuit shown in FIG. 6 can realize the above-described control section packet transfer procedure.

Next, a description will be given of how data is sent and received using the packet transfer procedure described above. For the sake of simplicity, the explanation will focus on the data transmission and reception method using three processing devices. In FIGS. 8a to 8d, three processing devices P1 to P3 are connected to block 12.
0. Although the storage device and its control unit are not shown, the control unit generates four packets, reads data from the storage device, and sends it to the processing device. At this time, the fourth packet (first type packet) is sent to the processing device in an empty state in which no data is stored. That is, three pieces of data and one empty packet form a set and are sent out in sequence as shown in block 121. Block 121
The numbers in are numbers attached to data for identification, and a blank column indicates that no data is stored. Figure a shows a state in which the first data 1 is sent to P1, and since P1 does not hold any data, data 1 is fetched and processing is started. Figure b shows a state in which an empty packet to which a further packet has been sent is sent to P1. P1 holds data 1 and waits for the processing to be completed and stores the result in this empty packet. In FIG. 1B, dotted lines indicate data transmission and reception to be performed in the next step. Figure c shows a state in which the packet transfer has further progressed. Data 4 was taken into P1 in the previous step, and the packet that stored this data 4 (indicated by an asterisk) is transferred to P1 as an empty packet.
It has been sent to 2. Note that hatching indicates processed results. In the figure c, P2 transfers the processing result to an empty packet*, and in the next step, data 5 is taken into P2. Figure d shows the state where the transfer has proceeded two steps from the figure c, and data 3 processed in P3 and data 4 processed in P1 are each transferred to empty packets. In this way, the data to be processed is sent to each processing device in sequence, and the control section can obtain processing results one after another in the order in which they are sent.

Next, there are 4 processing devices, and the data processing time is 3rd.
Let's examine the timing in detail for the case shown in the figure. The results are shown in FIG. In the figure, P ₁ to _{P 4} indicate processing devices, and C indicates a control unit. Also, the subscript N indicates that it is a first type packet,
The numbers are data numbers, the circles surrounded by circles indicate that the data will be taken into the processing device at that timing, and those surrounded by squares indicate the processing results. Further, e indicates an empty packet. The control section first sends out the first type of packet in an empty state (e _N ), and then sequentially sends out data to be processed while generating packets. At step 5, the first type of packet is returned to the control section, and since five packets have been generated, packet generation is stopped at this point. As is clear from the figure, data 1 is loaded into P1 in step 2, data 2 is loaded into P2 in step 4, and data 3 is loaded into P3 in step 6. Further, in step 6, the control unit 11 transfers the first type packet (e _N ) to P1 in an empty state. The processing time for data 1 is 4, as shown in FIG. 3, and the processing ends exactly at the sixth step. That is, in the seventh step, the result is stored in a packet and sent to P2. P
1 takes in the data 5 sent in this step 7, and the time-spaced packet is sent to P2 in the 8th step. The processing of data 2 being processed by P2 is completed in this eighth step, and the processing result is stored in the sent empty packet and sent to P3. In the 9th step, P2 receives new data 6 and sends an empty packet to P3 in the 10th step. In the tenth step, the processing result of data 1 is obtained in the control section 11. P3, which received the empty packet at the 11th step, is processing data 3, but as the processing takes 20 steps as shown in Figure 3, it does not end at that point, and does not wait until the 26th step to complete the process. wait. Therefore, the packet is stopped until the 26th step. P3 sends the processing result to P4 in the 27th step and receives data 7 to be processed next. The processing time for data 4 being processed in P4 is 10 steps, and the processing is complete when an empty packet is received in the 28th step.
The result is immediately sent to the control section 11 in the next step. Thereafter, the processing proceeds in the same manner, and the data sent from the control section 11 is processed in order, and the processing results are returned to the control section 11 in that order. Note that although two packets exist in the control section in steps 11 to 26, this is because the processing device is not yet in a state where it can receive the packets and is holding them internally (FIFO). However, the received processing results are written to the storage device at that time.

As is clear from FIG. 9, it takes 60 steps to process the 16 pieces of data shown in FIG. 3 and return all the processing results to the control section.
This is true for the processing method described in relation to Figure 2.
It can be seen that it is much shorter than 100 steps.

According to the present invention, since the processing devices are connected in a ring, it is very easy to increase the number of processing devices, and since the data transfer procedure is independent of the number of devices, the number of processing devices can be increased. Alternatively, it is possible to provide a parallel data processing device in which there is no need to change the procedure at all even if the number decreases due to a failure or the like.

[Brief explanation of drawings]

FIGS. 1 and 2 are block diagrams of conventional parallel data processing devices. FIG. 3 is a diagram showing an example of processing time for certain data, FIG. 4 is a block diagram of an embodiment of the present invention, FIG. 5 is a diagram showing the format of data during data transfer, and FIG. FIG. 7 is a detailed block diagram of a control unit used in an embodiment of the present invention, and FIGS. 8 and 9 show the progress state of data transfer. FIG. 10...Storage device, 11...Control unit, 12-1
4... Processing device, 31, 32... Counter, 3
4, 35...Register, 33...FIFO, 42~
44...Register, 73-78...Logic gate,
71, 72...Multiplexer.

Claims (1)

[Scope of Claims] 1. In a system in which a storage device having a control unit and n processing devices are connected in a ring shape as nodes, and data is transferred in one direction by packets on the nodes, the packets contain data. and an identifier indicating whether the packet is of the first type or the second type.
means for generating packets of the second type; when these packets are generated and when the packets are received from a node on the ring, the packets of the first type are left in an empty state without holding any data; ,
For the second type of packet, there is a means for storing the data read from the storage device and sending it to a node on the ring, and further, when data is stored in a packet sent from a node, a means for storing the data. The storage device is provided with means for storing the data, and each processing device is provided with a means for storing data, and further, when receiving a packet holding data, if the processing device already holds the data, it is sent as is to the next node. If the packet is not held, the data in the packet is taken in, the packet is made empty, and the packet is sent to the next node, and when the empty packet is received,
If the packet does not hold data, it is sent as is to the next node, and if it does hold data, it waits for the completion of processing on the data, stores the result in the received packet, and sends it to the next node. A parallel data processing device characterized by: