JPS61131062A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To sent only data to be processed and processing contents from a master arithmetic processors to execute them and to omit the setting of the operating sequence of plural slave arithmetic processors by supervising the state of the slave arithmetic processors by a priority discriminating part. CONSTITUTION:A control processor 2 reads out a program in a main memory 5, recognizes that the read program is vector addition and decides the storing position of operand data for vector operation. Deciding the vector addition, the processor 2 outputs an adding command and two operand data to a main bus 1. If the priority of the arithmetic processors 7a-7c is set up so that the highest priority is applied to the processor close to the control processor 2, data are exclusively Inputted from the arithmetic processor having the highest priority in the idle state and the processing is started by the internal means. The arithmetic processor completing the operation and sending the operated result is turned to the idle state and can be used for the operation of the succeeding vector element.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor system, for example, a master-slave system, in which a plurality of processors can effectively execute calculations.

[Conventional technology]

In the past, there have been many attempts to improve the overall performance of multiprocessor systems by increasing parallelism. There was a problem with the control method for evenly distributing the load.

As an example of research to deal with the above-mentioned problems in parallel processing systems, there is a distribution data transfer control device for parallel processor architecture disclosed in Japanese Patent Laid-Open No. 57-172455. is shown in Figure 5.

This conventional device distributes information to a plurality of arithmetic processors, and its configuration will now be described.

In Figure 5, 1 is the main bus (bus), 2 is the control processor (master arithmetic processing unit), 3.3a to 3
G is a bus interface 7/8 unit, 4 is a resource controller, 5 is a main memory, 6°6&~6C is a local memory, and 7&~7Cri arithmetic processor (slave arithmetic processing unit).

A conventional multiprocessor system is configured as described above, and is managed by a control processor 2 and a main memory 5 in which programs and data are stored.

First, when executing a program, the control processor 2 controls the resource controller 4. Main bus 1. A program is read from the main memory 5 via the bus interface unit 3 for the main memory 5, and the content to be processed is recognized. In this case, actual processing such as calculation is performed by the calculation processors 7a to 7c.
In order to maximize the processing effect,
The operations of the bus interface 7 eighth units 3&-3C and the local memo IJ6&-60 corresponding to the respective arithmetic units 7a-7C are set in advance according to the program. After that, the control processor 2 decodes the program, reads the necessary processing data from the main memory 5, and supplies the control information necessary for processing and the processing data to the corresponding arithmetic processors 7a to 7c of the arithmetic processor 7 via the main bus 1. do.

At this time, which arithmetic processor 7a to 7G performs each process.
Whether it is received or not is determined by the operation settings described above.
Perform parallel operations for maximum efficiency.
1 [Problems to be Solved by the Invention] Conventional multiprocessor systems such as those described above are configured to set in advance which slave arithmetic processing unit will perform processing such as arithmetic operations. ,
Each bus interface unit corresponds to the control content processed by the master arithmetic processing unit.

It is necessary to set the responsiveness of the local memory in advance, and furthermore, when one of the multiple processing processors in the slave processing unit fails, the responsiveness needs to be recalculated and reset. However, there were problems in that it was time-consuming and the algorithm was complicated.

This invention has been made to solve this problem, and allows the slave processing units themselves to operate independently without presetting the operating order of the plurality of slave processing units that perform processing in response to a single processing command. The purpose of the present invention is to obtain a multiprocessor system that can monitor the status and determine whether or not data processing can be executed, and that allows a master arithmetic processing unit to perform processing without sensing the status of a plurality of slave arithmetic processing units. .

[Means for solving problems]

A multiprocessor system according to the present invention includes a plurality of slave arithmetic processing units each having a priority determination section for determining the order of execution, and executes data to be processed based on the determination result of the priority determination section. .

[For production]

In this invention, the priority determining unit monitors the status of the slave processing device, so that the master processing device can process the data to be processed, etc. by sending only the data to be processed and the processing contents. Moreover, it is not necessary to preset the operating order of the plurality of slave arithmetic processing units.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention, in which 1 is a main bus, 2 is a control processor (master arithmetic processing unit), and 5 is a program and data to be processed by the system of this invention. Main memory (memo IJ) that stores
71 to 7C are arithmetic processors (slave arithmetic processing units) that perform actual arithmetic processing based on control information and data from the control processor 2.

FIG. 2-1 is a block diagram showing the main parts of the arithmetic processors (slave arithmetic processing units) 7a to 70 shown in FIG.
Figure 2-2 is a circuit diagram showing a further essential part of Figure 2-1. In these figures 2-1 and 2-2, 10 receives control information (processing content) and data (processed data) coming from main bus 1, and returns the processing results to main bus 1. 12 is a control unit for decoding the above-mentioned control information and operating the arithmetic processors 7 & -7a. The unit 13 is an arithmetic unit that performs processing according to the supplied data.

FIG. 1 shows the operation when adding vector data as shown in the explanatory diagram of FIG. 3 in the multiprocessor system configured as described above.

This will be explained with reference to FIGS. 2-1 and 2-2.

When the control processor 2 reads the program 5A on the main memory 5, it recognizes that it is an addition of vector data.
Furthermore, the storage location of operand data 15 for vector calculation is determined. After that, the control processor 12 determines that vector addition is possible and commands addition + (plus) 14A.
and two operand data Ai + 5 bits are continuously placed on the main bus IA. Here, the arithmetic processor 7a~
If the side closest to the 7aU control processor 2 is given a higher priority, at the time the above data is transferred to the main bus 1, the processors 7a to 70 that are in an empty state and have the highest priority
It takes in the data exclusively from the server and starts processing it internally. In this case, the processing of the arithmetic processors 7a to 7a may be prioritized by linking the arithmetic processors 7a to 7C using a method such as a daisy chain. When the calculation result is obtained, the calculation processors 7a to 7C notify the control processor 2 of the completion of the calculation, so that the control processor 2 calculates one of the calculation processors 7a to 7C.
The arithmetic results are taken into the main memory 5 or the control processor 2, and then the arithmetic processors 7a to 7C become empty. Therefore, the calculation of the next vector element is performed using the calculation processors 7a to 7C that are now empty or the calculation processors 7a to 7C with the highest priority among the other empty calculation processors 97a to 7G. It turns out.

Next, it is assumed that one of the arithmetic processors 71 to 7a becomes unusable due to some kind of trouble.

Normally, in such a case, the control processor 2 needs to change the data supply algorithm upon receiving notification that the arithmetic processors 7a to 7a are down.

However, in the multiprocessor system of the present invention, the arithmetic processors 7a to 70 that are down are simply put into a busy state (
By setting the CPU to the in-use state, data processing is supplied to the other arithmetic processors 73 to 7C, and the data processing is performed.

In the above embodiment, basic operations such as vector arithmetic operations are shown as functions of the arithmetic processors 7a to 7C.
Similar effects can be achieved even with functional operations.

Further, from the control processor 2 to the calculation processors 7a to 7C,
Although an example has been shown in which control information and data are transferred serially for supplying data to the device, if high speed is required, control information and data may be transferred in parallel.

〔Effect of the invention〕

As described above, the present invention includes a plurality of slave arithmetic processing units each including a priority determination unit that determines the order of execution,
Since the data to be processed is executed based on the determination result of this priority determination section, not only is the data supply algorithm of the master processing unit simple, but also when the slave processing unit goes down or is added. In this case, we have developed a system that can perform processing without changing the algorithm, and can allocate processing without any consideration of the processing time of slave processing units to the master processing unit, allowing the system to maximize its capabilities. It has the advantage of being configurable.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
-1 is a block diagram showing the main parts of the arithmetic processor (slave arithmetic processing unit) in Fig. 1, Fig. 2-2 is a circuit diagram showing the main parts of Fig. 2-1, and Fig. Figure 4 is an explanatory diagram for explaining the data flow in Figure 4. An example of the calculation process (Ci = Ai
+Bi ), and FIG. 5 is a block diagram schematically showing a conventional multiprocessor system. In the figure, 1 is a main bus, 2 is a control processor (master arithmetic processing unit), 7a to 7C are arithmetic processors (slave arithmetic processing unit ff), and I+ is a priority determination unit. Note that the same reference numerals in each figure indicate four or equivalent parts. Patent issuer Mitsubishi Electric Corporation Figure 1 ■ 7α ~ 7c:
)・-;t! 1) Figure 2-1 Figure 43 Figure 50 Procedural amendment (spontaneous) Showa mourning, 1°, 6th

Claims (3)

[Claims] (1) A multiprocessor system comprising a master processing unit that generates data to be processed and issues instructions, and a plurality of slave processing units that are driven by the commands from the master processing unit via a bus and process the data to be processed. In the processor system, each of the slave arithmetic processing units includes a priority determination unit that determines the order of execution, and the priority determination unit determines the order of execution by transmitting only the data to be processed and processing contents from the master arithmetic processing unit. The state of the arithmetic processing units is monitored and execution is determined in the order of priority setting, and the slave arithmetic processing unit whose execution is determined based on the determination result processes the data to be processed and the processing contents. Features a multiprocessor system. (2) The multiprocessor system according to claim 1, wherein the priority determination unit executes the processing by monitoring whether the slave arithmetic processing unit is in use. (3) The multiprocessor system according to claim 1, wherein the priority determination unit executes the processing by monitoring the abnormal state of the slave arithmetic processing unit so that it is regarded as being in use.