KR100323910B1 - Data interface and high-speed communication system using the same - Google Patents

Abstract

In the data interface for transferring data between processors, the recording side register group 12 in which data of the recording side processor sending data is recorded according to the clock signal, and the data recorded in these recording side register groups is later clocked. A read register group 13 in which data is read by a read-side processor receiving data to be transferred and written by an operation, and selectively in registers in the write register group in accordance with an address signal and a write signal of the write-side processor. Recording control means 15, 14-1 to 14-n for recording and read control means 16 for selectively reading out a register in the read side register group in accordance with an address signal of the read side processor; ) And (17), and the address buffer and the data signal by the double buffer configuration of the write register and the read register. Are separately connected on the recording side and the reading side, so that each processor can transmit without interfering with each other.

Description

DATA INTERFACE AND HIGH-SPEED COMMUNICATION SYSTEM USING THE SAME}

The present invention, for example, when controlling the control targets such as machine structures, electric motors, etc. by a multi-processor arithmetic processing system of a plurality of microprocessors, the transfer between the micro-processes at a higher speed An interface to be executed and a high speed communication system using the same.

Conventionally, in the case of control by a plurality of microprocessors, a microprocessor which receives information representing a counterpart of a control target from a control target, performs arithmetic processing from the control information, and issues a direct command to the control target (hereinafter, referred to as control). Between a microprocessor (hereinafter referred to as a central processor) that issues instructions to one or more control-side processors from information from a transmission interface, a man-machine interface, or an external interface; As a method of receiving messages and various control information, serial transmission, parallax transmission or transmission using dual port memory has been implemented.

Transmission using the dual port memory means that the read / write from the control side, the center side, or both sides to the dual port memory is performed in a predetermined transfer order between the control side and the center side. It is to receive control information.

When receiving various control information between one central processor and multiple control processors, the following conditions need to be provided.

(1) The sending timing of this information by the central processor for each control processor is relatively long for the high-speed operation period within a short time in the high-speed sampling of each controlling processor. Can not be done.

(2) The data that the central processor must receive from each processor must be in the order of tens to hundreds of words, and the circuit function must exceed the size of data that can be sent in one transmission.

(3) For the high-speed computation period in a short time in the high-speed sampling of each control-side processor, the central processor affects the computation time of each control-side processor with respect to the delivery of this information, and exceeds the computation cycle of each control-side. The central processor also affects its own processing time and does not exceed the processing cycle of the central processor.

(4) The control information data received by the central processor and the control processor in one operation includes one unified consistency, which data succeeds and which data cannot fail.

In order to satisfy these conditions, each operation processing structure and circuit are realized between the central stage and the plurality of processors on the control side.

In conventional serial transmission, it is possible to select synchronous asynchronous transmission.

If one word is one byte and the number of information about one word is one, it is possible for two communicating processors to communicate without interfering with each other.

However, if the data required to be exceeded exceeds this, the transmitting side cannot transmit the next data unless the receiving side informs the processor of the transmitting side.

As a result, the two processors with different operation cycles require a handshake operation for confirmation information of "sending / unsending" and "repairing / unsuccessful" between the central side that has transmitted and received and the processor on the control side. For the sake of confirmation processing, the entire processing time is overrun by interfering with each other's processing cycles.

In the conventional serial transmission, a large buffer for storing data of tens to hundreds of words is installed in the repair data storage buffer of the interface circuit block, and if the data repairs a predetermined number of data, a repair completion flag is set and the receiving processor It is conceivable to make it possible to determine whether or not the data repair operation can be started.

However, even if this is done, the timing at which the control or central processor reads data from the serial interface buffer and the timing at which the serial interface fills the buffer collide with each other. The likelihood of failing is increased, the data cannot be reliably received by the predetermined sampling, and the certainty of data repair decreases.

In order to prevent this, a processor dedicated to high-speed communication should be installed on both sides of the communication terminal, and error processing should be performed at once. In this case, by using a communication processor, the communication processor and the central processor or the control processor must be secured in a certain order. The problem arises as to whether the control information data is transmitted without affecting the arithmetic processing. Therefore, a problem such as communication between the central processor and the control processor must be solved.

In parallel transmission, control information data must be received at the timing at which both sides are synchronized at the time of transmission.

If one side is interrupted and a separate process is performed during the control information data transfer process, the data transfer will not be established.

Either one must be interrupted for the other to interfere with each other's arithmetic processing cycles, and the entire processing time will be overwritten.

In the case of transmission using dual port memory, access can be prohibited by the BUSY terminal, etc. so that one side cannot access when one side accesses, and both sides can operate without synchronization.

However, in the central processor with a long arithmetic processing cycle, when each control processor with a short arithmetic processing cycle reads the data of the duel port memory first, the recording (that is, data transmission) of the control information data to the dual port memory fails. Done.

Although data can be retransmitted after a failure, the dual-port memory-only circuits, such as providing a dual port memory readout time zone in the processor on the control side after ensuring the consistency of a series of data transmitted at one time It cannot be in a configuration.

Sending data back to the central processor extends the processing time of the central processor.

For example, Japanese Patent Application Laid-Open No. 1-91959 provides two buffers for recording and reading, and transfers data between the two buffers after a certain time from receiving a recording signal or reading signal.

However, when the computing speeds of mutually transferring computing devices are different or the frequency of data transmission and reception is different, data transfer between buffers may not be performed reliably.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to obtain a data interface and a high-speed communication system using the same, which makes it possible to perform control information data transfer between processors in a non-interference with each other. It is done.

In addition, it is an object of the present invention to obtain a data interface and a high-speed communication system using the same, which enables data transmission in which coherence is ensured so that control information data received in one operation between processors is integrated into one.

[Initiation of invention]

In accordance with the above object, the present invention provides a data interface for transferring data between processors, wherein a recording side register group in which data of a recording side processor sending data is recorded according to a clock signal, and a recording side register group thereof. A read side register group in which data written to the read side is transmitted by a subsequent clock operation and received by the read side processor, and among the write register groups according to the address signal and write signal of the write side processor. And a read control means for selectively writing to a register in the read side register group in accordance with an address signal of the read side processor.

The present invention also provides a register write select signal generation circuit for generating a write select signal for the write control means to selectively write to a register of the write side register group in accordance with an address signal and a write signal of the write side processor; It is provided for each register of the recording side register group, and in general, when the data on which the reading side register group feeds back the data of the corresponding register is selected and is selected by the recording select signal, the data of the recording side processor is selected. A read side selector circuit for supplying data to the registers of the write side register group, wherein the read control means reads selectively to the registers of the read side register group according to the address signal of the read side processor; Register plate generating select signal for And a read side selector circuit connected to each register of the read side register group and outputting data of the registers of the read side register group selected according to the read select signal to the read side processor. It is located in the data interface.

The present invention further provides that the write control means disables the transfer of data from the write side register group to the read side register group while the read side processor reads the data, and automatically transfers the data after the writing is completed. It is characterized by a data interface.

The present invention also provides a register write select signal generation circuit for generating a write select signal for selectively writing a register in the write side register group according to the address signal and write signal of the write side processor. And data provided in each register of the recording side register group and normally fed back with data of the resist of the recording side register group. When the data is selected by the recording select signal, data of the recording side processor is selected. A recording-side selector circuit for selecting and supplying data to the registers of the recording-side register group, and each register of the reading-side register group, and typically, the data of the register corresponding to the recording-side register group is selected, When the read signal of the read processor is in the read state, A second write side selector for selecting data fed back from the data of the registers of the read side register group and supplying data to the registers of the read side register group, wherein the read control means in accordance with an address signal of the read side processor; A register read select signal generation circuit for generating a read select signal for selectively reading out a register of the read side register group, and connected to each register of the read side register group and selected according to the read select signal. And a read side selector circuit for outputting data of a register of the read side register group to the read side processor.

Further, the present invention disables the transfer of data from the recording side register group to the reading side register group while the recording control means is recording by the recording side processor, and when the specific address is written, the reading side The data interface is characterized in that the transfer of data to the register group is performed simultaneously.

Also, the present invention provides a register write select signal generation circuit for generating a write select signal for selectively writing a register in the write side register group in accordance with an address signal and a write signal of the write side processor. And data provided to each register of the recording side register group, and in general, data fed back with data of the registers of the recording side register group, and selected by the recording select signal, are the data of the recording side processor. Is selected and a read side is selected from the write side register group when writing is performed at a predetermined address in accordance with an address signal and a write signal of the write side selector circuit and the write side processor to supply data to the registers of the write side register group. To make all data transfers to registers A write completion signal generation circuit for generating a write completion signal and each register of the read side register group; typically, data fed back the data of the registers of the read side register group is selected, and the write completion signal is selected. When indicating completion of recording, the recording side register group comprises a second recording side selector circuit which selects data of a corresponding register and supplies data to a register of the reading side register group, and the read control means includes the reading side. A register read select signal generation circuit for generating a read select signal for selectively reading out a register of the read side register group in accordance with an address signal of a processor, and a respective register of the read side register group; Register of the read-side register group selected according to the signal select signal And a read-side selector circuit for outputting data of the data to the read-side processor.

In addition, the present invention disables the transfer of data from the recording side register to the reading side register group while the recording control means reads the predetermined address space by the reading side processor. The data interface is characterized in that data is transferred simultaneously to the read side register group when the write operation is performed.

Also, the present invention provides a register write select signal generation circuit for generating a write select signal for selectively writing the registers of the write side register group according to the address signal and write signal of the write side processor; And is provided for each register of the recording side register group, and normally selects data fed back the data of the register of the recording side register group, and selects data of the recording side processor when selected by the recording select signal. The write side selector circuit for supplying data to the registers of the write side register group, and from the write side register group to the read side register when a predetermined address is written in accordance with the address signal and read signal of the write side processor. Records for simultaneous data transfer A write completion signal generation circuit for generating a signal, and data provided for each register of the read side register group, and typically data fed back with data of the registers of the read side register group are selected; When displaying, the recording side register group is a second recording side selector circuit which selects data of a corresponding register and supplies data to a register of the reading side register group, and the read control means is connected to an address signal of the reading side processor. And a register read select signal generation circuit for generating a read select signal for selectively reading out a register of the read side register group, and each register of the read side register group, in accordance with the read select signal. Recalling data of the register of the selected read-side register group A data interface characterized by comprising a read side select circuit output to a read side processor.

Further, the present invention cannot transfer data from the recording side register to the reading side register while the recording control means is reading the predetermined address space, and the reading of the predetermined address space is completed. The data interface is characterized in that data is automatically transferred to the read side register group.

The present invention also provides a register write select signal generation circuit for generating a write select signal for selectively writing a register in the write side register group according to the address signal and write signal of the write side processor. And data provided for each register of the recording side register group, and in general, data fed back with data of the registers of the recording side register group, and data of the recording side processor when selected by the recording select signal. Selects a read side selector circuit for supplying data to the registers of the write side register group, and reads from the write side register group when a predetermined address is read according to an address signal and a read signal of the read side processor. Version to perform data transfer to side register all at once The read completion signal generation circuit which generates a completion signal and each register of the read side register group are selected for data fed back with the data of the registers of the read side register group. When indicating completion, the second write side selector circuit selects data of a register corresponding to the write side register group and supplies data to the registers of the read side register group, and the read control means is an address signal of the read side processor. A register read signal generation circuit for generating a read select signal for selectively reading out a register of the read side register group, and a respective register of the read side register group, and connected to the read select signal. Data of the register of the read-side register group selected accordingly. In the data interface, characterized in that the reading-side selector circuit to output to the read-side processor.

The present invention also provides a register write select signal generation circuit for generating a write select signal for selectively writing a register in the write side register group according to the address signal and write signal of the write side processor. And data provided to each register of the recording side register group, and in general, data fed back with data of the registers of the recording side register group, and when selected by the recording select signal, data of the recording side processor. Selects and writes to a predetermined address according to a write side selector circuit for supplying data to a register of the write side register group, an address signal and a write signal of the write side processor, and an address signal and read signal of the read side processor. When this is done and a predetermined address is read A write / read completion signal generation circuit for generating a write completion signal and a read completion signal for carrying out data transfer from the write side register group to the read side register all at once, and for each register of the read side register group. Normally, data that feeds back the data of the register of the read side register group is selected. When the write completion signal and the read completion signal indicate completion of writing and reading, data of the register corresponding to the write side register group is selected. And a second write side selector circuit for selectively supplying data to the registers of the read side register group, wherein the read control means is configured to selectively read the registers of the read side register group according to the address signal of the read side processor. Generate register select signal for generating read select signal And a read side selector circuit connected to respective registers of the read side register group and outputting data of the registers of the read side register group selected in accordance with the read select signal to the read side processor. In addition, the present invention provides a first processor, a high-speed communication dedicated processor connected to the first processor, and a first processor connected to the first processor through the high-speed communication dedicated processor. And a second processor configured to transmit data between the first processor and the second dedicated processor and between the first dedicated processor and the second dedicated processor, and a data interface provided between the second dedicated processor and the second dedicated processor. The data of the processor of the data sending side is written in accordance with the clock signal A read side register group in which data is read by the processor receiving the data on which the side register group and the data recorded in these recording side register groups are transferred and written by a subsequent clock operation, and the data sending side Write control means for selectively writing to a register in the write register group in accordance with an address signal and a write signal of a processor and a read in a register in the read group register group in accordance with an address of the processor sending the data. A high-speed communication system comprising a read control means for.

The present invention relates to a data interface for transferring data between processors and a high speed communication system using the same.

1 is a block diagram showing the configuration of an interface according to one embodiment of the present invention;

2 is a block diagram showing a configuration on an interface according to another embodiment of the present invention.

3 is a block diagram showing a configuration of an interface according to another embodiment of the present invention;

4 is a block diagram showing a configuration of an interface according to another embodiment of the present invention;

5 is a block diagram showing a configuration of an interface according to another embodiment of the present invention;

6 is a block diagram showing a configuration of a high speed communication system according to another embodiment of the present invention;

Best Mode for Carrying Out the Invention

Hereinafter, a data interface according to the present invention and a high speed communication system using the same will be described according to each embodiment.

In the drawings of each embodiment, the same or corresponding parts are denoted by the same reference numerals.

Example 1

1 is a diagram showing a configuration of a data interface according to one embodiment of the present invention.

This data interface is, for example, a control side processor for directly instructing an elevator group to be controlled in an elevator group management system, and information from a call button on each floor or a destination command button in an elevator car, for example. In accordance with this, a single or plural of the control-side processors are respectively provided between the central-side processors that issue commands.

The recording side processor indicates the processor of the data sending side and the reading side processor indicates the processor of the receiving side data.

In addition, in such an elevator group management system, the transmitted data becomes control information data.

In FIG. 1, 10a to 10e are input signal terminals, respectively, an address signal, a write signal, and a data signal of a recording processor are input to terminals 10a to 10c, and a clock signal for register writing is input to terminal 10d. The address signal of the processor on the read side is input to the terminal 10e.

11 is an output signal terminal, and a data signal to the read side processor is output.

12 is a write side register group which is a register circuit 12-1 to 12-n in which data is written from the write side processor, and 13 is a register circuit 13-1 to 13-n where data is read from the read side processor. Read side register group.

14-1 to 14-n are data fed back from the read side registers 13-1 to 13-n corresponding to the data signal from the write side processor to the register circuits 12-1 to 12-n on the write side. Is a recording side selector circuit provided for each of the register circuits to be supplied, respectively, and 15 corresponds to the register circuits 12-1 to 12-n according to the address signal 10a and the write signal 10b of the recording side processor. A register write select signal generation circuit for generating a write select signal for writing to a register circuit.

In addition, the register circuits 12-1 to 12-n, 13-1 to 13-n, and the selector circuits 14-1 to 14-n are provided in parallel by the number of words n to be written as the same data. It is.

16 selects a data signal from a corresponding register circuit among the register circuits 13-1 to 13-n according to the address signal 10e of the read side processor, and generates a register read select signal for outputting to the read side processor. A register read select signal generation circuit 17 is a read side selector circuit for outputting a data signal of a register circuit on the read side selected in accordance with the read select signal to a data bus of the read side processor.

The write side selector circuits 14-1 to 14-n and the register write select signal generation circuit 15 constitute write control means, and the register read select signal generation circuit 16 and the read side selector circuit 17 ) Constitutes a read control means.

The following operation is described.

In the normal operation, when the address signal and the write signal output from the recording side processor become significant, the register writing select signal generation circuit 15 causes the data signal 10c of the data bus of the recording side processor to become the recording side register circuit. A select signal is generated to control the selector circuits 14-1 to 14-n so that the writes are made in the order of (12-1 to 12-n).

For example, in the state where the selector circuit 14-1 is selected by the select signal, the data signal of the processor on the recording side through the selector circuit 14-1 to the register circuit 12-1 by the clock signal 10d. 10c is recorded.

Then, the contents of the write side register circuit 12-1 are transferred to the corresponding read side register circuit 13-1 connected to this register circuit 12-1 by the next clock operation and are recorded.

When the write operation is completed and the write signal 10b on the recording side is in an unintentional state (state not displaying the write operation), the select signal generation circuit 15 stores each selector circuit 14 to preserve the contents of the register circuit. To feed back the data signals stored in the corresponding read side register circuits 13-1 to 13-n connected to -1 to 14-n to the write side register circuits 12-1 to 12-n. Generate a select signal.

On the other hand, when the address signal 10e of the read side processor is input to the register read select signal generation circuit 16, the register read select signal is generated in the read side selector circuit 17, so that the selector circuit 17 is provided with this. The value of the register circuit 13 on the read side is output as a data signal to the read side processor in accordance with the select signal.

In this manner, the write-side buffer circuits having the write-side register circuits 12-1 to 12-n and the read-side register circuits 13-1 to 13-n have a separate double buffer structure, so that the address and data signals By being connected separately, each processor can transmit data without interfering with each other.

Example 2

2 is a diagram illustrating a configuration of a data interface according to another embodiment of the present invention.

In this embodiment, in particular, in order to enhance the reliability by completely independent of the write operation and the read operation, the value of the write side register circuit 12 is read by the read side register circuit 12 even after the write side processor is immediately after the write operation. The value of the write side register 12 is automatically transferred to the read side register 13 after completion of the read operation without the automatic transfer to 13).

In FIG. 2, the second recording side selector circuits provided in each of the register circuits 13-1 to 13-n of the reading side register group 13 in accordance with the read signal of the reading side processor inputted from the input signal terminal 10f. 18-1 to 18-n select one of the data from the corresponding register circuit connected to the write side register group 12 and the data fed back the data of the read side register group 13 to the read side To each of the register circuits 13-1 to 13-n.

In addition, the write side selector circuits 14-1 to 14-n, the register write select signal generation circuit 15, and the second write side selector circuits 18-1 to 18-n constitute recording control means, The register read select signal generation circuit 16 and the read side selector circuit 17 constitute read control means.

The selector circuit 18 is normally selected so that the data of the corresponding register circuit 12 to which the read side is connected is written by a clock synchronizing operation immediately after the write side register 12 is written. When the processor starts the read operation and the read signal 10f becomes the significant state (indicates the read operation state), the data value of the read side register circuit 13 is fed back to maintain the developed value.

When the read signal 10f is in an unintentional state (indicating that it is not in the read operation), it returns to the normal state, and the data from the register circuit 12 on the recording side is selected, and the reading side is performed by the next block synchronization signal. The value of the register circuit 12 on the recording side is automatically transferred to the register circuit 13 on the right side.

As a result, the read operation of the read side processor is not influenced at all by the write operation of the write side processor, and data transmission is possible.

Example 3

3 is a diagram illustrating a configuration of a data interface according to another embodiment of the present invention.

In this embodiment, data is transferred simultaneously from the register circuit 12 on the recording side to the register circuit 13 on the reading side at the time when all the recordings are completed from the recording side processor.

In Fig. 3, a write completion signal generation circuit for generating a select signal to each of the second write side selector circuits 18-1 to 18-n for determining the input to the readout register circuits 13-1 to 13-n. (19) is installed.

The write side selector circuits 14-1 to 14-n, the register write select signal generation circuit 15, the second write side selector circuits 18-1 to 18-n, and the write completion signal generation circuit 19 The write control means constitutes a register, and the register read select generation circuit 16 and the read side selector circuit 17 constitute read control means.

In the second embodiment, the select signal is generated by the read signal of the read side processor, but the address signal 10a and the write signal 10b of the write side processor are used as data transfer conditions to the register circuit 13 on the read side. .

In the write completion signal generation circuit 19, a write completion signal permitting data transfer from the register circuit 12 on the recording side to the corresponding register circuit 13 on the read side in a write operation to a specific address of the recording side processor. Occurs.

In other words, the write side processor writes to the register circuits 12 on all the write side and writes to any specific address, thereby reading the read side register circuits 13-1 to 13 from all the write side register circuits 12-1 to 12-n. -n) can be used to transfer data all at once.

As shown in Fig. 3, the read signal 10f of the read-side processor of the second embodiment may be applied to the condition for generating the completion signal in the write-complete signal generation circuit 19. In this case, the read-side processor The write completion signal is generated as a condition of not needing to say that the read operation is not performed.

Example 4

4 is a diagram showing the configuration of a data interface according to another embodiment of the present invention.

In this embodiment, when a read side processor reads a certain address space when reading data as a series of matching data when the read side processor reads the data, the register on the write side is read. Automatic transfer of data from the circuit 12 to the register circuit 13 on the read side is prevented.

In Fig. 4, a write completion signal generation circuit for generating a select signal to each of the second write side selector circuits 18-1 to 18-n for determining inputs to the readout register circuits 13-1 to 13-n. 20 is installed.

The address signal 10e and read signal 10f of the read side processor are used as data transfer conditions to the register circuit 13 on the read side.

The write side selector circuits 14-1 to 14-n, the register write select signal generation circuit 15, the second write side selector circuits 18-1 to 18-n, and the write completion signal generation circuit ( 20 configures the write control means, and the register read select signal generation circuit 16 and the read side selector circuit 17 constitute the read control means.

As a result, data is not transferred from the register circuit 12 on the write side to the register circuit 13 on the read side until the read side processor finishes reading a space. It becomes unified and can be trusted as a series of consistent data.

Example 5

5 is a diagram illustrating a configuration of a data interface according to another embodiment of the present invention.

In this embodiment, the functions of Embodiments 2, 3, and 4 are combined to simultaneously transfer data from the write side register circuit 12 to the read side register circuit 13 at the time when all the writes are completed from the write side processor. At the same time, the data is not automatically transferred from the register circuit 12 on the write side to the register circuit 13 on the read side while the read side processor is reading a certain address space.

In Fig. 5, writing / reading completion of generating a select signal to each of the second recording-side selector circuits 18-1 to 18-n, which determines the input to the readout register circuits 13-1 to 13-n. The signal generation circuit 21 is provided.

The address signal 10a and write signal 10b of the write side processor, and the address signal 10e and read signal 10f of the read side processor are the data transfer conditions to the register circuit 13 on the read side.

The write side selector circuits 14-1 to 14-n, the register write selector signal generation circuit 15, the second write side selector circuits 18-1 to 18-n, and the write / read completion signal generation circuit ( 21 configures the write control means, and the register read select signal generation circuit 16 and the read side selector circuit 17 constitute the read control means.

As a result, the write side processor writes to all the register side register circuits 12 and then writes to a specific address, thereby reading from all the write side register circuits 12-1 to 12-n. 13-n) data can be transferred simultaneously, and data is not transferred from the register circuit 12 on the read side to the register circuit 13 on the read side until a certain space is read by the processor on the read side. For example, a series of data read in an address space becomes the same in time and becomes reliable as data having a set of matching.

Example 6

6 is a view showing the configuration of a high-speed communication system according to another embodiment of the present invention.

In the figure, 40 is a central processor as the first processor, 41 is a control processor as the second processor, 42 is a high speed communication processor for connecting the central processor 40 and the control processor 41, and 43a and 43b. Denotes the data interface described in each of the above embodiments, and is connected between the central processor 40 and the high speed communication dedicated processor 42, and between the high speed and new processor 42 and the control side processor 41, respectively.

In the case of data transmission between the central processor 40 and the high-speed communication processor 42 and between the high-speed communication processor 42 and the control-side processor 41, the processor on the side that sends data therebetween The recording side processor becomes the processor, and the processor receiving the data becomes the read side processor, and the effects described in the above embodiments are obtained by the data interfaces 43a and 43b.

As described above, according to the present invention, a data interface for transferring data between processors is recorded on a recording side register group in which data of a recording side processor sending data is recorded according to a clock signal, and these recording side register groups. Of the write register group according to a read side register group in which data is read by the read side processor on which the recorded data is transferred by a subsequent clock operation and which receives the written data, and an address signal and a write signal of the write side processor. Write control means for selectively writing to a register of the read side and read control means for selectively reading out a register in the read side register group according to the address signal of the read side processor. By setting the double buffer of the register, So as to be connected separately to the signal and the data signal in the recording side and the reading side is hangeoteuro each processor executes the transfer of data without interfering with each other.

Further, in the present invention, the write control means disables the transfer of data from the write side register group to the read side register group during the reading period of the read side processor, and automatically transfers the data after the writing is completed. Since the read operation can be performed without affecting the write operation of the recording processor at all, the reliability of data transfer can be improved.

In the present invention, the recording control means disables the transfer of data from the recording side register group to the reading side register group during the recording period of the recording side processor, and when writing to a specific address is performed, the reading side Since the transfer of data to the register group is carried out at the same time, it is possible to transfer data to the read-side register all at once when a desired series of register writing from the write-side processor is completed.

In the present invention, if the write control means disables the transfer of data from the write register to the read register while the read side processor reads the predetermined address space, and the reading of the predetermined address space is completed, Since data transfer to the read side register group is automatically performed, data transfer from the write side register to the read side register is not performed while the read side processor reads an address space. Any address space can be read as data having a series of matching.

Further, in the present invention, data cannot be transferred from the recording side register group to the reading side register group while the recording control means is writing the recording side processor and while the reading side processor is reading a predetermined address space. When writing to a specific address or reading of a predetermined address space is completed, transfer of data to the reading side register group is automatically performed. Therefore, a desired series of register writing from the recording side processor is performed. At the time of completion, data can be transferred to the read side register at the same time, and since the data transfer from the write side register to the read side register is not possible while the address space where the read side processor is being read, the read side processor Any address space on the side must It is possible to read out as the data with the integrity of the serial.

In the present invention, data is transmitted between a first processor, a high-speed communication dedicated processor connected to the first processor, and a first processor connected to the first processor through the high-speed communication dedicated processor. And a second processor configured to provide a data interface between the first processor and the high-speed communication processor and between the high-speed communication processor and the second processor, wherein the data interface sends data. A read side in which the data of the processor is written according to a clock signal, and a read in which data is written by the processor receiving the data, in which the data recorded in the write side register group is transferred and written by a subsequent clock operation. Address register and write scene of the side register group and the processor sending the data Recording control means for selectively writing to a register in the write register group, and reading control means for selectively reading into a register in the read side register group in accordance with an address signal of a processor sending the data. Since a high-speed communication system including a high-speed communication system includes a high-speed communication processor between the recording-side processor and the reading-side processor, the processor between the recording-side processor and the high-speed communication processor and between the high-speed communication-only processor and the reading-side processor, In this case, data transmission at high speed and non-interference can be performed without affecting each other's arithmetic processing.

Claims (11)

The recording side register group in which data of the recording side processor, which sends data as a data interface for transferring data between processors, is recorded according to a clock signal, and the data recorded in these recording side register groups is transferred by a subsequent clock operation. A read side register group in which data is read by a read side processor receiving data, and a record for selectively writing to a register in the write register group according to an address signal and a write signal of the write side processor; And a read control means for selectively reading out a register in the read side register group according to a control means and an address signal of the read side processor. The method of claim 1, A register write select signal generation circuit and the write side, wherein the write control means generates a write select signal for selectively writing to a register of the write side register group in accordance with an address signal and a write signal of the write side processor; It is provided for each register of the register group, and normally selects data fed back from the corresponding register of the read side register group. When selected by the write select signal, the data of the write side processor is selected to select the write side register. And a write side selector circuit for supplying data to the registers of the group, wherein the read control means generates a read select signal for selectively reading out the registers of the read side register group in accordance with an address signal of the read side processor. A read select signal generation circuit And a read selector circuit connected to each register of the read side register group and outputting data of the register of the read side register group selected in accordance with the read select signal to the read side processor. The method of claim 1, And the write control means disables transfer of data from the write side register group to the read side register group while the read side processor is reading, and automatically transfers the data after the read completion is completed. The method of claim 3, wherein A register write select signal generation circuit for generating a write select signal for selectively writing a register in the write side register group in accordance with an address signal and a write signal of the write side processor; It is provided for each register of the side register group, and in general, the data fed back the data of the register of the recording side register group is selected, and when selected by the recording select signal, the data of the recording side processor is selected. A recording-side selector circuit for supplying data to the registers of the recording-side register group and each register of the reading-side register group, and usually selects data of corresponding registers of the recording-side register group The read side when the read signal of the processor is in the read state A second write side selector circuit for selecting data fed back from the register group registers and supplying data to the registers on the read side register group, wherein the read control means reads the data according to an address signal of the read side processor; A register read select signal generation circuit for generating a read select signal for selectively reading out a register of the side register group, and the read connected to each register of the read side register group and selected according to the read select signal; And a read side selector circuit which outputs data of a register of the side register group to the read side processor. The method of claim 1, The recording control means disables the transfer of data from the recording side register group to the reading side register group during the recording of the recording side processor, and when writing to a specific address is performed, the data to the reading side register group The data interface, characterized in that the transmission of all at once. The method of claim 5, A register write select signal generation circuit for generating a write select signal for selectively writing to a register of the write side register group, in accordance with the address signal and write signal of the write side processor; It is provided for each register of the recording side register group, and normally selects data fed back the data of the register of the recording side register group. When selected by the recording select signal, the data of the recording side processor is selected and the A recording-side selector circuit for supplying data to a register of a recording-side register group, and data from the recording-side register group to the reading-side register when writing is performed at a predetermined address in accordance with an address signal and a write signal of the recording-side processor; Record completion model to perform transfer all at once A write completion signal generation circuit for generating a call and data provided for each register of the read side register group, and typically, data fed back with data of the registers of the read side register group are selected; Is a second recording side selector circuit which selects data of a corresponding register of the recording side register group and supplies data to a register of the reading side register group, wherein the read control means includes an address signal of the reading side processor. A readout select signal generation circuit for generating a read select signal for selectively reading out a register of the read side register group, and a respective register of the read side register group and connected to the read select signal. The data of the register of the read-side register group selected according to the Data interfaces, characterized in that the reading-side selector circuit that outputs a dokcheuk processor. The method of claim 1, The write control means disables the transfer of data from the write side register to the read side register while the read side processor is reading the predetermined address space, and when the read of the predetermined address space is completed, the read side A data interface, in which data is automatically transferred to a register group. The method of claim 7, wherein A register write select signal generation circuit and the write side, wherein the write control means generates a write select signal for selectively writing to a register of the write side register group in accordance with an address signal and a write signal of the write side processor; It is provided for each register of the register group, and normally selects data fed back the data of the register of the recording side register group, and when selected by the recording select signal, selects the data of the recording side processor and writes the data. A recording side selector circuit for supplying data to a register in the side register group, and data from the recording side register group to the reading side register when a predetermined address is read in accordance with the address signal and read signal of the reading side processor; Read completion to carry out the transfer all at once A write completion signal generation circuit for generating a call, and data provided for each register of the read side register group, and typically data fed back with data of the registers of the read side register group are selected, and the write completion signal indicates completion of the read. And a second write side selector circuit for selecting data of a corresponding register of the write side register group and supplying data to the register of the read side register group, wherein the read control means is connected to an address signal of the read side processor. And a register read select signal generation circuit for generating a read select signal for selectively reading out a register of the read side register group, and a respective register of the read side register group, in accordance with the read select signal. Recalling data of the register of the selected read-side register group Data interfaces, characterized in that the reading-side selector circuit that outputs a dokcheuk processor. The method of claim 1, The recording control means disables the transfer of data from the recording side register group to the reading side register group while the recording side processor is writing and while the reading side processor is reading a predetermined address space. And when data is written to a specific address or reading of a predetermined address space is completed, data transfer to the read side register group is automatically performed. The method of claim 9, A register write select signal generation circuit for generating a write select signal for the write control means for selectively writing to a register of the write side register group in accordance with an address signal and a write signal of the write side processor; It is provided for each register of the register group and normally selects data fed back the data of the register of the recording side register group. When selected by the recording select signal, the data of the recording side processor is selected and the recording side register is selected. A write side selector circuit for supplying data to a register of a group, an address signal and a write signal of the write side processor, an address signal and a read signal of the read side processor, and when a predetermined address is written, When reading is done, A write / read completion signal generation circuit for generating a write completion signal and a write completion signal for simultaneously performing data transfer from the side register group to the read side register, and each register of the read side register group; Selects data fed back the data of the registers of the read side register group, and when the write completion signal and the write completion signal indicate completion of writing and reading, select data of the corresponding register of the write side register group A second recording side selector circuit for supplying data to the registers of the side register group, wherein the read control means reads selectively to the registers of the read side register group in accordance with an address signal of the read side processor; A register read select signal generation circuit for generating a select signal; And a read side selector circuit connected to each register of the read side register group and outputting data of the register of the read side register group selected in accordance with the read select signal to the read side processor. A first processor, a high-speed communication dedicated processor connected to the first processor, and a second processor connected to the first processor through the high-speed communication dedicated processor to perform data transfer between the first processor And an interface provided between the first processor and the high-speed communication dedicated processor, and between the high-speed communication dedicated processor and the second processor, wherein data of the processor on the side to which the data interface sends data is supplied to a clock signal. The write side register group to be written along with the read side register group, the read side register group to which data written to these write side register groups are transferred by a subsequent clock operation to receive data to be written, and the read side register group; The write register in accordance with the address signal and the write signal of the sending processor Write control means for selectively writing to a register in the register, and read control means for selectively reading out a register in the read side register group in accordance with an address signal of the processor on which the data is sent. High speed communication system.