JPH0217673A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To shorten switching delay by connecting the drain electrode of a junction type FET disposed onto the sidewall section of a semiconductor layer through an insulating layer to the semiconductor layer through the contact hole of the insulating layer on the semiconductor layer. CONSTITUTION:The base electrode extracting region 40 of a bipolar transistor 51 and the gate region of a junction type PET 52 are connected respectively by a semiconductor layer 30 containing the same conductivity type impurity. The drain electrode 49 of the junction type FET arranged onto the sidewall section of the semiconductor layer 30 through an insulating layer 42 is bonded with the semiconductor layer 30 through a contact hole 48 in an insulating layer 31 on the semiconductor layer 30. According to such constitution, the forward voltage of the junction type FET as a clamper is lowered and acquired stably, thus shortening the switching delay of the bipolar transistor.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention relates to a semiconductor device having a bipolar transistor and a junction field effect transistor clamping between its collector and base, and a method for manufacturing the same (Summary of the Invention) In order to improve the switching delay of a semiconductor device having a junction field effect transistor that clamps between a bipolar transistor and its cochlear base, the base electrode extraction region of the bipolar transistor and the gate region of the junction field effect transistor are are connected to each other by a semiconductor layer containing impurities of the same conductivity type, and an insulating r-
By configuring the drain electrode disposed through the contact hole in the insulating layer to be connected to the semiconductor layer, a stable clamper junction field effect transistor with a low forward voltage Vf can be obtained. It is something.

Further, in the method for manufacturing the semiconductor device of the present invention, the base electrode extraction region and the gate region are formed at the same time via a common impurity-containing polycrystalline silicon I-, the emitter region and the drain region are simultaneously formed, and the silicon! - By connecting the base electrode and drain electrode, it is possible to manufacture a semiconductor device having a stable clamper junction field effect transistor with a small forward voltage Vf without changing the manufacturing process of the bipolar transistor. This is what I did.

[Conventional technology]

In a bipolar transistor, reverse injection of minority carriers from the collector region to the base region at saturation causes
There is a problem that the time to turn from on to off is slow. As a method for improving this switching delay, there is a collector base clamp method using a Schottky diode.

Furthermore, Japanese Patent Laid-Open No. 119972/1983 proposes a configuration in which a junction field effect transistor is used to clamp the collector-base in place of the Schittky diode. FIG. 2 shows its configuration. In the figure, (1) is a p-type semiconductor substrate, (2) is an n-
In the collector region of p-type isolation diffusion fd (31, it is configured as an island region. (4) Swelling + buried layer, (
5) is a p-type base region, (61 (6') is a p+ base electrode extraction region, and a gap of an appropriate width is provided between them to form a channel. This channel has dimensions such that it closes with a built-in potential. (7
) is the emitter region, (8) is the base electrode extraction region (6
The n+ region (9) formed in the channel between 1 (6') in contact with both the base and collector is the collector electrode, (l
O) is an emitter electrode, (11) is a metal electrode that is ohmically connected to both the base mm extraction region (61 (6') and the n middle region (8), and (12) is a surface protective film made of 5i (h). 3 shows the equivalent circuit of this I transistor. (13) is a bipolar transistor having an emitter terminal E, a base terminal B and a collector terminal C;
14) is a clamper junction field effect transistor, where the drain D is the n medium region (8), the source S is the n-collector region (2), and the gate G is the p+ base electrode extraction region (6).
(6'). In this configuration, if the width W of the gap between the base electrode extraction region (61 (6')) is set appropriately, when a reverse bias is applied between the base and the collector (
Vctt<Vctt VBH: Hose emitter voltage,
At V (H: collector emitter voltage), the depletion layer is expanded and the channel is closed. The collector current increases, and the bias voltage between the collector and base decreases due to the voltage drop due to the load, resulting in V B! ! -V cat, the depletion layer becomes thinner, and when V B11 > V cm, the channel opens, p + base electrode extraction region + 6) (6'
) and the n-collector region (2) are connected to the metal electrode (11) and the n-collector region (2).
It is connected via the middle region (8) to clamp the voltage between the base and the collector. That is, before reverse injection occurs from the collector to the base, the channel of the junction field effect transistor (14) opens and clamps the base-collector, and the bipolar transistor (13) is quickly switched from on to off. .

[Problem to be solved by the invention]

In the configuration shown in FIG. 2 described above, the forward voltage Vf of the junction field effect transistor (14) of the clamper depends on the channel width W, and the forward voltage Vf of the junction field effect transistor (14) of the clamper depends on the channel width W, and the gate region (i.e., the p+ base electrode extraction region) (6) (6') It is determined by the diffusion of the drain region (that is, the n-medium region) (8) and the accuracy of lithography mask alignment when forming the gate region (6) (6') and the drain region (8). Due to the accuracy of these diffusion and mask alignment, the channel @W becomes unstable and the voltage to be clamped (i.e., V
f) There was a sore that made it unstable.

However, since a junction field effect transistor as a clamper can have a lower forward voltage Vf than a pn diode, it can be put to practical use if it can be stably manufactured.

In view of the above-mentioned points, the present invention provides a bipolar transistor, that is, a semiconductor device, stably having a junction field effect transistor as a clamper with a small forward voltage vr, and a method for manufacturing the same.

[Means to solve the problem]

The present invention provides a semiconductor device having a bipolar transistor (51) and a junction field effect transistor (52) that clamps between the collector base of the bipolar transistor. The gate regions (41) of the junction field effect transistors (52) are connected to each other by semiconductor layers (30) containing impurities of the same conductivity type, and the semiconductor
The drain electrode (49) of the junction field transistor arranged on the side wall of d (30) via the insulating layer (42) is connected to the contact hole () of the insulating layer (31) on the semiconductor layer (30).
It is characterized in that it is connected to the semiconductor layer (30) via a layer 48).

Further, as a method for manufacturing such a semiconductor device, a base electrode extraction region (40) of a bipolar transistor (51) is used.
) and a gate region (41) of a junction field effect transistor (52), a step of simultaneously forming an emitter region (44) of a bipolar transistor and a drain region (45) of a junction field effect transistor, a bipolar transistor The base electrode (30) of the junction field effect transistor is connected to the drain electrode (49) of the junction field effect transistor.

[Effect]

The base electrode extraction region (4o) and gate region (4o) are formed by impurity diffusion from the semiconductor layer (3o) containing impurities.
1) is formed, and the double-headed regions (4o) and (41) are connected by this semiconductor layer (30). In addition, the semiconductor layer (
A drain region (45) is formed through the insulating layer side wall portion (42) formed on the side wall portion of the train region (45).
A drain electrode (49) from step 5) is formed in the semiconductor layer (30) via a contact hole (48) in the insulating layer (31). Therefore, the gate region (41) and drain region (45) of the junction field effect transistor (52) as a clamper are formed in a self-aligned manner, that is, the channel width W is not affected by the mask alignment accuracy of conventional lithography. First, the forward voltage Vf is determined by the mask width during etching of the semiconductor layer, the width of the insulating layer side wall portion (42), and the diffusion when forming the gate region (41) and drain region (45), so that the variation is small. A junction field effect transistor with a small value can be stably obtained. Further, the base electrode extraction region (40) and the gate region (41) are formed simultaneously by diffusion from the semiconductor FW (30), and the emitter region (44) and drain region (45) are formed simultaneously, and the base electrode By connecting the base electrode formed by the semiconductor I@(30) and the drain electrode (49), which connects the extraction region (40) and the gate region (41), a bipolar transistor can be formed without changing the manufacturing process of the bipolar transistor. A semiconductor device having a junction field effect transistor of a transistor and a clamper can be easily manufactured.

〔Example〕

Hereinafter, an example of a semiconductor device and its manufacturing method according to the present invention will be described in detail with reference to FIG.

As shown in FIG. 1A, n
A shaped silicon semiconductor layer (23) is epitaxially grown to form a silicon substrate (24).

In this example, the surface direction of the substrate (24) is (111).
The substrate has a crystal plane. That is, the substray l-
The principal plane of (21) is selected as a (111) crystal plane, and therefore the plane direction of the silicon semiconductor layer (23) formed thereon is also formed as a (111) crystal plane. Then, thick 5iO by selective oxidation (LOGOS)
Separation region (25) (26) consisting of a z layer.

A B+ collector electrode extraction region (27) that reaches the n+ buried @ area (22) outside the isolation region (26), and a p+ collector electrode that reaches the p-type breast straight (21) below the isolation region (25).
After forming the respective regions 28), a portion of the surface of the n-type silicon semiconductor layer (23) corresponding to a region where a bipolar transistor is to be formed and a region where a junction field effect transistor as a clamper is to be formed is formed. selectively to 5
An insulating layer (29) of t(h, etc.) is formed, and both front regions (25) and (26) including the top of this insulating layer (29) are formed.
), and an insulating Jiii (30) such as 5t02 is formed on the entire surface including the top of this polycrystalline silicon layer (30).
31) is deposited and formed.

Next, as shown in FIG. 1B, foot etching is performed on the insulating layer (31) to form a portion that will eventually form the intrinsic base region of the bipolar transistor and a channel of the junction field effect transistor. Windows (32) and (33) are formed in the parts, respectively, and these windows (32) and (
33) through the polycrystalline silicon [(30) and selectively etching the window (32).

Windows (34) and (35) corresponding to (33) are formed. Selective etching of the polycrystalline silicon layer (30) can be carried out using an etching solution that has dependence on the silicon plane ti number, such as a KOH solution or an APW solution (ethylenediamine NH2 (CH2) 2 and pyrocatechol Cal 4 (O
H) The polycrystalline silicon layer (30) is etched relatively quickly, but the semiconductor layer (23
) until the (lit) crystal plane on the surface is exposed.
As the etching of silicon progresses, the etching rate suddenly decreases and the etching apparently stops, so the etching process is stopped at this point. In this way, windows (34) (35) are formed in which only the polycrystalline silicon layer (30) is etched away, and the surface of the semiconductor layer (23) exposed within these windows (34) (35) is ( 111) becomes a smooth surface. Then cover the window (33) (35) and cover the window (32)
The photoresist layer (34) is exposed so that only (34) is exposed.
6) After selectively coating p-type impurities such as BF2''
Alternatively, B+ (37) is ion-implanted. (38)
is the ion implantation region.

Next, as shown in FIG. 1C, the ion implantation region (38) is activated by heat treatment and the p-type intrinsic base region (39) is
At the same time, p-type impurities are diffused from the polycrystalline silicon layer (30) to form a base electrode extraction region (40), and at the same time, p-type impurities are diffused from the polycrystalline silicon layer (30) in other parts. p+ gate region (41)
form.

Next, as shown in the first diagram, a 5t02 layer is deposited on the entire surface by, for example, CVD (chemical vapor deposition), and then a 5t (h layer) is etched by anisotropic etching, such as RIE (reactive ion etching). Etch each window (33
) and (34), a 5t02 sidewall portion (42) is formed on the sidewall of the polycrystalline silicon layer (30). Next, each 5
i(h) Contains n-type impurities such as arsenic (As) over the entire surface including the base region (39) facing from the window surrounded by the Jl'J wall (42) and the n-type semiconductor layer (23). A polycrystalline silicon layer (43) is deposited and heat treated to diffuse n-type impurities from the polycrystalline silicon layer (43) to form an n-type emitter region (44) in the base region (39). At the same time, an emitter metal electrode (46) is formed through a patterned polycrystalline silicon layer (43) as shown in FIG. 1E. At the same time, a collector metal electrode (47) is formed in the collector electrode extraction region (27), and a contact hole is formed in the insulating ff1l (31) on the so-called base electrode made of polycrystalline silicon I'!1 (30). (48) through a polycrystalline silicon layer (3
A drain metal electrode (49) is formed so as to be connected to the base electrode consisting of 0) and the drain region (45). These metal electric bridges (46), (47), (49)
For example, aluminum or the like can be used.

By doing so, the collector area (50).

An NPN bipolar transistor (51) consisting of a base region (39) and an emitter region (44), and a junction field effect transistor clamping between the collector and base, ie, a gate region (41) and a drain region (45).
, a junction field effect transistor (52) consisting of a source region corresponding to a collector region (50), and a base electrode of a polycrystalline silicon layer (30) containing p-type impurities connects the base region (40) and the gate. Area (4
1) is connected, and the drain electrode (49) is connected to the insulating layer (
A target semiconductor device (53) is obtained which is connected to the polycrystalline silicon layer (30) which will become a base electrode through the contact hole (48) of 31).

According to the above-described semiconductor device (53), the gate region (41) and drain region (45) of the junction field effect transistor (52) that clamps between the collector and base of the bipolar transistor (51) are formed in a self-aligned manner. Therefore, a small and stable forward voltage Vf can be obtained. That is, the channel width W is the mask width when etching polycrystalline silicon I-(30) doped with p-type impurities using, for example, a KOH solution + 5102 sidewall portions (
42) is determined by the diffusion when forming the p+ gate region (41) and the n+ drain region (45), and is not affected by the mask alignment accuracy of lithography. Therefore, Vf
Junction field effect transistor (5
2) A bipolar transistor (
51), that is, a semiconductor device (53) can be provided.

Furthermore, the base electrode deposition region (40) of the bipolar transistor (51) and the junction field effect transistor (52)
) is simultaneously formed by diffusion from the polycrystalline silicon layer (30), and the inner regions (40) and (41) are connected by this polycrystalline silicon layer (30). Silicon layer (30) and drain electrode (
49) are connected, and the emitter region (44) and drain region (45) are connected to a polycrystalline silicon layer (49) containing n-type impurities.
43) as a diffusion source. Therefore, without changing the manufacturing process (increasing the number of steps) of the bipolar transistor (51), the bipolar transistor (51)
51) and clamper junction field effect transistor (52)
) can be easily manufactured.

〔Effect of the invention〕

According to the present invention, the forward voltage Vf of the junction field effect transistor as a clamper can be obtained smaller and more stably, so that the switching delay of the bipolar transistor can be further improved. In addition, since a semiconductor device having a junction voltage effect transistor and a bipolar transistor with a small and stable forward voltage vf can be easily manufactured without changing the manufacturing process of the bipolar transistor, this type of semiconductor device can be put to practical use. This is what makes it possible.

[Brief explanation of the drawing]

1A to 1E are cross-sectional views showing an example of a semiconductor device according to the present invention in the order of manufacturing steps, FIG. 2 is a cross-sectional view of a conventional semiconductor device, and FIG. 3 is an equivalent circuit diagram thereof. (21) is a p-type silicon semiconductor substrate, (22
) is the n0 buried region, (23) is the n-type semiconductor layer, (30
) is a polycrystalline silicon layer containing p-type impurities, (31) is S
+02 layer, (39) is the intrinsic base region, (40) is the p-base electrode extraction region, (41) is the p+ gate region, (
42) is the 5i02 side wall part, (44) is the emitter region, (
45) is the drain region, (46) is the emitter metal electrode,
(47) is a collector metal electrode, and (49) is a drain metal electrode.

Claims (1)

[Claims] 1. In a semiconductor device having a bipolar transistor and a junction field effect transistor clamping between the collector base of the bipolar transistor, a base electrode extraction region of the bipolar transistor and a gate of the junction field effect transistor. The regions are connected to each other by a semiconductor layer containing impurities of the same conductivity type, and a drain electrode of the junction field effect transistor disposed on a side wall of the semiconductor layer via an insulating layer is connected to the drain electrode of the junction field effect transistor on the semiconductor layer. A semiconductor device, characterized in that it is connected to the semiconductor layer described above through a contact hole in an insulating layer. 2. In a method for manufacturing a semiconductor device having a bipolar transistor and a junction field effect transistor clamping between the collector base of the bipolar transistor, the base electrode extraction region of the bipolar transistor and the gate region of the junction field effect transistor are separated. simultaneously forming an emitter region of the bipolar transistor and a drain region of the junction field effect transistor; and connecting a base electrode of the bipolar transistor and a drain electrode of the junction field effect transistor. A method for manufacturing a semiconductor device.