JPH02174307A - Bias circuit for push-pull amplifier - Google Patents

Bias circuit for push-pull amplifier

Info

Publication number
JPH02174307A
JPH02174307A JP63328606A JP32860688A JPH02174307A JP H02174307 A JPH02174307 A JP H02174307A JP 63328606 A JP63328606 A JP 63328606A JP 32860688 A JP32860688 A JP 32860688A JP H02174307 A JPH02174307 A JP H02174307A
Authority
JP
Japan
Prior art keywords
transformer
winding
terminal
current
push
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63328606A
Other languages
Japanese (ja)
Inventor
Hiromichi Otani
大谷 弘道
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63328606A priority Critical patent/JPH02174307A/en
Publication of JPH02174307A publication Critical patent/JPH02174307A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce current consumption by giving a DC bias current to two transistors (TRs) in series. CONSTITUTION:A current fed from a feeding terminal 3 flows from an emitter to a collector of a TR 11, passes through an output TR 19, a coil 16 and a resistor 14 and flows from the emitter of a TR 10 to the collector and reaches a ground point through an output transformer 19. Thus, the DC bias current flows in series with two TRs 10, 11. Thus, the current is halved with respect to a conventional current. Moreover, the start of winding of the output transformer 19 is selected in this case to cancel the magnetic flux due to a DC generated in two windings thereby preventing the magnetic saturation due to the DC.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は低消費電力にて動作する低歪増幅器に関する 〔従来の技術〕 第2図に従来のプッシュプル増幅器を示す0図において
、1は入力端子、2は出力端子、3は給電端子、4.5
.12.13はコンデンサ、6,7゜8、9.14.1
5は抵抗器、10.11はトランジスタ、18は入カド
ランス、19は出力トランスである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a low distortion amplifier that operates with low power consumption [Prior Art] In Fig. 2, a conventional push-pull amplifier is shown. Input terminal, 2 is output terminal, 3 is power supply terminal, 4.5
.. 12.13 is a capacitor, 6,7°8, 9.14.1
5 is a resistor, 10.11 is a transistor, 18 is an input transformer, and 19 is an output transformer.

第2図に示すように、従来プッシュプル増幅器はトラン
ス19の巻線の両端に各々トランジスタ10゜11のコ
レクタを接続し、そのトランス19の巻線の中間タップ
を接地し、各々のトランジスタ10.11はそれぞれエ
ミッタへ抵抗14.15を介して給電を受けている。
As shown in FIG. 2, the conventional push-pull amplifier connects the collectors of transistors 10 and 11 to both ends of the winding of a transformer 19, respectively, and connects the center tap of the winding of the transformer 19 to ground. 11 receives power through resistors 14 and 15 to their emitters, respectively.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のプッシュプル増幅器は歪特性を良好な状
態で使用するため、トランジスタのコレクタ電流を十分
に流す必要があり、消費電流が多いという欠点がある。
In order to use the above-described conventional push-pull amplifier with good distortion characteristics, it is necessary to allow a sufficient collector current to flow through the transistor, resulting in a drawback of high current consumption.

本発明の目的は前記課題を解決したプッシュプル増幅器
バイアス回路を提供することにある。
An object of the present invention is to provide a push-pull amplifier bias circuit that solves the above problems.

〔実施例〕〔Example〕

以下、本発明の一実施例を図により説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例を示す回路図である。FIG. 1 is a circuit diagram showing one embodiment of the present invention.

図において、本発明は3巻の巻線を有する出力トランス
19を用いるプッシュプル増幅器において、第1のトラ
ンジスタ10のコレクタを前記トランス19の第1の巻
線の第1の端子に接続し、第1のトランジスタ10のエ
ミッタを第1の抵抗器14とコイル16を介して前記ト
ランス19の第2の巻線の第1の端子に接続し、第2の
トランジスタ11のコレクタを前記トランス19の第2
の巻線の第2の端子に接続し、第2のトランジスタ11
のエミッタを第2の抵抗器15を介して給電端子3へ接
続し、前記トランス19の第1の巻線の第2の端子を接
地し、前記トランス19の第2の巻線の第1の端子をコ
ンデンサ17を介して接地したものである。その他の構
成は第2図に示す従来と同じである。
In the figure, the present invention is a push-pull amplifier using an output transformer 19 with three turns of winding, in which the collector of the first transistor 10 is connected to the first terminal of the first winding of said transformer 19; The emitter of the first transistor 10 is connected to the first terminal of the second winding of the transformer 19 via the first resistor 14 and the coil 16, and the collector of the second transistor 11 is connected to the first terminal of the second winding of the transformer 19. 2
is connected to the second terminal of the winding of the second transistor 11
The emitter of the transformer 19 is connected to the power supply terminal 3 via the second resistor 15, the second terminal of the first winding of the transformer 19 is grounded, and the first terminal of the second winding of the transformer 19 is grounded. The terminal is grounded via a capacitor 17. The rest of the structure is the same as the conventional one shown in FIG.

給電端子3から給電された電流は、トランジスタ11の
エミッタからコレクタに流れ、出力トランス19を通っ
て:1イル16、抵抗器14を通り、トランジスタ10
のエミッタからコレクタに流れ出力トランス19を通っ
て接地点へ至る。
The current supplied from the power supply terminal 3 flows from the emitter to the collector of the transistor 11, passes through the output transformer 19, passes through the output transformer 19, passes through the resistor 14, and passes through the transistor 10.
flows from the emitter to the collector, passes through the output transformer 19, and reaches the ground point.

これにより、直流バイアス電流は2個のトランジスタ1
0.11を直列に流れるため、電流を従来の半分にでき
る。又、このとき、出力トランス19の巻線の巻始めを
第1図のように選ぶことにより、2つの巻線で発生ずる
直流による磁束を打消合い、直流による磁気飽和を防い
でいる。
As a result, the DC bias current flows through the two transistors 1
0.11 flows in series, the current can be halved compared to the conventional one. Also, at this time, by selecting the beginning of the winding of the output transformer 19 as shown in FIG. 1, the magnetic fluxes due to the direct current generated in the two windings cancel each other out, thereby preventing magnetic saturation due to the direct current.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明はバイアス電流を半分にして
省消費電力を実現できる効果がある。
As explained above, the present invention has the effect of reducing power consumption by halving the bias current.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明によるブツシュグル増幅器バイアス回路
の実施例を示す回路図、第2図は従来のグツシュグル増
幅器を示す回路図である。 1・・・入力端子     2・・・出力端子3・・・
給電端子 4、5.12.13.17・・・コンデンサ6、7.8
.9.14.15・・・抵抗器10、11・・・トラン
ジスタ 16・・・コイル 19・・・出力トランス 18・・・入カドランス
FIG. 1 is a circuit diagram showing an embodiment of a Bushgur amplifier bias circuit according to the present invention, and FIG. 2 is a circuit diagram showing a conventional Bushgur amplifier. 1...Input terminal 2...Output terminal 3...
Power supply terminal 4, 5.12.13.17... Capacitor 6, 7.8
.. 9.14.15...Resistor 10, 11...Transistor 16...Coil 19...Output transformer 18...Input transformer

Claims (1)

【特許請求の範囲】[Claims] (1)3巻の巻線を有する出力トランスを用いるプッシ
ュプル増幅器において、第1のトランジスタのコレクタ
を前記トランスの第1の巻線の第1の端子に接続し、第
1のトランジスタのエミッタを第1の抵抗器とコイルを
介して前記トランスの第2の巻線の第1の端子に接続し
、第2のトランジスタのコレクタを前記トランスの第2
の巻線の第2の端子に接続し、第2のトランジスタのエ
ミッタを第2の抵抗器を介して給電端子へ接続し、前記
トランスの第1の巻線の第2の端子を接地し、前記トラ
ンスの第2の巻線の第1の端子をコンデンサを介して接
地したことを特徴とするプッシュプル増幅器バイアス回
路。
(1) In a push-pull amplifier using an output transformer having a three-turn winding, the collector of the first transistor is connected to the first terminal of the first winding of the transformer, and the emitter of the first transistor is connected to the first terminal of the first winding of the transformer. A first terminal of a second winding of the transformer is connected to a first terminal of a second winding of the transformer through a first resistor and a coil;
connecting the emitter of the second transistor to the power supply terminal via a second resistor, and grounding the second terminal of the first winding of the transformer; A push-pull amplifier bias circuit characterized in that the first terminal of the second winding of the transformer is grounded via a capacitor.
JP63328606A 1988-12-26 1988-12-26 Bias circuit for push-pull amplifier Pending JPH02174307A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63328606A JPH02174307A (en) 1988-12-26 1988-12-26 Bias circuit for push-pull amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63328606A JPH02174307A (en) 1988-12-26 1988-12-26 Bias circuit for push-pull amplifier

Publications (1)

Publication Number Publication Date
JPH02174307A true JPH02174307A (en) 1990-07-05

Family

ID=18212151

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63328606A Pending JPH02174307A (en) 1988-12-26 1988-12-26 Bias circuit for push-pull amplifier

Country Status (1)

Country Link
JP (1) JPH02174307A (en)

Similar Documents

Publication Publication Date Title
JP3306252B2 (en) Common base transistor amplifier
JPH05267944A (en) Transformer driving circuit
JPH02174307A (en) Bias circuit for push-pull amplifier
US4764735A (en) Push-pull transformer feed-back amplifier
JPS645370Y2 (en)
JPH02186705A (en) Push-pull amplifier bias circuit
US2920277A (en) Transistor amplifier
JPH04139908A (en) Bias circuit for push-pull amplifier
JPS59122207A (en) Current source
JPH04578Y2 (en)
JPH0514070A (en) Push-pull amplifier bias circuit
GB2094582A (en) Negative resistance
JPH0352027Y2 (en)
JPH0222803Y2 (en)
JPS5840646Y2 (en) amplifier circuit
JPS61140612U (en)
JP2538239Y2 (en) Low frequency amplifier circuit
SU1145448A1 (en) Generator
JPS6211105Y2 (en)
JPH0336100Y2 (en)
JPS5814414Y2 (en) Bias light warmer
JPS581853Y2 (en) magnetic recording and playback device
JPS6216795Y2 (en)
JPH0530181Y2 (en)
JPS607548Y2 (en) power amplifier