JPH02186705A - Push-pull amplifier bias circuit - Google Patents

Push-pull amplifier bias circuit

Info

Publication number
JPH02186705A
JPH02186705A JP1004677A JP467789A JPH02186705A JP H02186705 A JPH02186705 A JP H02186705A JP 1004677 A JP1004677 A JP 1004677A JP 467789 A JP467789 A JP 467789A JP H02186705 A JPH02186705 A JP H02186705A
Authority
JP
Japan
Prior art keywords
terminal
winding
transformer
transistor
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1004677A
Other languages
Japanese (ja)
Inventor
Hiromichi Otani
大谷 弘道
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1004677A priority Critical patent/JPH02186705A/en
Publication of JPH02186705A publication Critical patent/JPH02186705A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce a bias current by permitting an input current to flow from a collector to an emitter in a transistor(Tr) and permitting it to flow from a collector to an emitter in other Tr through a resistor, a coil, and an output transistor so as to attain grounding through resistor. CONSTITUTION:The collector of Tr 3 is connected to the first terminal of a first winding in a transformer 2, and the emitter is connected to the first terminal of a second winding in the transformer through the resistor 11 and the coil 13. On the other hand, the collector of Tr 4 is connected to the second terminal of the second winding in the transformer 2, and the emitter is grounded through a resistor 12. The second terminal of the first winding in the transformer 2 and the first terminal of the second winding in the transformer 2 are grounded through respective capacitors 14 and 15, and the second terminal of the first winding is set to be the power terminal of feeding. Since the DC bias current flows in two Tr in serial in such constitution, the current can be reduced to half.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はブツシュデル増幅器バイアス回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a Bushdel amplifier bias circuit.

〔従来の技術〕[Conventional technology]

20巻線の両端子に各々トランジスタ3,4のコレクタ
を接続し、前記トランス2の巻線の中間タップより給電
し、各々のトランジスタ3.4のエミッタはそれぞれ抵
抗11.12’i介して接地している。内因において1
は入カドランス、2は出力トランス、5.6.15.1
9.20はコンデンサ。
The collectors of transistors 3 and 4 are connected to both terminals of the winding 20, and power is supplied from the center tap of the winding of the transformer 2, and the emitter of each transistor 3 and 4 is grounded through a resistor 11 and 12'i, respectively. are doing. 1 in internal causes
is the input transformer, 2 is the output transformer, 5.6.15.1
9.20 is a capacitor.

?、8.9,10.11.12は抵抗器、16は入力端
子。
? , 8.9, 10.11.12 are resistors, and 16 is an input terminal.

17は出力端子、18は給電端子である。17 is an output terminal, and 18 is a power supply terminal.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のブツシュゾル増幅器は歪特性を良好な状
態で使用するため1両方のトランジスタのコレクタ電流
を十分に流すため、消費電流が多いという欠点がある。
The above-mentioned conventional Bushzol amplifier has the drawback that it consumes a large amount of current because sufficient collector currents are passed through both transistors in order to maintain good distortion characteristics.

本発明の課題は、上述した欠点を除去し、トランジスタ
のコレクタ電流を少くしたブツシュグル増幅器バイアス
回路を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a bushing amplifier bias circuit which eliminates the above-mentioned drawbacks and reduces the collector current of the transistor.

〔課題を解決するだめの手段〕[Failure to solve the problem]

本発明によれば、3巻1tJt有する出力トランスを用
いるブツシュグル増幅器において、第1のトランジスタ
のコレクタを前記トランスの第1の巻線の第1の端子に
接続し前記第1のトランジスタのエミッタを第1の抵抗
器とコイルを介して前記トランスの第2の巻線の第1の
端子に接続し、第2のトランジスタのコレクタを前記ト
ランスの第2の巻線の第2の端子に接続し、前記第2の
トランジスタのエミッタを第2の抵抗器を介して接地し
、前記トランスの第1の巻線の第2の端子と第2の巻線
の第1の端子を各々コンデンサを介して接地するか又は
コンデンサを介して接続し、更に第1の巻線又は第2の
巻線又社第1及び第20巻線よシコンデンサを介して接
地し、前記トランスの第1の巻線の第2の端子を電源端
子とすることを特徴とするプッシュプル増幅器バイアス
回路が得られる。
According to the present invention, in a Bushgur amplifier using an output transformer having 3 turns and 1 tJt, the collector of the first transistor is connected to the first terminal of the first winding of the transformer, and the emitter of the first transistor is connected to the first terminal of the first winding of the transformer. 1 resistor and a coil to a first terminal of a second winding of the transformer, and a collector of a second transistor is connected to a second terminal of a second winding of the transformer; The emitter of the second transistor is grounded via a second resistor, and the second terminal of the first winding and the first terminal of the second winding of the transformer are each grounded via a capacitor. The first winding or the second winding or the first and 20th windings are grounded through a capacitor, and the first winding of the transformer is grounded through a capacitor. A push-pull amplifier bias circuit characterized in that terminal No. 2 is used as a power supply terminal is obtained.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例の構成図である。FIG. 1 is a block diagram of an embodiment of the present invention.

第1図において第1のトランジスタ3のコレクタをトラ
ンス2の第1の巻線の第1の端子に接続シ、前記第1の
トランジスタ3のエミッタを第1の抵抗器11とコイル
13i介して前記トランス2の第2の巻線の第1の端子
に接続し、第2のトランジスタ4のコレクタを前記トラ
ンス2の第2の巻線の第2の端子に接続し、前記第2の
トランジスタ4のエミッタを第2の抵抗器12を介して
接地し、前記トランス2の第1の巻線の第2の端子と第
2の巻線の第1の端子を各々コンデンサを介して接地す
るか又はコンデンサを介して接続し。
In FIG. 1, the collector of the first transistor 3 is connected to the first terminal of the first winding of the transformer 2, and the emitter of the first transistor 3 is connected through the first resistor 11 and the coil 13i. the collector of the second transistor 4 is connected to the second terminal of the second winding of the transformer 2; The emitter is grounded via a second resistor 12, and the second terminal of the first winding and the first terminal of the second winding of the transformer 2 are respectively grounded via a capacitor or a capacitor. Connect via.

更に第1の巻線又は第2の巻線又は第1及び第2の巻線
よりコンデンサを介して接地し、前記トランスの第1の
巻線の第2の端子を電源端子としている。
Furthermore, the first winding, the second winding, or the first and second windings are grounded via a capacitor, and the second terminal of the first winding of the transformer is used as a power supply terminal.

このような構成において、給電端子18から給電された
電流は出力トランス2を通ってトランジスタ3のコレク
タからエミッタに流れ、抵抗器11、コイル13を通り
、出力トランス2を通シ。
In such a configuration, the current supplied from the power supply terminal 18 flows through the output transformer 2 from the collector to the emitter of the transistor 3, passes through the resistor 11 and the coil 13, and passes through the output transformer 2.

トランジスタ4のコレクタからエミッタに流れ。Flows from the collector of transistor 4 to the emitter.

抵抗器12より接地点へ至る。From the resistor 12 to the ground point.

これにより直流バイアス電流は2個のトランジスタを直
列に流れるため、電流を従来の半分にできる。又、この
時、出力トランスの巻線の巻始めを第1図の様に選ぶ事
により、2つの巻線で発生する直流による磁束を打消し
合い、直流による磁気包和金防いでいる。この点につい
ては従来技術と同一である。
As a result, the DC bias current flows through the two transistors in series, so the current can be halved compared to the conventional one. Also, at this time, by selecting the beginning of the winding of the output transformer as shown in Figure 1, the magnetic fluxes caused by the direct current generated in the two windings cancel each other out, thereby preventing magnetic envelopment caused by the direct current. This point is the same as the prior art.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に1本発明はバイアス電流を約172に
し、省消費電力とする効果がるる。
As explained above, in the present invention, the bias current is set to about 172, which results in the effect of saving power consumption.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明を採用したブツシュノル増幅器の実施例
の構成図、第2図は従来のプッシュプル増幅器の一例の
構成図である。 1・・・入カドランス、2・・・出力トランス、3.4
・・・トランジスタ、5,6,14.15j19.20
・・・コンデンサ、7〜12・・・抵抗器、13・・・
コイル、16・・・入力端子、17・・・出力端子、1
8・・・給電端子。
FIG. 1 is a block diagram of an embodiment of a Bushnor amplifier employing the present invention, and FIG. 2 is a block diagram of an example of a conventional push-pull amplifier. 1...Input transformer, 2...Output transformer, 3.4
...Transistor, 5, 6, 14.15j19.20
...Capacitor, 7-12...Resistor, 13...
Coil, 16...Input terminal, 17...Output terminal, 1
8...Power supply terminal.

Claims (1)

【特許請求の範囲】[Claims] 1、3巻線を有する出力トランスを用いるプッシュプル
増幅器において、第1のトランジスタのコレクタを前記
トランスの第1の巻線の第1の端子に接続し、前記第1
のトランジスタのエミッタを第1の抵抗器とコイルを介
して前記トランスの第2の巻線の第1の端子に接続し、
第2のトランジスタのコレクタを前記トランスの第2の
巻線の第2の端子に接続し、前記第2のトランジスタの
エミッタを第2の抵抗器を介して接地し、前記トランス
の第1の巻線の第2の端子と第2の巻線の第1の端子を
各々コンデンサを介して接地するか又はコンデンサを介
して接続し、更に第1の巻線又は第2の巻線又は第1及
び第2の巻線よりコンデンサを介して接地し、前記トラ
ンスの第1の巻線の第2の端子を電源端子とすることを
特徴とするプッシュプル増幅器バイアス回路。
In a push-pull amplifier using an output transformer with one or three windings, the collector of the first transistor is connected to the first terminal of the first winding of the transformer;
connecting an emitter of a transistor to a first terminal of a second winding of the transformer through a first resistor and a coil;
A collector of a second transistor is connected to a second terminal of a second winding of the transformer, an emitter of the second transistor is grounded via a second resistor, and a collector of the second transistor is connected to a second terminal of a second winding of the transformer. The second terminal of the wire and the first terminal of the second winding are each grounded or connected through a capacitor, and A push-pull amplifier bias circuit characterized in that the second winding is grounded via a capacitor, and the second terminal of the first winding of the transformer is used as a power supply terminal.
JP1004677A 1989-01-13 1989-01-13 Push-pull amplifier bias circuit Pending JPH02186705A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1004677A JPH02186705A (en) 1989-01-13 1989-01-13 Push-pull amplifier bias circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1004677A JPH02186705A (en) 1989-01-13 1989-01-13 Push-pull amplifier bias circuit

Publications (1)

Publication Number Publication Date
JPH02186705A true JPH02186705A (en) 1990-07-23

Family

ID=11590527

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1004677A Pending JPH02186705A (en) 1989-01-13 1989-01-13 Push-pull amplifier bias circuit

Country Status (1)

Country Link
JP (1) JPH02186705A (en)

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