JPS5923495B2 - gate circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gate circuit using transistors used in a sampling and holding circuit of an encoding/decoding circuit.

A conventional gate circuit is comprised of an input terminal 1, an output terminal 2, and a differential amplifier, as shown in FIG.

This differential amplifier includes transistors 4 and 4 that constitute a differential circuit.
5, a transistor 6 serving as a current source of the differential circuit, and transistors 7 and 8 serving as an active load of the differential circuit.

This gate circuit is connected to the output side of the differential amplifier (transistor 5
It is a voltage follower (the ratio of the input voltage to the output voltage is approximately 1) that provides feedback from the collector of the transistor 5 to the inverting input side (the base of the transistor 5).

The gate action is performed by controlling the base voltage of the current source transistor 6.

This gate circuit has the advantage of being extremely easy to integrate as it does not require elements such as transformers or capacitors, but on the other hand, since the maximum output current of the gate circuit is determined by the current of transistor 6, it is connected to output terminal 2. A current source with a capacity greater than or equal to the maximum current required by the load must be provided.

Therefore, when the gate circuit is ON and the input signal is small,
The load current flowing to the output terminal 2 is also small, but since a constant current is supplied from the current source, all remaining load current becomes a reactive current flowing to the (-■) power supply through the transistor 7.8.

This results in a significant increase in the power consumption of the circuit.

The object of the present invention is to provide a gate circuit which eliminates the above-mentioned drawbacks.

The gate circuit of the present invention is characterized by connecting an emitter follower to the inverting input and non-inverting input of the differential amplifier in the circuit shown in FIG. The emitter is used as an output terminal, and feedback is provided from this output terminal to the inverting input.

Next, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a circuit diagram showing one embodiment of the present invention.

Components that are the same as in FIG. 1 are given the same reference numerals.

In the figure, the base and emitter of transistor 9 are connected to input terminal 1 and the base of transistor 4, respectively.

The base and emitter of transistor 10 are connected to output terminal 2.
and the base of transistor 5, respectively, and the collectors of transistors 9 and 10 are connected to the -■ power supply.

The bases of the transistors 11 and 12 are connected to the base and gate signal terminal 3 of the transistor 6, and the emitters of each transistor are connected to the +■ power supply.

The collector of transistor 11 is connected to the emitter of transistor 9, and the collector of transistor 12 is connected to the emitter of transistor 10.

The base of the transistor 13 is connected to the collector of the transistor 5, the emitter is connected to the output terminal 2, and the collector is connected to the +V power supply.

The base of the transistor 14 is connected to the base of the transistor 7.8, the collector is connected to the output terminal 2, and the emitter is connected to the power supply.

Transistors 4-6 and 9-12 are PNP junction transistors, and transistors 7, 8, 13 and 14 are NPN junction transistors.

Next, the operation of this circuit will be explained.

When a gate signal is applied to the gate signal terminal 3, a current flows through the transistor 6゜11.12, and the transistor 9, 11
and 10, 12 operate as emitter followers, and transistors 4, 5, 7, 8 operate as a differential circuit.

When current flows through transistor 7.8, transistor 1
Current flows through transistors 13 and 14, and transistors 13 and 14 act as emitter followers.

That is, this gate circuit connects emitter followers (transistors 9 and 10) to the non-inverting input terminal and inverting input terminal (bases of transistors 4 and 5) of a differential amplifier consisting of transistors 4 and 5°7.8. Connect the output terminal (collector of transistor 5) of the differential amplifier to the emitter follower (transistor 13), and connect the output terminal (emitter of transistor 13) of the emitter follower connected to this collector to the inverting input terminal. Input terminal of emitter follower (bypass of transistor 10)
It has a voltage follower configuration as a whole.

At this time, the input signal voltage of input signal terminal 1 is the output terminal 2 (
This is obtained as an in-phase output signal.

In addition, since the current is supplied directly from the power supply +V rather than through the current source 6 as shown in Figure 1, even if the input signal voltage is small, the transistor 14 No extra current flows.

Next, when the current of gate signal terminal 3 is set to O, the current of transistors 6, 11, and 12 becomes 0, and transistors 4 and 5
．． The current of γ~10 also becomes 0.

The currents in transistors 13 and 14 are also zero because the current in transistors 7.8 is zero.

Therefore, at this time, all transistors are turned off and no current flows through the output terminal 2, so this gate circuit is turned off.

The operating current of the transistor 14 may have a current value such that the transistor 13 operates as an emitter follower when the output current of the output terminal 2 is 0.

When the output current is output from the terminal 2, the current is supplied from the voltage of +■ to the transistor 13, and when the output current flows into the gate circuit, the current is supplied to the transistor 13.
4 to the -V power supply.

In other words, the output current is supplied to the transistors 13 and 13 by the required amount.
14, it is not necessary to always flow the maximum current as in the conventional example.

Further, since the current of the transistor 14 is small, the power consumption is determined almost solely by the output current.

Note that since the current of the transistor 14 is proportional to the emitter area, the current of the transistor 14 is determined by setting this emitter area in relation to the emitter area of the transistor 7.8.

Next, with reference to FIGS. 4 and 5, the reduction in power consumption by the present invention will be explained in comparison with the conventional configuration shown in FIG. 1.

In the following description, it is assumed that the load RL is connected to the output terminal.

In Fig. 1, when the output voltage is positive, the current flowing to loads R and L is supplied from transistor 6, and when the output voltage is negative, the current flowing to load RL is absorbed by the power supply -■ through transistor 8. Ru.

At this time, transistor 8 must absorb not only the current of load RL but also the current of constant current source transistor 6.

This relationship is illustrated in FIG. 4.

In FIG. 4, the output voltage is set to {circle around (1)}, the value of the current RLI flowing through the load RL is set to 1, and the direction of the current is positive when it flows into the output terminal, and negative when it flows out.

As is clear from Fig. 4, when the output voltage is V, the load R
The maximum current flowing through L is equal to the current of transistor 6 (G).

When the output voltage is O, no current flows to the load RL, and the current of the transistor 6 flows to the transistor 8f. When the output voltage is negative, the current of the transistor 6 and the current of the load RL flow to the transistor 8 (Fig. 4). straight line T8).

On the other hand, the relationship between output voltage and current according to the present invention can be expressed as shown in FIG.

In Figure 5, when the output voltage is positive, transistor 1
The current of transistor 4 is zero, and the current of transistor 13 is proportional to current RL2 flowing through loads R and L.

When the output voltage is negative, the current of the transistor 13 is zero, and the current of the transistor 14 is proportional to the current RL2 flowing to the load RL.

Comparing FIG. 5 with FIG. 4, the current of transistor 13 is smaller than that of transistor 6, and the current of transistor 14 is also smaller than that of transistor 8, so that power consumption can be reduced.

FIG. 3 is a circuit diagram showing another embodiment of the invention, in which transistors 11 and 12 of FIG. 2 are removed and a resistor 15 is connected instead between the emitter of transistor 9 and the emitter of transistor 4. , a resistor 16 is connected between the emitter of transistor 10 and the emitter of transistor 5.

Currents determined by the base-emitter voltage VBE of transistors 4 and 5 and the values of resistors 15 and 16 flow through these resistors 15 and 16, respectively.
Similarly to FIG. 2, 10 operates as an emitter follower.

If the resistor can be realized in a smaller area than the transistor during integration, this circuit is more suitable for high-density integration.

In addition, in the embodiments shown in FIGS. 2 and 3, the PNP transistor is
PN transistor, power supply voltage +V to -V, -V to +
Even when converted to V, the effect of the present invention is not impaired,
It does the same thing.

As described above, according to the present invention, since the power consumption when the gate circuit is ON can be reduced, it is possible to easily integrate the gate circuit.

[Brief explanation of drawings]

Figure 1 shows a conventional gate circuit, Figures 2 and 3.
Each figure is a circuit diagram showing an embodiment of the present invention, and FIGS. 4 and 5 are voltage-current characteristic diagrams of FIGS. 1 and 2. In Figs. 1 to 3, 1...input terminal, 2
...Output terminal, 3...Gate signal terminal, 4-14...Transistor, 15,16...
·····resistance.

Claims (1)

[Claims] 1. A differential circuit having first and second transistors, a collector connected to the emitters of the first and second transistors, the emitter connected to one pole of a power supply, and a gate signal terminal. a first current source transistor whose base is connected; and a seventh current source transistor whose collector is connected to the respective collectors of the first and second transistors, whose emitter is connected to the other pole of the power supply and whose bases are commonly connected. and an eighth transistor, the bases of the first and second transistors (to which the collectors are connected, and the power supply (
second and third current source transistors having emitters connected to each other and bases connected to the gate signal terminal, and a second transistor having a collector connected to the power supply and a base connected to the collector of the second transistor and an output terminal. a third transistor having an emitter connected to the other pole of the power source, a collector connected to the emitter of the third transistor, and a base connected to the bases of the seventh and eighth transistors; a fifth transistor having a collector connected to the other pole of the power supply, an emitter connected to the collector of the third current source transistor, and a base connected to the output terminal; and a sixth transistor having a collector connected to the other pole of the second current source transistor, an emitter connected to the collector of the second current source transistor, and a base connected to the input terminal. 2 A differential circuit having a first and a second transistor, and a differential circuit having a collector connected to the emitters of the first and second transistors, the emitter connected to one pole of the current, and a base connected to the gate signal terminal. a current source transistor; seventh and eighth transistors having collectors connected to respective collectors of the first and second transistors, emitters connected to the other pole of the power supply, and bases commonly connected; , first and second resistors having one end connected to the bases of the first and second transistors and the other ends connected to the emitters of the first and second transistors, respectively; a third transistor whose collector is connected, whose base is connected to the collector of the second transistor and whose emitter is connected to the output terminal; and a third transistor whose emitter is connected to the other pole of the power supply and whose collector is connected to the emitter of the third transistor. a fourth transistor whose base is connected to the bases of the seventh and eighth transistors; a fourth transistor whose collector is connected to the other pole of the power supply and whose emitter is connected to the base of the second transistor and the output terminal; a fifth transistor whose base is connected to the first transistor; and a sixth transistor whose collector is connected to the other pole of the power supply, whose emitter is connected to the base of the first transistor, and whose base is connected to the input terminal. A gate circuit characterized by: