JPH02172266A - Lead, package and electric circuit device - Google Patents
Lead, package and electric circuit deviceInfo
- Publication number
- JPH02172266A JPH02172266A JP32739888A JP32739888A JPH02172266A JP H02172266 A JPH02172266 A JP H02172266A JP 32739888 A JP32739888 A JP 32739888A JP 32739888 A JP32739888 A JP 32739888A JP H02172266 A JPH02172266 A JP H02172266A
- Authority
- JP
- Japan
- Prior art keywords
- outer lead
- lead portion
- solder
- package
- bonding material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims abstract description 43
- 239000000463 material Substances 0.000 claims abstract description 26
- 238000001125 extrusion Methods 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 abstract description 29
- 230000000149 penetrating effect Effects 0.000 abstract 2
- 238000004806 packaging method and process Methods 0.000 description 6
- 238000005476 soldering Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 239000010408 film Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 238000004080 punching Methods 0.000 description 3
- 238000007650 screen-printing Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 101100136092 Drosophila melanogaster peng gene Proteins 0.000 description 1
- 229910000713 I alloy Inorganic materials 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
イ、産業上の利用分野
本発明は、リード、パッケージ及び電気回路装置に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to leads, packages, and electric circuit devices.
口、従来技術
従来の半導体装技術としては、厚膜技術をはじめ、薄膜
技術、樹脂封止、ボンディング等を夫々駆使したものが
知られている。BACKGROUND OF THE INVENTION Conventional techniques for semiconductor devices include those that make full use of thick film technology, thin film technology, resin encapsulation, bonding, and the like.
そこで、例えば、いわゆるフラットバック型と呼ばれる
表面実装法を用いた半導体装置について説明する。これ
は、プリント基板への実装密度を高くするためのもので
あって、例えばエポキシ樹脂等のモールド樹脂から突出
している端子（後述するアウターリード部４ｂ）開帳を
狭くし、この端子をモールド樹脂の対向辺（或いは４辺
）に出して後述する第１１図及び第１３図に示すように
、プリント基板１に平面付けするタイプのものである。Therefore, for example, a semiconductor device using a surface mounting method called a so-called flat back type will be described. This is to increase the mounting density on the printed circuit board. For example, the opening of the terminal protruding from the mold resin such as epoxy resin (outer lead part 4b to be described later) is narrowed, and this terminal is placed in the mold resin. It is of a type that is exposed on the opposite sides (or four sides) and attached flat to the printed circuit board 1, as shown in FIGS. 11 and 13, which will be described later.
即ち１例えば第１３図に示すように、パッケージ５に設
けられたり一ド４は、インナーリード部４ａとアウター
リード部４ｂからなる。インナーリード部４ａは、マウ
ント１０上にマウントされた半導体素子（例えばダイナ
ミックＲＡＭ等を含むＩＣチップ）７上のパッド８にボ
ンディングワイヤ（例えば金）９によって半導体素子７
と電気的に接続され、さらに全体がトランスファモール
ドにより樹脂（例えばエポキシ樹脂）６でモールドされ
ている。That is, for example, as shown in FIG. 13, the lead 4 provided in the package 5 consists of an inner lead part 4a and an outer lead part 4b. The inner lead portion 4a connects the semiconductor element 7 to a pad 8 on a semiconductor element (for example, an IC chip including a dynamic RAM, etc.) 7 mounted on a mount 10 by a bonding wire (for example, gold) 9.
The entire structure is molded with resin (for example, epoxy resin) 6 by transfer molding.
また、アウターリード部４ｂは、例えば厚さ０．１５ｍ
、１ｐＪＡ０．３５ｍｍ、半田付は部分の長さ１．０
ｍｍであり、第１１図及び第１２図に示すように、折曲
した状態に成形されている。そして、その端部がプリン
ト基板１上のＣｕの導体パターン２（厚さＱ、０５ｍｍ
、幅０．４ ｍｍ ）に例えば半田３によって電気的に
接続された状態で固定されている。また、夫々の隣り合
うアウターリード部４ｂの間隔は例えば／１．０ｍａ＋
ｚＪであり、バクケージ５全体を図示はしていないが、
この例では対向する側（第１２図参照）Ｋ夫々／１９ピ
ンＩずつ合計／３８ピンｌのアウターリード部４ｂ（！
Ｊ−ド４）がパッケージ５に設けられている。夫々のア
ウターリード部４ｂは、上述したようにして半導体素子
７及びプリント基板１上の導体パターン２上に電気的に
接続された状態で固定されている。なお、上述したアウ
ターリード部４ｂを固定する領域のパターン２の幅は例
えばｌＯ，４ｒｒｍ／Ｉであって、その隣り合うパター
ン２との間隔は例えば１０．２ｍｍＪである。Further, the outer lead portion 4b has a thickness of, for example, 0.15 m.
, 1pJA0.35mm, soldering part length 1.0
mm, and is formed into a bent state as shown in FIGS. 11 and 12. Then, the end part is a Cu conductor pattern 2 (thickness Q, 05 mm) on the printed circuit board 1.
, width 0.4 mm), and are electrically connected and fixed, for example, by solder 3. Further, the interval between adjacent outer lead portions 4b is, for example, /1.0ma+
zJ, and although the entire Bakucage 5 is not shown,
In this example, the outer lead portion 4b (!) of the opposing side (see FIG. 12) has a total of 38 pins L each with K/19 pins I.
A J-dore 4) is provided in the package 5. Each outer lead portion 4b is fixed and electrically connected onto the semiconductor element 7 and the conductive pattern 2 on the printed circuit board 1 as described above. The width of the pattern 2 in the area where the outer lead portion 4b is fixed is, for example, 10,4rrm/I, and the distance between adjacent patterns 2 is, for example, 10.2 mmJ.
以上説明したように、パッケージ５をプリント基板１に
実装する場合について考えると、夫々隣り合うアウタリ
ード部４ｂ同士の間隔が７０．３ｍｍ７と非常に狭く、
しかも夫々のアウターリード部４ｂが固定されるプリン
ト基板１上の導体パターン２同士の間隔もｔｏ、２ｍｍ
１と非常に狭（なっている。As explained above, when considering the case where the package 5 is mounted on the printed circuit board 1, the distance between the adjacent outer lead parts 4b is very narrow at 70.3 mm7.
Furthermore, the distance between the conductor patterns 2 on the printed circuit board 1 to which the respective outer lead portions 4b are fixed is also 2 mm.
1, which is very narrow.
従って、例えば半田付けの際、第１１図及び第１２図に
示すように、半田３が所定のパターン２からはみ出して
しまい、最悪の場合には隣りのパターン２又は半田３と
電気的に接続（シｍ ））Ｌ、てしまうという問題が
ある。即ち、実装歩留りを著しく低下させてしまうこと
になる。Therefore, during soldering, for example, the solder 3 may protrude from the predetermined pattern 2, as shown in FIGS. Sim )) L, there is a problem that it gets lost. In other words, the mounting yield will be significantly reduced.
また、このような問題を解決しようとすると、どうして
もパッケージ５の夫々隣り合うアウターリード部４ｂ同
士の間隔及びプリント基板１上の夫々隣り合う導体パタ
ーン２同士の間隔を大きくしなければならなくなる。こ
のことは、特に今日のように高密度実装が要求されてい
る電気回路装置においては不都合となる。Furthermore, in order to solve this problem, it is necessary to increase the distance between adjacent outer lead portions 4b of the package 5 and the distance between adjacent conductor patterns 2 on the printed circuit board 1. This is particularly inconvenient in today's electrical circuit devices that require high-density packaging.
ハ、発明の目的
本発明の目的は、信頼性の高い実装を行え、かつ実装密
度も向上することができるリード、パッケージ及び電気
回路装置を提供することにある。C. OBJECTS OF THE INVENTION An object of the present invention is to provide a lead, a package, and an electric circuit device that can be mounted with high reliability and that can also improve packaging density.
二、発明の構成
即ち、本発明は、インナーリード部と、所定の導体に接
合材を介して接合されるアウターリード部とを有し、前
記アウターリード部に接合材はみ出し防止手段が設けら
れているリードに係るものである。2. Structure of the invention, that is, the present invention has an inner lead portion and an outer lead portion that is bonded to a predetermined conductor via a bonding material, and the outer lead portion is provided with means for preventing the bonding material from protruding. This is related to the lead that is currently in use.
また、本発明は、電気部品と、この電気部品を接続した
インナーリード部と、所定の導体に接合材を介して接合
されるアウターリード部とを有し、前記アウターリード
部に接合材はみ出し防止手段が設けられているパッケー
ジも提供するものである。Further, the present invention includes an electrical component, an inner lead portion to which the electrical component is connected, and an outer lead portion that is bonded to a predetermined conductor via a bonding material, and prevents the bonding material from protruding into the outer lead portion. A package is also provided in which the means are provided.
さらに、本発明は、電気部品と、この電気部品を接続し
たインナーリード部と、所定の導体に接合材を介して接
合されるアウターリード部とを有するパッケージの前記
アウターリード部が前記導体に接合され、この接合域に
おいて前記アウターリード部と前記導体との少なくとも
一方に接合材はみ出し防止手段が設けられている電気回
路装置をも提供するものである。Furthermore, the present invention provides a package that includes an electrical component, an inner lead portion connected to the electrical component, and an outer lead portion bonded to a predetermined conductor via a bonding material, the outer lead portion being bonded to the conductor. The present invention also provides an electric circuit device in which at least one of the outer lead portion and the conductor is provided with a means for preventing extrusion of the bonding material in the bonding region.
ホ、実施例 以下、本発明の詳細な説明する。E, Example The present invention will be explained in detail below.
第１図〜第４図は本発明の第１の実施例を示すものであ
る。但し、上述した第１１図〜第１３図の例と同様の部
分については共通符号を付し、その説明を省略すること
がある。1 to 4 show a first embodiment of the present invention. However, parts similar to those in the example shown in FIGS. 11 to 13 described above are given the same reference numerals, and their explanations may be omitted.
本例によれば、第１１図〜第１３図の例と著しく異なる
構成は、第１図に示すように、厚さｏ、１５■、幅０．
３５Ｍの夫々のアウターリード部４ｂにおいてその導体
パターン２に接続される部分（接分域２０）に縦ｌＯ，
４ｔｒｍ４、横１０．１５ｍｍ４の長方形の貫通孔１２
がエツチングにより夫々設けられていることである。即
ち、図示はしていないが、この例では全部でＦ３ Ｅｌ
ピンのり−ド４があり、その夫々のアウターリード部４
ｂに貫通孔１２が夫々設けられている。この貫通孔１２
は、リードフレーム成形時のエツチングや打抜き加工で
形成してよい。なお、この例でのリード４の材質は、Ｆ
ｅ−Ｎｉ合金（４２アロイ合金）である。また、パッケ
ージ５の外形寸法は縦１２０ｍｍｎ、横／１４閤ｌ、厚
さ！２．０鵬ｊである。According to this example, the configuration that is significantly different from the examples shown in FIGS. 11 to 13 is that the thickness is o, 15 cm, and the width is 0.
In each outer lead portion 4b of 35M, a vertical lO,
4trm4, horizontal 10.15mm4 rectangular through hole 12
are provided by etching. That is, although not shown, in this example, F3 El
There is a pin lead 4, and each outer lead part 4
A through hole 12 is provided in each of b. This through hole 12
may be formed by etching or punching during lead frame molding. The material of the lead 4 in this example is F.
It is an e-Ni alloy (42 alloy alloy). Also, the external dimensions of package 5 are 120 mm long, 14 liters wide, and thick! It is 2.0 Peng.
次に、プリント基板１について説明すると、公知の方法
によって、絶縁基板（例えばフェノール樹脂）１上にＣ
ｒ％Ｃｕ、Ａｕをこの順に真空蒸着により積層し、バタ
ーニングを行って所定の導体パターン２を形成する。な
お、この導体パタ５−／２は、夫々上述したアウターリ
ード部４ｂに対して厚さｆｆＯ，０５ｍｍ１幅ｆ Ｏ，
４鵬ｊであり、隣り合うパターン２同士の間隔は夫々１
０．２ｍｍ１のものである。導体パターン２の配線幅は
ｌＯ，４Ｍｍ／！である。そして、導体パターン２上に
スクリーン印刷により厚さ１０．２Ｍｌの半田の膜３を
接合域２０に形成する。そして、雰囲気！チッ素ｌのも
とで温度ｆ２５０’Ｃ？の熱を約ｔ１５秒４間加えるこ
とによって、第２図及び第３図に示すように、パッケー
ジ５のアウターリード部４ｂを上述したプリント基板１
上の導体パターン２１Ｃ半田付けする。Next, to explain the printed circuit board 1, C is coated on an insulating substrate (for example, phenol resin) 1 by a known method.
r% Cu and Au are laminated in this order by vacuum evaporation, and patterning is performed to form a predetermined conductor pattern 2. Note that this conductor pattern 5-/2 has a thickness ffO, a width of 05 mm and a width fO, respectively, with respect to the outer lead portion 4b described above.
4, and the distance between adjacent patterns 2 is 1.
It is 0.2 mm1. The wiring width of conductor pattern 2 is lO, 4Mm/! It is. Then, a solder film 3 having a thickness of 10.2 ml is formed in the bonding area 20 on the conductive pattern 2 by screen printing. And the atmosphere! Temperature f250'C under nitrogen l? As shown in FIGS. 2 and 3, the outer lead portion 4b of the package 5 is bonded to the printed circuit board 1 as shown in FIGS.
Solder the upper conductor pattern 21C.
以上に説明したように、本実施例によるリード４及びパ
ッケージ５によれば、アウターリード部４ｂに貫通孔１
２を設けているので、第２図及び第３図に示すように、
半田３が導体パターン２からはみ出そうとしても、その
分の半田３が貫通孔１２に入り込もうとするため、十分
に接合強度を保ちながら半田３のはみ出しを防止できる
。従って、隣り合うパターン２同士がシッートすること
なく、信頼性の高い実装が行える。また、上記したよう
に信頼性の高い実装が行えるので、隣り合うアウターリ
ード部４ｂ（リード４）同士の間隔を小さくすることが
でき（即ち、所望のピッチな得ることができる。）、パ
ッケージ５自体を縮小できる（即ち、パッケージ５内部
の実装密度を高くできることにもなる。）。さらに、隣
り合う導体パターン２同士の間隔も小さくできるので、
プリント基板１上の実装密度を高くすることもできる。As explained above, according to the lead 4 and package 5 according to this embodiment, the through hole 1 is provided in the outer lead portion 4b.
2, as shown in Figures 2 and 3,
Even if the solder 3 tries to protrude from the conductor pattern 2, the solder 3 tries to enter the through hole 12, so that the solder 3 can be prevented from protruding while maintaining sufficient bonding strength. Therefore, highly reliable mounting can be performed without adjacent patterns 2 coming into contact with each other. Furthermore, since highly reliable mounting can be performed as described above, the distance between adjacent outer lead parts 4b (leads 4) can be reduced (that is, a desired pitch can be obtained), and the package 5 The package itself can be reduced in size (that is, the packaging density inside the package 5 can be increased). Furthermore, since the distance between adjacent conductor patterns 2 can be reduced,
It is also possible to increase the mounting density on the printed circuit board 1.
また、半田３とリード部４ｂとの接触部分の表面積も十
分であるため、接合強度も問題はない。Further, since the surface area of the contact portion between the solder 3 and the lead portion 4b is sufficient, there is no problem with the bonding strength.
また、これまでは半田のヌレ性等の検査は目視では困難
であったが（第１１図参照）、上述の第２図及び第３図
のように、半田３が貫通孔１２からアウターリード部４
ｂの上部側に出ているので、半田ヌレ性等の確認を目視
でも容易に行える。In addition, until now it has been difficult to visually inspect the wetting properties of solder (see Figure 11), but as shown in Figures 2 and 3 above, the solder 3 passes through the through hole 12 to the outer lead. 4
Since it is protruding from the upper side of b, it is easy to check the solder wetness etc. visually.
なお、第４図は、パーケージ５が導体パターン２上に半
田付けされている状態を示す断面図である。Note that FIG. 4 is a sectional view showing a state in which the package 5 is soldered onto the conductive pattern 2. As shown in FIG.
第５図は本発明の他の実施例を示すものであって、第５
Ａ図はアウターリード部４ｂの斜視図、第５Ｂ図）１第
５Ａ図（１）ＶＢ−ＶＢ線側面図、第５Ｃ図はｖｃ−ｖ
ｃ線断面図である。FIG. 5 shows another embodiment of the present invention.
Figure A is a perspective view of the outer lead portion 4b, Figure 5B) 1 Figure 5A (1) A side view on the VB-VB line, and Figure 5C is a vc-v
It is a sectional view taken along the c line.
本例において上述の第１図の例と異なる点は、厚さｅ
： ０．１５ｍｍ、幅ｄ：ｏ、５５ｍｏ＋のアウターリ
ード部４ｂにおいてその接合域２０に、０．１ ｔｎｎ
のアール（丸み）をもつ路長楕円状の貫通孔（スロット
）（長手方向の長さａ ： ０．４ ｍｍ、 Ｉｌｌ！
ｂ ： ０．２Ｍ）３２が設けられていることである。The difference in this example from the example shown in FIG. 1 above is that the thickness e
: 0.1 tnn in the joint area 20 of the outer lead part 4b of 0.15 mm, width d:o, 55mo+
An elliptical through hole (slot) with a roundness of (longitudinal length a: 0.4 mm, Ill!
b: 0.2M) 32 is provided.
また、その他にも第５Ｂ図に示すように、導体パターン
２及び半田［３の長手方向の寸法を、夫々図において両
側にｆ：約０．４ ａｍだけ大きく、また、第５Ｃ図の
ようにそれらの幅は夫々同一に（或いはパターン２の幅
はアウターリード部４ｂの幅よりも多少小さく）形成さ
れている。なお、その他の寸法ｃ（接合域２０における
アウターリード部４ｂの長手方向の長さ）は１．０Ｍで
ある。In addition, as shown in Fig. 5B, the longitudinal dimensions of the conductor pattern 2 and the solder [3 are increased by f: approximately 0.4 am on both sides in the figure, and as shown in Fig. 5C. Their widths are the same (or the width of pattern 2 is somewhat smaller than the width of outer lead portion 4b). Note that the other dimension c (length in the longitudinal direction of the outer lead portion 4b in the bonding region 20) is 1.0M.
上述した各寸法において、上記した貫通孔３２を設けた
場合と設けないンの半田がヌレる表面積を計算した値を
以下に示す。For each of the dimensions described above, the calculated values of the surface area where the solder wets when the above-described through hole 32 is provided and when the through hole 32 is not provided are shown below.
（以下、余白）
なお、上記の底面とは半田膜３との接触面３０を示し、
また、側面とはアウターリードｓ４ｂの厚さ方向の面３
１（貫通孔３２のある場合にはその内部におる側面も含
む）を示す。但し、リード部４ｂの上面では半田は接触
しないものとする。(Hereinafter, blank space) Note that the above-mentioned bottom surface refers to the contact surface 30 with the solder film 3,
Also, the side surface is the surface 3 in the thickness direction of the outer lead s4b.
1 (including the side surface inside the through hole 32 if there is one). However, it is assumed that the solder does not come into contact with the upper surface of the lead portion 4b.
即ち、上記したように、合計の表面積で比較すると、本
発明に基づく場合は従来例に比べて、約１２％増加して
いる。従って、上述の例と同様の利点があると共に、表
面積を大きくとれて半田付は強度上有利となる。ここで
、一般に、底面（半田膜３との接触面）３０よりも側面
（アウターリード部４ｂの厚さ方向の面）３１における
メニスカスが多くなるほど半田付けの強度が増すと考え
られるので、この例による半田付けの強度は従来例より
もずっと増すことになる。That is, as mentioned above, when comparing the total surface area, the case based on the present invention has an increase of about 12% compared to the conventional example. Therefore, in addition to having the same advantages as the above-mentioned example, a large surface area can be obtained, and soldering is advantageous in terms of strength. Here, it is generally considered that the strength of soldering increases as the number of menisci on the side surface (the surface in the thickness direction of the outer lead portion 4b) increases more than on the bottom surface (the surface in contact with the solder film 3) 30. The strength of soldering is much greater than that of the conventional method.
第６Ａ図及び第６Ｂ図は本発明の他の実施例を示すもの
であって、上述の例に比べてアウターリード部４ｂの貫
通孔の形状及び数を第６Ａ図の１３（長方形）、第６Ｂ
図の１４（円形）のように変形したものである。即ち、
これらの場合にも、上述した利点をもっていることは明
らかであると共和、半田３とリード部４ｂとの接触面積
をより大きくとれることがある。FIGS. 6A and 6B show other embodiments of the present invention, in which the shape and number of through holes in the outer lead portion 4b are different from 13 (rectangular) in FIG. 6B
It is modified as shown in 14 (circular) in the figure. That is,
It is clear that these cases also have the above-mentioned advantages, and the contact area between the solder 3 and the lead portion 4b can be made larger.
第７図は本発明の他の実施例を示すものであって、上述
の例のように貫通孔を設けるのではなく図に示すような
波状の凹部（又はデイ／プル）１５をこの例では４個ア
ウターリード部４ｂの導体ノくターン２側の面に設けた
ものである。これもエツチングで容易にでき、例えば紙
面垂直方向に延びるストライプパターンの凹部１５を４
本形成できる。この場合でも凹部１５による半田はみ出
し防止作用により上述と同様の利点をもっていると共に
、半田３がアウターリード部４ｂと接触する表面積が増
えるので、接合強度も高くなる。FIG. 7 shows another embodiment of the present invention, in which, instead of providing a through hole as in the above example, a wavy recess (or day/pull) 15 as shown in the figure is provided. Four of them are provided on the surface of the outer lead portion 4b on the conductor turn 2 side. This can also be done easily by etching, for example, by forming four recesses 15 in a stripe pattern extending perpendicular to the plane of the paper.
Can be formed into a book. Even in this case, the effect of preventing solder from extruding by the recess 15 provides the same advantages as described above, and since the surface area where the solder 3 contacts the outer lead portion 4b increases, the bonding strength also increases.
また、図示はしていないが、上述した第７図の例と同様
か或いは他の形状（例えば第１図、第６Ａ図及び第６Ｂ
図の様な形状）の凹部をプリント基板１上の導体パター
ン２に設けてもよい。この場合にも、上述の例と同様の
利点がある。即ち、導体パターン側の凹部による半田は
み出し防止作用があるため、信頼性の高い実装が行える
上に、高密度実装を実現できる電気回路装置を提供でき
る。Also, although not shown, shapes similar to the example of FIG. 7 described above or other shapes (for example, FIG. 1, FIG. 6A, and FIG. 6B)
A concave portion (shaped as shown in the figure) may be provided in the conductive pattern 2 on the printed circuit board 1. This case also has the same advantages as the above example. That is, since the concave portion on the conductor pattern side has the effect of preventing solder from extruding, it is possible to provide an electric circuit device that not only allows highly reliable mounting but also realizes high-density mounting.
或いは、第１図の例と組み合せて、アウターＩＪ −ド
部に貫通孔又は凹部を設けると同時に導体パターン２に
も凹部を設けてもよい。Alternatively, in combination with the example shown in FIG. 1, a through hole or a recess may be provided in the outer IJ-do portion and a recess may be provided in the conductor pattern 2 at the same time.
第８図は本発明の他の実施例を示すものであって、アウ
ターリード部４ｂの側面及び先端に図に示すような楔形
の切欠き部１６を設けたものである。即ち、この場合に
も切欠き部１６内に半田が入り込むため、上述の例と同
様の利点がある。FIG. 8 shows another embodiment of the present invention, in which a wedge-shaped notch 16 as shown in the figure is provided on the side surface and tip of the outer lead portion 4b. That is, in this case as well, since the solder enters into the notch 16, there is an advantage similar to that of the above-mentioned example.
第９図及び第１０図は本発明の更に他の例を示すもので
ある。FIGS. 9 and 10 show still another example of the present invention.
この例は、いわゆるピンスルーホール型と呼ばれる実装
構造において、両面に導体パターン２ａ２ｂを設けたプ
リント基板１に貫通孔（スルーホール）１８にを形成し
、これに図のように鉛直線方向に延びたアウターリード
部１７（既述の４ｂＫ対応するもの）を挿入し、予め導
体パターン２上にスクリーン印刷によって形成された半
田３により半田付けを行うものである。そして、アウタ
ーリード部１７には、図のように、その幅広の部分に上
述したと同様の円形の貫通孔１４が設けられている。即
ち、この例においても、アウターリード部１７に貫通孔
１４を設けることにより、半田３が一部分貫通孔１４に
入り込むため、横方向の広がりが抑制され上述した例と
同様の利点がある。In this example, in a mounting structure called a so-called pin-through-hole type, a through hole 18 is formed in a printed circuit board 1 with conductor patterns 2a2b on both sides, and a through hole 18 is formed in the printed circuit board 1, which extends in the vertical direction as shown in the figure. The outer lead portion 17 (corresponding to the above-mentioned 4bK) is inserted and soldered using the solder 3 previously formed on the conductor pattern 2 by screen printing. As shown in the figure, the outer lead portion 17 is provided with a circular through hole 14 similar to that described above in its wide portion. That is, in this example as well, by providing the through hole 14 in the outer lead portion 17, the solder 3 partially enters the through hole 14, so that the spread in the lateral direction is suppressed, and there is an advantage similar to the example described above.
以上、本発明を例示したが、上述の例は本発明の技術的
思想に基づいて更に変形可能である。Although the present invention has been illustrated above, the above-mentioned example can be further modified based on the technical idea of the present invention.
例えば上述したアウターリード部の貫通孔の形状は三角
形、四角形、五角形、六角形の他、適宜のものであって
よく、その数も１個又は複数であってよい。また、貫通
孔の形成方法もエツチングの他、パンチング法等が採用
でき、この場合には直径０．２５ｍ１１のものまでパン
チング可能である。For example, the shape of the through-hole of the outer lead portion described above may be triangular, quadrangular, pentagonal, hexagonal, or any other appropriate shape, and the number thereof may be one or more. In addition to etching, a punching method can be used to form the through holes, and in this case, punching up to a diameter of 0.25 m11 is possible.
また、上述したアウターリード部及び導体パターンの凹
部の形状も適宜であってよく、その形成方法もエツチン
グの他、例えばサンドブラスト法や切削工具で粗面化し
たり、また、パンチで押圧すること和より凹部な設ける
こともできる。なお、上記した貫通孔及び凹部の形状パ
ターンは必ずしも同一パターンの繰り返しである必要は
ない。Further, the shape of the outer lead portion and the recessed portion of the conductor pattern described above may be any suitable shape, and the forming method thereof may be, for example, roughening with a sandblasting method or a cutting tool, or pressing with a punch, in addition to etching. A recessed portion may also be provided. Note that the shape patterns of the through holes and recesses described above do not necessarily have to be the same repeating pattern.
また、接合材としては上述した半田の他、例えば導電性
接着剤（銀エポキシ樹脂等）を用いてもよい。また、上
述した導体パターン２上の半田膜３はスクリーン印刷の
他、例えばディッピングで形成しても・よく、第９図及
び第１０図の例におけるスルーホール１８にはスルーホ
ールメツキが施されていてよい。なお、上述の例では導
体パターンの形成を真空蒸着により行ったが、例えばス
パッタリングも採用できる。導体パターンの材質も変更
可能である。In addition to the solder described above, for example, a conductive adhesive (such as silver epoxy resin) may be used as the bonding material. Further, the solder film 3 on the conductor pattern 2 described above may be formed by, for example, dipping in addition to screen printing, and the through holes 18 in the examples of FIGS. 9 and 10 are plated. It's fine. In the above example, the conductor pattern was formed by vacuum deposition, but sputtering, for example, can also be used. The material of the conductor pattern can also be changed.
また、リード（インナーリード部及びアウターリード部
）の材質も上述した！４２７０イ合金ｌの他１例えば！
銅合金ｉであってよい。In addition, the materials of the leads (inner lead part and outer lead part) are also mentioned above! 4270 I alloy l and 1 other example!
It may be a copper alloy i.
また、上述した接合域２０においてアウターリード部と
導体の両者に接合材はみ出し手段（貫通孔或いは凹部）
を設けてもよい。In addition, in the above-mentioned bonding area 20, a bonding material protruding means (through hole or recess) is provided in both the outer lead portion and the conductor.
may be provided.
なお、本発明は、上述の例の他、例えばＴＡＢ形のパッ
ケージやバーンインテスト用のソケットにも適用できる
。この場合でも、ソケット内にインナーリード、ソケッ
ト外にアウターリードが存在することになり、本発明の
範囲に包含される。In addition to the above-mentioned example, the present invention can also be applied to, for example, a TAB type package and a socket for burn-in testing. Even in this case, there will be an inner lead inside the socket and an outer lead outside the socket, which is within the scope of the present invention.
へ、発明の作用効果
本発明は、上述のように、アウターリード部に接合材は
み出し防止手段を設けているので、例えば半田による所
定の導体へのアウターリード部の接合の際、近接した隣
り合う他のアウターリード部及び導体と接続することが
なく、信頼性の高い実装が行える。しかも、上記したよ
うに信頼性の高い実装が行えるので、隣り合うアウター
リード部同士及び導体同士の間隔等も小さくでき、実装
密度も向上する。従って、信頼性及び実装密度の高いリ
ード及びパッケージを提供できる。また、上記アウター
リード部と上記導体との接合域において上記アウターリ
ード部と上記導体との少なくとも一方に接合材はみ出し
防止手段が設けられているので、上述したと同様に信頼
性及び実装密度の高い電気回路装置を提供できる。F. Effects of the Invention As described above, the present invention is provided with a means for preventing the bonding material from protruding from the outer lead portion, so that when the outer lead portion is bonded to a predetermined conductor by soldering, for example, adjacent adjacent Highly reliable mounting is possible without connection to other outer leads or conductors. Furthermore, since highly reliable mounting can be performed as described above, the distance between adjacent outer lead portions and between adjacent conductors can be reduced, and the packaging density can also be improved. Therefore, it is possible to provide leads and packages with high reliability and high packaging density. Further, in the bonding area between the outer lead portion and the conductor, at least one of the outer lead portion and the conductor is provided with a means for preventing the bonding material from protruding, so that the same reliability and packaging density as described above can be achieved. We can provide electrical circuit devices.
第１図〜第１０図は本発明の実施例を示すものであって
、
第１図はフラットハック型バクケージのアウターリード
部を導体に接合する前の状態を示す一部破断斜視図、
第２図はフラットハック型バクケージのアウターリード
部を導体に接合した後の実装状態を示す一部破断斜視図
、
第３図は第２図の１１線矢視拡大断面図、第４図はフラ
ットハック型バクケージを導体に接合した後の実装状態
を示す断面図、
第５Ａ図はアウターリード部の貫通孔の他の形状を示す
斜視図、
第５Ｂ図は第５Ａ図のＶＢ−ＶＢ線側面図、第５Ｃ図は
第５Ａ図のｖｃ−Ｖ（ＪＩＭ面図、第６人図及び第６Ｂ
図は夫々アウターリード部の貫通孔の他の形状を示す各
要部平面図、第７図は他の接合材はみ出し防止手段を示
すアウターリード部の斜視図、
第９図はピンスルーホール型のアウターリード部の断面
図、
第１０図は第９図のＸ−Ｘ線矢視断面図である。
槙１１図〜第１３図は従来例を示すものであって、
第１１図はフラットバックをパッケージのアウターリー
ド部を導体に接合した後の状態を示す一部破断斜視図、
第１２図は第１１図のＸｆｌ−Ｘｌｌ線矢視拡大断面図
、
第１３図はフラットパック凰パッケージを導体に接合し
た後の実装状態を示す断面図
である。
なお、図面に示す符号において、
１・・・・・・・・・・・・ プリント基板２・・・・
・・・・・・・・ 導体パターン３・・・・・・・・・
・・・半田（接合材）４・・・・・・・・・・・・ リ
ード
４ａ・・・・・・・・・ インナーリード部４ｂ、１７
・・・・・・ アウターリード部５・・・・・・・・・
・・・パッケージ６・・・・・・・・・・・・モールド
樹脂７・・・・・・・・・・・・ ＩＣチップ（電気部
品）９・・・・・・・・・・・・ ポンディングワイヤ
ー１０・・・・・・・・・マウント部
１２．１３．１４．３２・・・・・・貫通孔（接合材は
み出し防止手段）
１５．１６・・・・・・ 凹部又は切欠き部（接合材は
み出し防止手段）
２０・・・・・・・・・・・・
である。1 to 10 show embodiments of the present invention; FIG. 1 is a partially cutaway perspective view showing the state before the outer lead portion of the flat hack type back cage is joined to the conductor; The figure is a partially cutaway perspective view showing the mounting state after the outer lead part of the flat hack type back cage is joined to the conductor. Figure 3 is an enlarged sectional view taken along the line 11 in Figure 2. Figure 4 is the flat hack type back cage. 5A is a perspective view showing another shape of the through hole of the outer lead portion; FIG. 5B is a side view taken along the line VB-VB of FIG. 5A; Figure 5C is the vc-V of Figure 5A (JIM view, 6th figure, and 6B
The figures are plan views of the main parts showing other shapes of the through-holes in the outer lead part, FIG. 7 is a perspective view of the outer lead part showing other jointing material extrusion prevention means, and FIG. 9 is a pin-through-hole type. 10 is a sectional view taken along the line X--X in FIG. 9. Figures 11 to 13 show conventional examples. Figure 11 is a partially cutaway perspective view showing the state of the flat back after the outer lead portion of the package is joined to the conductor, and Figure 12 is a partially cutaway perspective view of the flat back after the outer lead portion of the package is joined to the conductor. FIG. 11 is an enlarged cross-sectional view taken along the line Xfl-Xll, and FIG. 13 is a cross-sectional view showing the mounting state after the flat pack package is bonded to a conductor. In addition, in the symbols shown in the drawings, 1...... Printed circuit board 2...
・・・・・・・・・ Conductor pattern 3・・・・・・・・・
...Solder (bonding material) 4...Lead 4a...Inner lead part 4b, 17
・・・・・・Outer lead part 5・・・・・・・・・
...Package 6...Mold resin 7...IC chip (electrical component) 9...・ Ponding wire 10...Mount part 12.13.14.32...Through hole (means to prevent bonding material from extruding) 15.16...Concave part or cut Notch portion (bonding material extrusion prevention means) 20...
Claims (3)
接合されるアウターリード部とを有し、前記アウターリ
ード部に接合材はみ出し防止手段が設けられているリー
ド。1. A lead comprising an inner lead part and an outer lead part joined to a predetermined conductor via a joining material, the outer lead part being provided with a means for preventing the joining material from protruding.
ド部と、所定の導体に接合材を介して接合されるアウタ
ーリード部とを有し、前記アウターリード部に接合材は
み出し防止手段が設けられているパッケージ。2. It has an electrical component, an inner lead portion to which the electrical component is connected, and an outer lead portion that is bonded to a predetermined conductor via a bonding material, and the outer lead portion is provided with a means for preventing the bonding material from protruding. package.
ド部と、所定の導体に接合材を介して接合されるアウタ
ーリード部とを有するパッケージの前記アウターリード
部が前記導体に接合され、この接合域において前記アウ
ターリード部と前記導体との少なくも一方に接合材はみ
出し防止手段が設けられている電気回路装置。3. The outer lead portion of the package has an electrical component, an inner lead portion connected to the electrical component, and an outer lead portion bonded to a predetermined conductor via a bonding material. An electric circuit device, wherein at least one of the outer lead portion and the conductor is provided with a means for preventing extrusion of a bonding material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32739888A JPH02172266A (en) | 1988-12-23 | 1988-12-23 | Lead, package and electric circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32739888A JPH02172266A (en) | 1988-12-23 | 1988-12-23 | Lead, package and electric circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02172266A true JPH02172266A (en) | 1990-07-03 |
Family
ID=18198708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32739888A Pending JPH02172266A (en) | 1988-12-23 | 1988-12-23 | Lead, package and electric circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02172266A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04131951U (en) * | 1991-05-28 | 1992-12-04 | 株式会社三社電機製作所 | Power semiconductor module |
| JPH0555438A (en) * | 1991-08-26 | 1993-03-05 | Rohm Co Ltd | Lead terminal structure of electronic component |
| JPH0533542U (en) * | 1991-10-03 | 1993-04-30 | ソニー株式会社 | Semiconductor device |
| JPH067256U (en) * | 1992-06-29 | 1994-01-28 | アイワ株式会社 | Electronic parts |
| JPH06227633A (en) * | 1991-03-08 | 1994-08-16 | Rexnord Corp | Module type conveyor chain connection structure of open hinge pin |
| JP2005283450A (en) * | 2004-03-30 | 2005-10-13 | Nagano Keiki Co Ltd | Pressure sensor and its manufacturing method |
| JP2016127205A (en) * | 2015-01-07 | 2016-07-11 | Ｎｔｔエレクトロニクス株式会社 | Flexible printed wiring board and packaging method for the same |
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|---|---|---|---|---|
| JPS62166552A (en) * | 1986-01-18 | 1987-07-23 | Mitsubishi Electric Corp | Package structure for electronic component |
| JPS6315034B2 (en) * | 1980-06-19 | 1988-04-02 | Satake Eng Co Ltd |
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| JPS6315034B2 (en) * | 1980-06-19 | 1988-04-02 | Satake Eng Co Ltd | |
| JPS62166552A (en) * | 1986-01-18 | 1987-07-23 | Mitsubishi Electric Corp | Package structure for electronic component |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06227633A (en) * | 1991-03-08 | 1994-08-16 | Rexnord Corp | Module type conveyor chain connection structure of open hinge pin |
| JPH04131951U (en) * | 1991-05-28 | 1992-12-04 | 株式会社三社電機製作所 | Power semiconductor module |
| JPH0555438A (en) * | 1991-08-26 | 1993-03-05 | Rohm Co Ltd | Lead terminal structure of electronic component |
| JPH0533542U (en) * | 1991-10-03 | 1993-04-30 | ソニー株式会社 | Semiconductor device |
| JPH067256U (en) * | 1992-06-29 | 1994-01-28 | アイワ株式会社 | Electronic parts |
| JP2005283450A (en) * | 2004-03-30 | 2005-10-13 | Nagano Keiki Co Ltd | Pressure sensor and its manufacturing method |
| JP2016127205A (en) * | 2015-01-07 | 2016-07-11 | Ｎｔｔエレクトロニクス株式会社 | Flexible printed wiring board and packaging method for the same |
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